[DAGCombiner] try to form test+set out of shift+mask patterns

Authored by spatel on Mon, Sep 2, 7:52 AM.


[DAGCombiner] try to form test+set out of shift+mask patterns

The motivating bugs are:

As discussed there, we could view this as a failure of IR canonicalization,
but then we would need to implement a backend fixup with target overrides
to get this right in all cases. Instead, we can just view this as a codegen
opportunity. It's not even clear for x86 exactly when we should favor
test+set; some CPUs have better theoretical throughput for the ALU ops than

This patch is made more complicated than I expected because there's an early
DAGCombine for 'and' that can change types of the intermediate ops via

Differential Revision: https://reviews.llvm.org/D66687

llvm-svn: 370668