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[RISCV] Add support for rev8 and orc.b to Zbb.

Authored by craig.topper on Jan 22 2021, 12:07 PM.

Description

[RISCV] Add support for rev8 and orc.b to Zbb.

These instructions use a portion of the encodings for grevi and
gorci. The full encodings are only supported with Zbp. Note,
rev8 has a different encoding between rv32 and rv64.

Zbb is closer to being finalized that Zbp which has motivated
some decisions in this patch.

I'm treating rev8 and orc.b as separate instructions when
either Zbb or Zbp is enabled. This allows us to print to suggest
that either feature needs to be enabled to support these mnemonics.
I had tried to put HasStdExtZbbAndNotZbp on the Zbb instructions,
but that caused a diagnostic that said Zbp is required if neither
feature is enabled. We should really mention Zbb since its closer
to final.

This does require extra isel patterns for the different cases so
that bswap will always print as rev8 in assembly listing since
we can't use an InstAlias.

llvm-objdump disassembling should always pick the rev8 or orc.b
instructions. llvm-mc parsing and printing text will not convert
the grevi/gorci spellings to rev8/gorc.b. We could probably fix
this with a special case in processInstruction in the assembly
parser if it its important.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94944

Details

Committed
craig.topperJan 22 2021, 12:49 PM
Reviewer
asb
Differential Revision
D94944: [RISCV] Add support for rev8 and orc.b to Zbb.
Parents
rG3c94cee63b40: [RISCV] Add zext.h instruction to Zbb.
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