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[RISCV] implement li pseudo instruction

Authored by asb on Apr 17 2018, 2:56 PM.

Description

[RISCV] implement li pseudo instruction

The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering
and is similar to the expansion performed by the GNU Assembler.

Differential Revision: https://reviews.llvm.org/D41949
Patch by Mario Werner.

llvm-svn: 330224

Details

Committed
asbApr 17 2018, 2:56 PM
Differential Revision
D41949: [RISCV] implement li pseudo instruction
Parents
rG09e0e2e656df: COFF: Merge .idata, .didat and .edata into .rdata by default.
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