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[AArch64] Prevent spilling between ldxr/stxr pairs

Authored by LemonBoy on May 1 2021, 8:13 AM.

Description

[AArch64] Prevent spilling between ldxr/stxr pairs

Apply the same logic used to check if CMPXCHG nodes should be expanded
at -O0: the register allocator may end up spilling some register in
between the atomic load/store pairs, breaking the atomicity and possibly
stalling the execution.

Fixes PR48017

Reviewed By: efriedman

Differential Revision: https://reviews.llvm.org/D101163

Details

Committed
LemonBoyMay 1 2021, 8:17 AM
Differential Revision
D101163: [AArch64] Prevent spilling between ldxr/stxr pairs
Parents
rG87f017d69f5f: [SCEV] Add tests for and/or loop guards (NFC)
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