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[ARM] Add sign and zero extend patterns for MVE

Authored by dmgreen on Jul 13 2019, 8:43 AM.

Description

[ARM] Add sign and zero extend patterns for MVE

The vmovlb instructions can be uses to sign or zero extend vector registers
between types. This adds some patterns for them and relevant testing. The
VBICIMM generation is also put behind a hasNEON check (as is already done for
VORRIMM).

Code originally by David Sherwood.

Differential Revision: https://reviews.llvm.org/D64069

llvm-svn: 366008

Details

Committed
dmgreenJul 13 2019, 8:43 AM
Differential Revision
D64069: [ARM] Add sign and zero extend patterns for MVE
Parents
rGf6ce7ddecbc5: Template-related improvements to Visual Studio visualizers
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