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[RISCV] Switch to the Machine Scheduler

Authored by luismarques on Sep 17 2019, 4:15 AM.

Description

[RISCV] Switch to the Machine Scheduler

Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

llvm-svn: 372106

Details

Committed
luismarquesSep 17 2019, 4:15 AM
Differential Revision
D66973: [RISCV] Switch to the Machine Scheduler
Parents
rG3ab9e8b81858: [Attributor][Fix] Initialize the cache prior to using it
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