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[RISCV] Add zext.h instruction to Zbb.

Authored by craig.topper on Jan 22 2021, 11:58 AM.

Description

[RISCV] Add zext.h instruction to Zbb.

zext.h uses the same encoding as pack rd, rs, x0 in rv32 and
packw rd, rs, x0 in rv64. Encodings without x0 as the second source
are not valid in Zbb.

I've added two new instructions with these specific encodings with
predicates that enable them when either Zbb or Zbp is enabled.

The pack spelling will only be accepted with Zbp. The disassembler
will use the zext.h instruction when either feature is enabled.

Using the pack spelling will print as pack when llvm-mc is
emitting text. We could fix this with some custom code in
processInstruction if this is important, but I'm not sure it is.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94818

Details

Committed
craig.topperJan 22 2021, 12:49 PM
Reviewer
asb
Differential Revision
D94818: [RISCV] Add zext.h instruction to Zbb.
Parents
rG83c92fdeda6b: [RISCV] Move pack instructions to Zbp extension only.
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