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[RISCV] Expand unaligned fixed-length vector memory accesses

Authored by frasercrmck on May 14 2021, 5:56 AM.

Description

[RISCV] Expand unaligned fixed-length vector memory accesses

RVV vectors must be aligned to their element types, so anything less is
unaligned.

For regular loads and stores, our custom-lowering of fixed-length
vectors meant that we opted out of LegalizeDAG's built-in unaligned
expansion. This patch adds that logic in to our custom lower function.

For masked intrinsics, we declare that anything unaligned is not legal,
leaving the ScalarizeMaskedMemIntrin pass to do the expansion for us.

Note that neither of these methods can handle the expansion of
scalable-vector memory ops, so those cases are left alone by this patch.
Scalable loads and stores already go through expansion by default but
hit an assertion, and scalable masked intrinsics will silently generate
incorrect code. It may be prudent to return an error in both of these
cases.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D102493

Details

Committed
frasercrmckJun 2 2021, 1:27 AM
Reviewer
craig.topper
Differential Revision
D102493: [RISCV] Expand unaligned fixed-length vector memory accesses
Parents
rG5f25145306e7: [flang] Add tests for REPEAT. NFC
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