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This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling…

Authored by Suyog Sarda <suyog.sarda@samsung.com> on Dec 12 2014, 4:53 AM.

Description

This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads, and vectorizes it.

Test case :

float hadd(float* a) {
    return (a[0] + a[1]) + (a[2] + a[3]);
 }

AArch64 assembly before patch :

       ldp	s0, s1, [x0]
	ldp	s2, s3, [x0, #8]
	fadd	s0, s0, s1
	fadd	s1, s2, s3
	fadd	s0, s0, s1
	ret

AArch64 assembly after patch :

       ldp	d0, d1, [x0]
	fadd	v0.2s, v0.2s, v1.2s
	faddp	s0, v0.2s
	ret

Reviewed Link : http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141208/248531.html

llvm-svn: 224119

Event Timeline

Suyog Sarda <suyog.sarda@samsung.com> committed rG384095e65c9d: This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling… (authored by Suyog Sarda <suyog.sarda@samsung.com>).Dec 12 2014, 4:53 AM