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[AArch64] Improve codegen of volatile load/store of i128

Authored by vhscampos on Oct 28 2019, 6:44 AM.

Description

[AArch64] Improve codegen of volatile load/store of i128

Summary:
Instead of generating two i64 instructions for each load or store of a
volatile i128 value (two LDRs or STRs), now emit a single LDP or STP.

Reviewers: labrinea, t.p.northover, efriedma

Reviewed By: efriedma

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69559

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