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[PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins

Authored by Conanap on Aug 28 2020, 9:27 AM.

Description

[PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins

This patch implements the builtins for Vector Load with Zero and Signed Extend Builtins (lxvr_x for b, h, w, d), and adds the appropriate test cases for these builtins. The builtins utilize the vector load instructions itnroduced with ISA 3.1.

Differential Revision: https://reviews.llvm.org/D82502#inline-797941

Details

Committed
ConanapAug 28 2020, 9:28 AM
Differential Revision
D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend
Parents
rGfabd4c1ae1fc: [Statepoint] Always spill base pointer.
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