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[X86][SSE] Add support for <64 x i1> bool reduction

Authored by RKSimon on Sun, Sep 8, 4:46 AM.

Description

[X86][SSE] Add support for <64 x i1> bool reduction

This generalizes the existing <32 x i1> pre-AVX2 split code to support reductions from <64 x i1> as well, we can probably generalize to any larger pow2 case in the future if the (unlikely) need ever arises.

We still need to tweak combineBitcastvxi1 to improve AVX512F codegen as its assumes vXi1 types should be handled on the mask registers even when they aren't legal.

Differential Revision: https://reviews.llvm.org/D67070

llvm-svn: 371328

Details

Committed
RKSimonSun, Sep 8, 4:46 AM
Differential Revision
D67070: [X86][SSE] Add support for <64 x i1> bool reduction
Parents
rGacf81f4210cd: [StackMap] Current stackmap version should be 3. NFC.
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