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[AArch64] Improve codegen for inverted overflow checking intrinsics

Authored by aemerson on Oct 9 2017, 8:15 AM.

Description

[AArch64] Improve codegen for inverted overflow checking intrinsics

E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an
intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the
inverted condition code for the CSEL.

rdar://28495949

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D38160

llvm-svn: 315205

Details

Committed
aemersonOct 9 2017, 8:15 AM
Reviewer
kristof.beyls
Differential Revision
D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics
Parents
rG8557e2940813: [x86] regenerate test checks; NFC
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