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[AArch64] Optimize instruction selection for certain vector shuffles

Authored by miyuki on Aug 27 2020, 3:06 AM.

Description

[AArch64] Optimize instruction selection for certain vector shuffles

This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:

shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>

is essentially:

shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D86225

Details

Committed
miyukiAug 27 2020, 3:06 AM
Reviewer
dmgreen
Differential Revision
D86225: [AArch64] Optimize instruction selection for certain vector shuffles
Parents
rG8191603dc42a: [NFC][ValueTracking] Fix typo in test
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