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[DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) ->…

Authored by RKSimon on Mar 18 2021, 8:34 AM.

Description

[DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x)

Extend this to support ComputeNumSignBits of the (used) source vector elements so that we can handle more than just the case where we're sext_in_reg from the source element signbit.

Noticed while investigating the poor codegen in D98587.

Details

Committed
RKSimonMar 18 2021, 8:34 AM
Parents
rG283799157e50: [mlir][linalg] Add support for memref inputs/outputs for `linalg.tiled_loop`.
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craig.topper added inline comments.
/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
11801

I'm not sure this is correct if the inner node is ISD::ZERO_EXTEND_VECTOR_INREG. If ExVTBits is greater than N00Bits the "(N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) < ExtVTBits)" portion is always true. So the ZERO_EXTEND_VECTOR_INREG would be replaced by SIGN_EXTEND_VECTOR_INREG.

The original ZERO_EXTEND_VECTOR_INREG would have zero extended from N00. then the SIGN_EXTEND_INREG should have been a NOP. So we should just have ZERO_EXTEND_VECTOR_INREG.

Maybe the earlier "If the input is already sign extended, just drop the extension." prevents us from encountering this case.

RKSimon added inline comments.Mar 20 2021, 6:49 AM
/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
11801

I think you might be right - I'll double check later today.