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[InstCombine] improve demanded bits analysis of left-shifted operand

Authored by spatel on May 3 2021, 5:17 AM.

Description

[InstCombine] improve demanded bits analysis of left-shifted operand

If we don't demand high bits, then we also don't care about those
high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling,
but I haven't looked at that yet.

https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF

Differential Revision: https://reviews.llvm.org/D101489

Details

Committed
spatelMay 3 2021, 5:39 AM
Differential Revision
D101489: [InstCombine] improve demanded bits analysis of left-shifted operand
Parents
rGab7316f1c64c: [clang] Spell correct variable
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