[RISCV] Add MachineInstr immediate verification

Authored by luismarques on Oct 16 2019, 8:06 AM.


[RISCV] Add MachineInstr immediate verification

This patch implements the TargetInstrInfo::verifyInstruction hook for RISC-V. Currently the hook verifies the machine instruction's immediate operands, to check if the immediates are within the expected bounds. Without the hook invalid immediates are not detected except when doing assembly parsing, so they are silently emitted (including being truncated when emitting object code).

The bounds information is specified in tablegen by using the OperandType definition, which sets the MCOperandInfo's OperandType field. Several RISC-V-specific immediate operand types were created, which extend the MCInstrDesc's OperandType enum.

To have the hook called with llc pass it the -verify-machineinstrs option. For Clang add the cmake build config -DLLVM_ENABLE_EXPENSIVE_CHECKS=True, or temporarily patch TargetPassConfig::addVerifyPass.

Review concerns:

  • The patch adds immediate operand type checks that cover at least the base ISA. There are several other operand types for the C extension and one type for the F/D extensions that were left out of this initial patch because they introduced further design concerns that I felt were best evaluated separately.
  • Invalid register classes (e.g. passing a GPR register where a GPRC is expected) are already caught, so were not included.
  • This design makes the more abstract MachineInstr verification depend on MC layer definitions, which arguably is not the cleanest design, but is in line with how things are done in other parts of the target and LLVM in general.
  • There is some duplication of logic already present in the MCOperandPredicates. Since the MachineInstr and MCInstr notions of immediates are fundamentally different, this is currently necessary.

Reviewers: asb, lenary

Reviewed By: lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67397

llvm-svn: 375006


luismarquesOct 16 2019, 8:06 AM
Differential Revision
D67397: [RISCV] Add MachineInstr immediate verification
rG2d6a2303f83d: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands