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[RISCV] Add RVV insertelt/extractelt scalable-vector patterns

Authored by frasercrmck on Jan 11 2021, 9:42 AM.

Description

[RISCV] Add RVV insertelt/extractelt scalable-vector patterns

Original patch by @rogfer01.

This patch adds support for insertelt and extractelt operations on
scalable vectors.

Special care must be taken on RV32 when dealing with i64 vectors as
there are no straightforward ways to insert a 64-bit element without a
register of that size. To that end, both are custom-lowered to different
sequences.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94615

Details

Committed
frasercrmckJan 25 2021, 2:03 PM
Reviewer
craig.topper
Differential Revision
D94615: [RISCV] Add RVV insertelt/extractelt scalable-vector patterns
Parents
rG1ac36b34db81: Fix 0f0462cacf34aa88ae71a13c4199c1b1e70f3ee6
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