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[ARM] CSEL generation

Authored by dmgreen on Jul 14 2020, 2:04 AM.

Description

[ARM] CSEL generation

This adds a peephole optimisation to turn a t2MOVccr that could not be
folded into any other instruction into a CSEL on 8.1-m. The t2MOVccr
would usually be expanded into a conditional mov, that becomes an IT;
MOV pair. We can instead generate a CSEL instruction, which can
potentially be smaller and allows better register allocation freedom,
which can help reduce codesize. Performance is more variable and may
depend on the micrarchitecture details, but initial results look good.
If we need to control this per-cpu, we can add a subtarget feature as we
need it.

Original patch by David Penry.

Differential Revision: https://reviews.llvm.org/D83566

Details

Committed
dmgreenJul 16 2020, 3:10 AM
Differential Revision
D83566: [ARM] CSEL generation
Parents
rG2762da0a16a7: [SVE][CodeGen] Legalisation of masked loads and stores
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