HomePhabricator

[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling…

Authored by asb on Apr 11 2018, 10:34 PM.

Description

[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv

fadd.d is required in order to force floating point registers to be used in
test code, as parameters are passed in integer registers in the soft float
ABI.

Much of this patch is concerned with support for passing f64 on RV32D with a
soft-float ABI. Similar to Mips, introduce pseudoinstructions to build an f64
out of a pair of i32 and to split an f64 to a pair of i32. BUILD_PAIR and
EXTRACT_ELEMENT can't be used, as a BITCAST to i64 would be necessary, but i64
is not a legal type.

llvm-svn: 329871

Details

Committed
asbApr 11 2018, 10:34 PM
Parents
rGbedca0b41bec: Test commit access
Branches
Unknown
Tags
Unknown