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[ARM] Add FP16 vector insert/extract patterns

Authored by miyuki on Jun 4 2019, 2:39 AM.

Description

[ARM] Add FP16 vector insert/extract patterns

This change adds two FP16 extraction and two insertion patterns
(one per possible vector length).
Extractions are handled by copying a Q/D register into one of VFP2
class registers, where single FP32 sub-registers can be accessed. Then
the extraction of even lanes are simple sub-register extractions
(because we don't care about the top parts of registers for FP16
operations). Odd lanes need an additional VMOVX instruction.

Unfortunately, insertions cannot be handled in the same way, because:

  • There is no instruction to insert FP16 into an even lane (VINS only works with odd lanes)
  • The patterns for odd lanes will have a form of a DAG (not a tree), and will not be implementable in pure tablegen

Because of this insertions are handled in the same way as 16-bit
integer insertions (with conversions between FP registers and GPRs
using VMOVHR instructions).

Without these patterns the ARM backend would sometimes fail during
instruction selection.

This patch also adds patterns which combine:

  • an FP16 element extraction and a store into a single VST1 instruction
  • an FP16 load and insertion into a single VLD1 instruction

Differential Revision: https://reviews.llvm.org/D62651

llvm-svn: 362482

Details

Committed
miyukiJun 4 2019, 2:39 AM
Differential Revision
D62651: [ARM] Add FP16 vector insert/extract patterns
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rG4ef0f82b71de: [clangd] Support offsets for parameters in signatureHelp
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