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[mips] Fix lowering load/store instruction in PIC case

Authored by atanasyan on Aug 1 2019, 9:04 AM.

Description

[mips] Fix lowering load/store instruction in PIC case

If an operand of the lw/sw instructions is a symbol, these instructions
incorrectly lowered using not-position-independent chain of commands.
For PIC code we should use lw/addiu instructions with the R_MIPS_GOT16
and R_MIPS_LO16 relocations respectively. Instead of that LLVM generates
position dependent code with the R_MIPS_HI16 and R_MIPS_LO16
relocations.

This patch provides a fix for the bug by handling PIC case separately in
the MipsAsmParser::expandMemInst. The main idea is to generate a chain
of PIC instructions to load a symbol address into a register and then
load the address content.

The fix is not optimal and does not fix all PIC-related problems. This
is a task for subsequent patches.

Differential Revision: https://reviews.llvm.org/D65524

llvm-svn: 367580

Details

Committed
atanasyanAug 1 2019, 9:04 AM
Differential Revision
D65524: [mips] Fix lowering load/store instruction in PIC case
Parents
rG66ce04f26113: [InstCombine] add tests with 'ne' predicates; NFC
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