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[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.

Authored by simon_tatham on Jun 27 2019, 5:40 AM.

Description

[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.

In the CSEL Rd,Rm,Rn instruction family (also including CSINC, CSINV
and CSNEG), the architecture lists it as CONSTRAINED UNPREDICTABLE
(i.e. SoftFail) to use SP in the Rd or Rm slot, but outright illegal
to use it in the Rn slot, not least because some encodings of that
form are used by MVE instructions such as UQRSHLL.

MC was treating all three slots the same, as SoftFail. So the only
reason UQRSHLL was disassembled correctly at all was because the MVE
decode table is separate from the Thumb2 one and takes priority; if
you turned off MVE, then encodings such as [0x5f,0xea,0x0d,0x83]
would disassemble as spurious CSELs.

Fixed by inventing another version of the GPRwithZR register class,
which disallows SP completely instead of just SoftFailing it.

Reviewers: DavidSpickett, ostannard

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63862

llvm-svn: 364531

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