@dmgreen I think the right solution to this problem is to come up with some sort of cost model here so that these things are handled appropriately. But I would like your or someone's input on this as well. Let me know.

I forgot to update the differential link in the commit but this patch was merged as part of (https://github.com/llvm/llvm-project/commit/726785b1594c6b567c5c8ddd59075aee726590c6)

I noticed there was another instance of vbsl being reported recently in https://github.com/llvm/llvm-project/issues/62642. Hopefully it can be addresses via extra optimizations too.

address reviewer comments

More concise pattern matching

I agree that it's not ideal to have target-specific logic in this file.

add test

tests coming

Address reviewer comments

clang-format and remove print statement

[AArch64] Change shouldSinkOperand to allow bitselect instructions

[AArch64][InstCombine] Bail out for bitselect instructions

I agree. I changed the implementation to not introduce the intrinsic. I will need another change in InstCombine to handle case #1 mentioned on github bug report. I will have separate patch for it changing InstCombine. Thanks

Change shouldSinkOperand to allow backend to generate bitselect instructions

I tested this and this does fix the issue with older swig version. Thanks for working on it.

[Bazel] Port 78e172fc92e74be3347409e4a67432c97f071818

Fix Bazel build

No reason. It just needs blessing of a reviewer.