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lizhijin (lizhijin)
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User Since
Apr 23 2022, 2:02 AM (74 w, 4 d)

Recent Activity

Jul 6 2023

lizhijin added a comment to D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.

ping

Jul 6 2023, 11:19 PM · Restricted Project, Restricted Project
lizhijin retitled D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS from [AArch64] Add patterns to support indexed FMLA/FMLS to [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.
Jul 6 2023, 11:19 PM · Restricted Project, Restricted Project

Jul 5 2023

lizhijin requested review of D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.
Jul 5 2023, 6:39 PM · Restricted Project, Restricted Project

Apr 6 2023

lizhijin added a comment to D147619: [SVE] Add patterns to delete redundant sel instructions.

The aim is to combine svadd_x and svsel intrinsics.
As we can see gcc has patterns to combine sel and some other instructions, while clang can't.
gcc : https://godbolt.org/z/G4aYefG51
clang : https://godbolt.org/z/G4aYefG51

Apr 6 2023, 11:18 PM · Restricted Project, Restricted Project

Apr 5 2023

lizhijin requested review of D147619: [SVE] Add patterns to delete redundant sel instructions.
Apr 5 2023, 8:03 AM · Restricted Project, Restricted Project

Mar 13 2023

lizhijin added a comment to D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.

ping

Mar 13 2023, 6:17 PM · Restricted Project, Restricted Project

Mar 11 2023

lizhijin updated the diff for D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
Mar 11 2023, 6:32 PM · Restricted Project, Restricted Project

Mar 8 2023

lizhijin abandoned D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions.
Mar 8 2023, 5:21 PM · Restricted Project, Restricted Project, Restricted Project
lizhijin updated the summary of D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
Mar 8 2023, 12:16 AM · Restricted Project, Restricted Project
lizhijin requested review of D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
Mar 8 2023, 12:12 AM · Restricted Project, Restricted Project

Feb 9 2023

lizhijin added a comment to D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..

@lizhijin: In case there's a misunderstanding I just wanted to say your patch has been accepted and is good to land. Sometimes patches are accepted with a few extra comments which you're trusted to consider before landing a patch (i.e. there's no need to wait for the patch to be accepted again). There's no real rule but typically I just wait a day after acceptance before landing a patch (with any suggested minor modifications) in order to give other reviewers a chance to comment.

Feb 9 2023, 3:18 AM · Restricted Project, Restricted Project, Restricted Project

Feb 8 2023

lizhijin updated the summary of D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Feb 8 2023, 10:48 PM · Restricted Project, Restricted Project, Restricted Project
lizhijin updated the diff for D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..

Rebase

Feb 8 2023, 10:38 PM · Restricted Project, Restricted Project, Restricted Project
lizhijin updated the diff for D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..

Update code format.

Feb 8 2023, 6:41 AM · Restricted Project, Restricted Project, Restricted Project

Feb 7 2023

lizhijin retitled D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes. from [SVE] Add intrinsics for shift operations that explicitly undefine the result for inactive lanes. to [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Feb 7 2023, 5:27 PM · Restricted Project, Restricted Project, Restricted Project
lizhijin requested review of D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Feb 7 2023, 7:21 AM · Restricted Project, Restricted Project, Restricted Project

Feb 2 2023

lizhijin added a comment to D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions.

ping

Feb 2 2023, 4:07 AM · Restricted Project, Restricted Project, Restricted Project

Jan 28 2023

lizhijin updated the diff for D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions.
Jan 28 2023, 7:31 AM · Restricted Project, Restricted Project, Restricted Project

Jan 19 2023

lizhijin requested review of D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions.
Jan 19 2023, 9:20 AM · Restricted Project, Restricted Project, Restricted Project

Jan 18 2023

lizhijin abandoned D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions.

This patch is superseded by D125016 and this one can be abandoned.

Jan 18 2023, 5:34 PM · Restricted Project, Restricted Project

May 18 2022

lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
May 18 2022, 10:25 AM · Restricted Project, Restricted Project

May 16 2022

lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
May 16 2022, 9:47 AM · Restricted Project, Restricted Project

May 13 2022

lizhijin updated the summary of D125016: [LV] Widen freeze instead of scalarizing it.
May 13 2022, 12:42 AM · Restricted Project, Restricted Project

May 10 2022

lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
May 10 2022, 7:31 AM · Restricted Project, Restricted Project
lizhijin retitled D125016: [LV] Widen freeze instead of scalarizing it from [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions to [LV] Widen freeze instead of scalarizing it.
May 10 2022, 7:29 AM · Restricted Project, Restricted Project

May 5 2022

lizhijin added a comment to D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions.

Hi, @david-arm , I added a patch to change the strategy for vectorizing freeze instrucion, and tried to use VPWidenRecipe for freeze instruction. Can you help to review this patch : https://reviews.llvm.org/D125016

May 5 2022, 8:38 AM · Restricted Project, Restricted Project
lizhijin requested review of D125016: [LV] Widen freeze instead of scalarizing it.
May 5 2022, 8:28 AM · Restricted Project, Restricted Project

Apr 23 2022

lizhijin requested review of D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions.
Apr 23 2022, 2:24 AM · Restricted Project, Restricted Project