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User Details
- User Since
- Apr 23 2022, 2:02 AM (74 w, 4 d)
Jul 6 2023
Jul 6 2023
lizhijin added a comment to D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.
ping
lizhijin retitled D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS from [AArch64] Add patterns to support indexed FMLA/FMLS to [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.
Jul 5 2023
Jul 5 2023
lizhijin requested review of D154558: [AArch64][SVE] Add patterns to support sve indexed FMLA/FMLS.
Apr 6 2023
Apr 6 2023
lizhijin added a comment to D147619: [SVE] Add patterns to delete redundant sel instructions.
The aim is to combine svadd_x and svsel intrinsics.
As we can see gcc has patterns to combine sel and some other instructions, while clang can't.
gcc : https://godbolt.org/z/G4aYefG51
clang : https://godbolt.org/z/G4aYefG51
Apr 5 2023
Apr 5 2023
lizhijin requested review of D147619: [SVE] Add patterns to delete redundant sel instructions.
Mar 13 2023
Mar 13 2023
lizhijin added a comment to D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
ping
Mar 11 2023
Mar 11 2023
lizhijin updated the diff for D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
Mar 8 2023
Mar 8 2023
lizhijin updated the summary of D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
lizhijin requested review of D145551: [SVE] Add patterns for shift intrinsics with FalseLanesZero mode.
Feb 9 2023
Feb 9 2023
lizhijin added a comment to D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Feb 8 2023
Feb 8 2023
lizhijin updated the diff for D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Rebase
lizhijin updated the diff for D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Update code format.
Feb 7 2023
Feb 7 2023
lizhijin retitled D143499: [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes. from [SVE] Add intrinsics for shift operations that explicitly undefine the result for inactive lanes. to [SVE] Add intrinsics for logical/bitwise operations that explicitly undefine the result for inactive lanes..
Feb 2 2023
Feb 2 2023
lizhijin added a comment to D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions.
ping
Jan 28 2023
Jan 28 2023
Jan 19 2023
Jan 19 2023
Jan 18 2023
Jan 18 2023
This patch is superseded by D125016 and this one can be abandoned.
May 18 2022
May 18 2022
lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
May 16 2022
May 16 2022
lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
May 13 2022
May 13 2022
lizhijin updated the summary of D125016: [LV] Widen freeze instead of scalarizing it.
May 10 2022
May 10 2022
lizhijin updated the diff for D125016: [LV] Widen freeze instead of scalarizing it.
lizhijin retitled D125016: [LV] Widen freeze instead of scalarizing it from [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions to [LV] Widen freeze instead of scalarizing it.
May 5 2022
May 5 2022
lizhijin added a comment to D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions.
Hi, @david-arm , I added a patch to change the strategy for vectorizing freeze instrucion, and tried to use VPWidenRecipe for freeze instruction. Can you help to review this patch : https://reviews.llvm.org/D125016
lizhijin requested review of D125016: [LV] Widen freeze instead of scalarizing it.
Apr 23 2022
Apr 23 2022
lizhijin requested review of D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions.