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User Since
Nov 11 2020, 3:34 AM (92 w, 2 h)

Recent Activity

May 26 2022

guopeilin updated guopeilin.
May 26 2022, 7:57 AM

Mar 24 2022

guopeilin abandoned D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.
Mar 24 2022, 1:16 AM · Restricted Project, Restricted Project

Feb 15 2022

guopeilin committed rG064b2a6dc6c9: [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction (authored by Allen).
[DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction
Feb 15 2022, 5:40 PM
guopeilin closed D119105: [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction.
Feb 15 2022, 5:40 PM · Restricted Project

Feb 13 2022

guopeilin committed rGb2f5164deb0e: [IVDescriptors] Support FOR where we have multiple sink pointed (authored by Allen).
[IVDescriptors] Support FOR where we have multiple sink pointed
Feb 13 2022, 5:31 PM
guopeilin closed D118558: [IVDescriptors] Support FOR where we have multiple sink pointed.
Feb 13 2022, 5:31 PM · Restricted Project

Feb 6 2022

guopeilin committed rGb3b129f11f3c: [DAGCombiner][AArch64] Enhance to support for scalar CSINC (authored by Allen).
[DAGCombiner][AArch64] Enhance to support for scalar CSINC
Feb 6 2022, 6:29 PM
guopeilin closed D116915: [DAGCombiner][AArch64] Enhance to support for scalar CSINC.
Feb 6 2022, 6:29 PM · Restricted Project

Jan 11 2022

guopeilin committed rGdc01fb1d726a: [DAGCombiner][AArch64] precommit some tests for D116915 NFC (authored by Allen).
[DAGCombiner][AArch64] precommit some tests for D116915 NFC
Jan 11 2022, 10:45 PM

Jan 4 2022

guopeilin added a comment to D116442: [AArch64ISelLowering] Don't look through scalable extract_subvector when optimising DUPLANE..

LGTM! Thanks for the bug fixing

Jan 4 2022, 12:30 AM · Restricted Project

Dec 31 2021

guopeilin added a comment to D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend.

@guopeilin This doesn't really answer my question. You say that the SCEV for the wide IV at this point is {((sext i32 %arg1 to i64) + (sext i32 %arg2 to i64)),+,(sext i32 %arg2 to i64)}<nsw><%body>, which has the <nsw> flag. My baseline expectation would be that SCEVExpander will also add the nsw flag to the expanded IR (see the code around https://github.com/llvm/llvm-project/blob/015ff729cb90317e4e75cf48b1e5dd7850f0cbd0/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp#L1300-L1304). My question is why that doesn't happen because making sure SCEVExpander propagates the flag from SCEV to IR seems like the more principled way to address this problem.

Dec 31 2021, 1:13 AM · Restricted Project

Dec 29 2021

guopeilin added a comment to D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend.

Can you explain why SCEVExpander does not preserve the nowrap flag in this case? Assuming it is present on the wide IV, I would have expect it to also get expanded as such.

Sorry for the late reply. The SCEVExpander(Rewriter) is used to create the widen IV and its widenIVUse(). As for the IV increment, we just use the following code:

WideInc =
      cast<Instruction>(WidePhi->getIncomingValueForBlock(LatchBlock));

Of course in this way, we cannot preserve the nowrap flag cause both the WidePhi and the IncomingValueForBlock do not contain the flag.
I guess the reason why we don`t need to preserve this flag previously is that the AddRec is computed from the OrigPhi, which is like the following:

{((sext i32 %arg1 to i64) + (sext i32 %arg2 to i64)),+,(sext i32 %arg2 to i64)}<nsw><%body>

So, at this moment, it does not matter whether the increased instruction contains the flag because the SCEV is right.
However, during the optimization pipeline, we may call the SE->forgetLoop() to drop the cache value and recompute from scratch. At that moment, since we have lost the NSW flag, then the BackedgeTakenCount would be CouldNotCompute, which will prevent vectorizing.
With this patch, function s122 and function s172 in TSVC now can be vectorized. Following is the source code of s122:

real_t s122(struct args_t * func_args)
{
//    induction variable recognition
//    variable lower and upper bound, and stride
//    reverse data access and jump in data access
    struct{int a;int b;} * x = func_args->arg_info;
    int n1 = x->a;
    int n3 = x->b;
    initialise_arrays(__func__);
    int j, k;
#pragma clang loop vectorize(assume_safety)
    for (int nl = 0; nl < iterations; nl++) {
        j = 1;
        k = 0;
        for (int i = n1-1; i < LEN_1D; i += n3) {
            k += j;
            a[i] += b[LEN_1D - k];
        }
    }
}
Dec 29 2021, 2:04 AM · Restricted Project
guopeilin updated the diff for D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend.

fix the affected tests

Dec 29 2021, 1:05 AM · Restricted Project

Dec 24 2021

guopeilin added a comment to D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend.

With the help of nsw flag in keep-nsw-nuw-flag.ll, this loop which cannot be vectorized due to CouldNotCompute BackedgeTakenCount now can be vectorized.
We can use opt -indvars keep-nsw-nuw-flag.ll -S | opt -loop-vectorize -S to verify this.
Also, if we just use -indvars -loop-vectorize back to back, this loop can be vectorized without this patch. And I found out that the reason is that nsw flag still remains when we try to vectorize this loop. That is some cached value is reused during scalar-evolution analysis for loop-vectorize pass.
During the pipeline, we may call forgetLoop in many places, thus the cached value may be cleared. So I guess it is better to keep the nsw or nuw flags explicitly after widen IV.

Dec 24 2021, 5:49 PM · Restricted Project
guopeilin added reviewers for D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend: fhahn, efriedma, nikic, dmgreen.
Dec 24 2021, 5:32 PM · Restricted Project
guopeilin requested review of D116276: [IndVarS] Keep the nsw/nuw flags after simplifyAndExtend.
Dec 24 2021, 5:31 PM · Restricted Project

Dec 10 2021

guopeilin abandoned D113079: [InstCombine] Take arguments into consideration when simplify range check.
Dec 10 2021, 10:32 PM · Restricted Project

Nov 4 2021

guopeilin added inline comments to D113079: [InstCombine] Take arguments into consideration when simplify range check.
Nov 4 2021, 6:49 PM · Restricted Project
guopeilin updated the diff for D113079: [InstCombine] Take arguments into consideration when simplify range check.
Nov 4 2021, 6:47 PM · Restricted Project

Nov 3 2021

guopeilin added a comment to D113079: [InstCombine] Take arguments into consideration when simplify range check.

Sorry for the absence of the description.
Actually, it is a runtime error. The simplify range check optimization will change (icmp slt x, 0) | (icmp sgt x, n) into icmp ugt x, n
Now, suppose the %0 is negative, Before optimizing, we will compare the argument with 0 to see whether the argument is less than 0, if so, we will finally return shl i32 %0, 0.
However, after optimizing, we will not have this comparison, and we will finally return shl i32 %0, %and. The problem is that %and is also driven from the argument, it can be undefined cause it is a shift operation that depends on the argument. So, after optimization, we will get an undefined result.
So, I guess that if both x and n in (icmp slt x, 0) | (icmp sgt x, n) are derived from the argument, then we should be conservative.

Nov 3 2021, 1:29 AM · Restricted Project

Nov 2 2021

guopeilin requested review of D113079: [InstCombine] Take arguments into consideration when simplify range check.
Nov 2 2021, 9:03 PM · Restricted Project

Oct 15 2021

guopeilin committed rGb092dc0bb9e4: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled (authored by guopeilin).
[AArch64ISelLowering] Avoid duplane in some cases when sve enabled
Oct 15 2021, 12:35 AM
guopeilin closed D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Oct 15 2021, 12:35 AM · Restricted Project

Oct 14 2021

guopeilin updated the diff for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.

update test file

Oct 14 2021, 12:33 AM · Restricted Project

Oct 12 2021

guopeilin added inline comments to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Oct 12 2021, 10:08 PM · Restricted Project
guopeilin updated the diff for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Oct 12 2021, 10:06 PM · Restricted Project
guopeilin updated the diff for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Oct 12 2021, 8:13 PM · Restricted Project

Oct 11 2021

guopeilin added a comment to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.

pinging reviewers...

Oct 11 2021, 8:30 PM · Restricted Project

Oct 2 2021

guopeilin added inline comments to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Oct 2 2021, 10:22 PM · Restricted Project

Sep 30 2021

guopeilin added inline comments to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Sep 30 2021, 12:30 AM · Restricted Project

Sep 29 2021

guopeilin added a comment to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.

Hi @guopeilin, thanks for making the changes. I'm still a little concerned about the test case though as I'm not sure how reliable it will be over time, especially with the undef values present in the code. I did manage to reduce this test case to:

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"

define <4 x i32> @test_work_knt_val(<16 x i32>* %arg) {
entry:
  %0 = load <16 x i32>, <16 x i32>* %arg, align 256
  %shvec = shufflevector <16 x i32> %0, <16 x i32> undef, <4 x i32> <i32 14, i32 14, i32 14, i32 14>
  %1 = add <16 x i32> %0, %0
  store <16 x i32> %1, <16 x i32>* %arg, align 256
  ret <4 x i32> %shvec
}

I think the problem is that there has to be multiple uses of the loaded value (%0) in order for the DAG combine to trigger.

Sep 29 2021, 12:28 AM · Restricted Project
guopeilin updated the diff for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Sep 29 2021, 12:26 AM · Restricted Project

Sep 28 2021

guopeilin added a comment to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.

Tried to simplify the test case but failed. @david-arm

Sep 28 2021, 4:07 AM · Restricted Project
guopeilin added a comment to D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Sep 28 2021, 4:05 AM · Restricted Project
guopeilin updated the diff for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Sep 28 2021, 4:03 AM · Restricted Project

Sep 27 2021

guopeilin added reviewers for D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled: efriedma, fhahn, dmgreen, nikic.
Sep 27 2021, 1:22 AM · Restricted Project
guopeilin requested review of D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled.
Sep 27 2021, 1:18 AM · Restricted Project

Sep 11 2021

guopeilin committed rG749ddd25e901: [BitcodeReader] Delay select until all constants resolved (authored by guopeilin).
[BitcodeReader] Delay select until all constants resolved
Sep 11 2021, 3:55 AM
guopeilin closed D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 11 2021, 3:54 AM · Restricted Project

Sep 8 2021

guopeilin added inline comments to D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 8 2021, 5:20 AM · Restricted Project
guopeilin added inline comments to D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 8 2021, 5:20 AM · Restricted Project
guopeilin updated the diff for D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 8 2021, 5:19 AM · Restricted Project

Sep 7 2021

guopeilin added a comment to D109053: [BitcodeReader] Delay select until all constants resolved.

Pinging reviewers ...

Sep 7 2021, 5:14 AM · Restricted Project

Sep 6 2021

guopeilin updated the diff for D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 6 2021, 2:27 AM · Restricted Project

Sep 5 2021

guopeilin committed rG5f48c144c58f: [AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z (authored by guopeilin).
[AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z
Sep 5 2021, 8:16 PM
guopeilin closed D108755: [AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z.
Sep 5 2021, 8:16 PM · Restricted Project, Restricted Project
guopeilin updated the diff for D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 5 2021, 8:07 PM · Restricted Project
guopeilin added inline comments to D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 5 2021, 3:58 AM · Restricted Project
guopeilin updated the diff for D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 5 2021, 3:57 AM · Restricted Project

Sep 1 2021

guopeilin updated the summary of D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 1 2021, 4:40 AM · Restricted Project
guopeilin requested review of D109053: [BitcodeReader] Delay select until all constants resolved.
Sep 1 2021, 4:21 AM · Restricted Project

Aug 31 2021

guopeilin added a comment to D108755: [AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z.

LGTM

Aug 31 2021, 6:24 PM · Restricted Project, Restricted Project

Aug 27 2021

guopeilin added inline comments to D91512: [AArch64][Isel] Avoid implicit zext for SIGN_EXTEND_INREG (TRUNCATE).
Aug 27 2021, 7:23 PM · Restricted Project
guopeilin updated the diff for D91512: [AArch64][Isel] Avoid implicit zext for SIGN_EXTEND_INREG (TRUNCATE).
Aug 27 2021, 6:30 AM · Restricted Project

Aug 26 2021

guopeilin updated the diff for D91512: [AArch64][Isel] Avoid implicit zext for SIGN_EXTEND_INREG (TRUNCATE).

Pinging reviewers...

Aug 26 2021, 4:41 AM · Restricted Project
guopeilin requested review of D108755: [AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z.
Aug 26 2021, 3:57 AM · Restricted Project, Restricted Project

Aug 25 2021

guopeilin committed rG4c4dbeeeea4a: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR (authored by guopeilin).
[DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR
Aug 25 2021, 4:34 AM
guopeilin closed D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.
Aug 25 2021, 4:34 AM · Restricted Project

Aug 24 2021

guopeilin added a comment to D108451: [Sema] Avoid crash in CheckEnumConstant with contains-error expressions.

Hi, @sammccall thanks for the patch.
The precommit checks suggest that some test cases failing, could you please fix them. Thanks

Aug 24 2021, 4:53 AM · Restricted Project

Aug 23 2021

guopeilin updated the diff for D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.

Hi all!
Updata a new test case.
Function test2 will fail due to assertion of invalid offset of EXTRACT_SUBVECTOR.
Also modify the AMD test case

Aug 23 2021, 11:47 PM · Restricted Project
guopeilin added a comment to D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.

Pinging reviewers....

Aug 23 2021, 5:38 AM · Restricted Project

Aug 22 2021

guopeilin added a comment to D82657: [AST][RecoveryAST] Preserve the type by default for recovery expression..

Hi @hokein , I encounter a bug when clang parses enum and I have been recorded in https://bugs.llvm.org/show_bug.cgi?id=51554.

I added a comment on the bug and sent https://reviews.llvm.org/D108451

This is a "rough edge" between erroneous and well-formed code and I'm not totally sure it's the perfect fix, but it does seem to be robust against crashes which is definitely he biggest thing.

Aug 22 2021, 6:20 PM · Restricted Project

Aug 19 2021

guopeilin added a comment to D82657: [AST][RecoveryAST] Preserve the type by default for recovery expression..

Hi @hokein , I encounter a bug when clang parses enum and I have been recorded in https://bugs.llvm.org/show_bug.cgi?id=51554.
The source code like the following:

enum E { e = E() };
int main() {
  return 0;
}

Some error message are expected like the following:

test.cpp:1:14: error: invalid use of incomplete type 'E'
enum E { e = E() };
             ^~~
test.cpp:1:6: note: definition of 'E' is not complete until the closing '}'
enum E { e = E() };

Also, I have made some analyses like the following:

In ParseDecl.cpp:
1. llvm-10: 
   AssignedVal.get(): NULL
Aug 19 2021, 11:23 PM · Restricted Project

Aug 18 2021

guopeilin added a comment to D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.
Aug 18 2021, 4:49 AM · Restricted Project, Restricted Project

Aug 17 2021

guopeilin added a comment to D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.

This test already passes without the code change: https://godbolt.org/z/48TnbeKj1

The store is not expected, which will become unreachable after SimplifyCFG.

Right, but that is the correct outcome.
Why is it not UB to free an undef (a.k.a. any random pointer)?
It is as per the current langref: https://alive2.llvm.org/ce/z/jBqe-E

Also, i would like to note that the patch's description doesn't mention that this wants to make free(undef) non-UB.

The key point is that function free can be overload, take this test case as an example, we can overload function _ZdlPv with an empty body. So the result becomes that we call a free function which actually does not free anything. Absolutely this is not a way that free an undef.
So it is better to delete an instruction that calling an empty function with an undefined argument.
I will update this test case later, also the description.

Thanks, but this still does not sound good to me.
If you want to change semantics of free()/_ZdlPv() in such a way,
what you need to do is to mark it as nobuiltin: https://godbolt.org/z/a5P3TzG7T

Aug 17 2021, 8:50 PM · Restricted Project, Restricted Project
guopeilin updated the diff for D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.
Aug 17 2021, 8:47 PM · Restricted Project, Restricted Project
guopeilin added a comment to D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.

Hi all, I update a new patch with a much simple test case. Please review, Thanks a lot!

Aug 17 2021, 8:37 PM · Restricted Project
guopeilin updated the diff for D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.
Aug 17 2021, 8:36 PM · Restricted Project
guopeilin committed rG9cfa9b44a589: [CodeGenPrepare] The instruction to be sunk should be inserted before its user… (authored by TiehuZhang).
[CodeGenPrepare] The instruction to be sunk should be inserted before its user…
Aug 17 2021, 3:59 AM
guopeilin closed D107262: [CodeGenPrepare] The instruction to be sunk should be inserted before its user in a block.
Aug 17 2021, 3:58 AM · Restricted Project

Aug 16 2021

guopeilin committed rG9790a2a72f60: [tests] precommit tests for D107692 (authored by Allen).
[tests] precommit tests for D107692
Aug 16 2021, 10:06 PM
guopeilin abandoned D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.
Aug 16 2021, 6:59 PM · Restricted Project
guopeilin abandoned D105019: [RegisterCoalescer] Avoid coalescing erased Copy.
Aug 16 2021, 6:59 PM · Restricted Project
guopeilin abandoned D107794: [AArch64ISelLowering] Avoid sinking mul's ops in some cases.
Aug 16 2021, 6:56 PM · Restricted Project
guopeilin added a comment to D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.

This test already passes without the code change: https://godbolt.org/z/48TnbeKj1

The store is not expected, which will become unreachable after SimplifyCFG.

Right, but that is the correct outcome.
Why is it not UB to free an undef (a.k.a. any random pointer)?
It is as per the current langref: https://alive2.llvm.org/ce/z/jBqe-E

Also, i would like to note that the patch's description doesn't mention that this wants to make free(undef) non-UB.

Aug 16 2021, 6:47 AM · Restricted Project, Restricted Project
guopeilin added a comment to D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.

This test already passes without the code change: https://godbolt.org/z/48TnbeKj1

Aug 16 2021, 6:11 AM · Restricted Project, Restricted Project
guopeilin requested review of D108123: [MemoryBuiltins] Mark user defined delete as nobuiltin.
Aug 16 2021, 5:00 AM · Restricted Project, Restricted Project

Aug 11 2021

guopeilin added reviewers for D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR: fhahn, dmgreen.
Aug 11 2021, 6:21 PM · Restricted Project

Aug 9 2021

guopeilin added reviewers for D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR: craig.topper, RKSimon.
Aug 9 2021, 7:06 PM · Restricted Project
guopeilin added a comment to D107794: [AArch64ISelLowering] Avoid sinking mul's ops in some cases.

Within the CodegenPrepare::tryToSinkFreeOperands, those Ops that use in the same BB as TargetBB will be skipped.

for (Use *U : reverse(OpsToSink)) {
    auto *UI = cast<Instruction>(U->get());
    if (UI->getParent() == TargetBB || isa<PHINode>(UI))
      continue;
    ToReplace.push_back(U);
  }

Thus for the Ops shuffle and insertelement of Mul generated by shouldSinkOperands, if the shuffle is already in the same BB of Mul, we will not sink the shuffle. However, the insertelement instruction will be sink right above the Mul instruction while behind the shuffle instruction. That is illegal cause def not dominate the use.

Aug 9 2021, 7:04 PM · Restricted Project
guopeilin added reviewers for D107794: [AArch64ISelLowering] Avoid sinking mul's ops in some cases: NickGuy, dmgreen, fhahn, efriedma.
Aug 9 2021, 6:49 PM · Restricted Project
guopeilin added inline comments to D107794: [AArch64ISelLowering] Avoid sinking mul's ops in some cases.
Aug 9 2021, 6:44 PM · Restricted Project
guopeilin requested review of D107795: [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR.
Aug 9 2021, 6:38 PM · Restricted Project
guopeilin requested review of D107794: [AArch64ISelLowering] Avoid sinking mul's ops in some cases.
Aug 9 2021, 6:37 PM · Restricted Project

Jul 19 2021

guopeilin committed rGe908e063d1f9: [LoopUtils] Fix incorrect RT check bounds of loop-invariant mem accesses (authored by mdchen).
[LoopUtils] Fix incorrect RT check bounds of loop-invariant mem accesses
Jul 19 2021, 4:39 AM
guopeilin committed rGf3814ed3e942: [LV] Re-generate check lines of some fragile tests (NFC) (authored by mdchen).
[LV] Re-generate check lines of some fragile tests (NFC)
Jul 19 2021, 4:39 AM
guopeilin closed D104148: [LoopUtils] Fix incorrect RT check bounds for loop-invariant mem accesses.
Jul 19 2021, 4:39 AM · Restricted Project
guopeilin closed D105438: [LV] Re-generate check lines of some fragile tests.
Jul 19 2021, 4:39 AM · Restricted Project

Jun 28 2021

guopeilin added a reviewer for D105019: [RegisterCoalescer] Avoid coalescing erased Copy: atrick.
Jun 28 2021, 6:14 PM · Restricted Project
guopeilin added a comment to D105019: [RegisterCoalescer] Avoid coalescing erased Copy.

Sometimes the CurrList may have two identical instructions that will be coalesced later. Once the first one coalesced, it will be removed from its parent, this will make the second identical instruction become illegal at the same time which getParent will be a nullptr. In this case, we should avoid coalescing erased instruction.<br>
The test case will trigger an Assertion like the following:

llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:359: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.

Also recorded in Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=50919

Jun 28 2021, 6:07 AM · Restricted Project
guopeilin added reviewers for D105019: [RegisterCoalescer] Avoid coalescing erased Copy: stoklund, sabuasal, craig.topper.
Jun 28 2021, 6:03 AM · Restricted Project
guopeilin requested review of D105019: [RegisterCoalescer] Avoid coalescing erased Copy.
Jun 28 2021, 5:59 AM · Restricted Project

Jun 13 2021

guopeilin committed rG8449af41e5c7: [LoopVectorize] precommit pr50686.ll for D104148 (authored by mdchen).
[LoopVectorize] precommit pr50686.ll for D104148
Jun 13 2021, 10:58 PM

May 25 2021

guopeilin added a comment to D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.

Actually, this transformation doesn't take too much time. However the IR it generated is very long. And this will have a great effect on the further pass. More specifically, the expanding SCEV which replaces the variable %add.i.2.i contains thousands of operands.
So if you use opt -indvars -S, you can see the program keeps printing the IR all the time.
Besides, I use clang -O3 test.cpp and find that the program gets a segment fault with a stack dump like the followings:

May 25 2021, 6:27 AM · Restricted Project

May 24 2021

guopeilin updated the diff for D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.
May 24 2021, 6:17 AM · Restricted Project
guopeilin added a comment to D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.

I'm not a fan of this direction.
Which stack overflow are you seeing?

May 24 2021, 5:42 AM · Restricted Project
guopeilin added a comment to D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.

Why is this not already covered by the isHighCostExpansion() check?

May 24 2021, 5:35 AM · Restricted Project
guopeilin added reviewers for D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues: lebedev.ri, SjoerdMeijer, dmgreen, nikic, Meinersbur.
May 24 2021, 12:41 AM · Restricted Project
guopeilin added a comment to D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.

Details are recorded in https://bugs.llvm.org/show_bug.cgi?id=50442.

May 24 2021, 12:37 AM · Restricted Project
guopeilin requested review of D103007: [LoopUtils] Avoid expanding complicated SCEVNAry when rewriteLoopExitValues.
May 24 2021, 12:34 AM · Restricted Project