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eastig (Evgeny Astigeevich)
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User Since
Oct 14 2014, 7:04 AM (244 w, 1 d)

Recent Activity

Feb 15 2019

eastig added a comment to D56720: [MemorySSA] Add caching results of reaching LiveOnEntry MemoryDef to ClobberWalker.

FWIW, the cause of the slowdown is the usage of MemorySSA in EarlyCSE.
Here's an alternative solution: D58248.
On my machine compile time goes from ~41s to ~11s (with vixl ToT today).

Feb 15 2019, 8:58 AM · Restricted Project

Jan 16 2019

eastig added a comment to D56720: [MemorySSA] Add caching results of reaching LiveOnEntry MemoryDef to ClobberWalker.

Hi George,

Jan 16 2019, 10:15 AM · Restricted Project

Jan 15 2019

eastig added a reviewer for D56720: [MemorySSA] Add caching results of reaching LiveOnEntry MemoryDef to ClobberWalker: sanjoy.
Jan 15 2019, 7:46 AM · Restricted Project
eastig created D56720: [MemorySSA] Add caching results of reaching LiveOnEntry MemoryDef to ClobberWalker.
Jan 15 2019, 7:02 AM · Restricted Project

Nov 23 2018

eastig accepted D54742: [CodeMetrics] Don't let extends of i1 be free..

+1, LGTM
I'd like someone from the X86 world to approve this as well.

Nov 23 2018, 3:13 AM

Nov 21 2018

eastig added a comment to D54742: [CodeMetrics] Don't let extends of i1 be free..

Hi Jonas,

Nov 21 2018, 9:58 AM

Oct 31 2018

eastig added a comment to D53373: [CodeMetrics] Don't let extends of i1 be free..

Hi Jonas,

Oct 31 2018, 9:48 AM

May 14 2018

eastig added a comment to D46723: Require GCC 5.1 and LLVM 3.5 at a minimum.
In D46723#1096058, @jfb wrote:

We might need to play with _GLIBCXX_USE_CXX11_ABI=0 and the -Wabi-tag option to mitigate libstdc++ ABI issues.

Agreed. Do you have a Linux machine to try it out? I don't have a VM set up with an older distro at the moment. It would be useful to see which libstdc++ features are used by LLVM when compiled with GCC 5.1 (as well as with LLVM 3.4 when using libstdc++).

I have a machine with Ubuntu 14.04. I'll run experiments.

May 14 2018, 3:17 PM

May 11 2018

eastig added a comment to D46723: Require GCC 5.1 and LLVM 3.5 at a minimum.
In D46723#1096058, @jfb wrote:

We might need to play with _GLIBCXX_USE_CXX11_ABI=0 and the -Wabi-tag option to mitigate libstdc++ ABI issues.

Agreed. Do you have a Linux machine to try it out? I don't have a VM set up with an older distro at the moment. It would be useful to see which libstdc++ features are used by LLVM when compiled with GCC 5.1 (as well as with LLVM 3.4 when using libstdc++).

May 11 2018, 2:45 PM
eastig added a comment to D46723: Require GCC 5.1 and LLVM 3.5 at a minimum.

We might need to play with _GLIBCXX_USE_CXX11_ABI=0 and the -Wabi-tag option to mitigate libstdc++ ABI issues.

May 11 2018, 8:46 AM

Feb 27 2018

eastig added a comment to D43769: [TTI] rename getArithmeticInstructionCost() to getUnitThroughput(); NFC.

Sanjay,
Maybe it's worth to send the API change to llvm-dev as RFC?

Feb 27 2018, 12:38 PM

Feb 21 2018

eastig added a comment to D42503: libcxx: Unbreak external thread library configuration..

Just validated that it has fixed the issue.
Thank you, Peter.

Feb 21 2018, 2:04 PM
eastig added a comment to D42503: libcxx: Unbreak external thread library configuration..

Hi Peter,

Feb 21 2018, 1:28 PM
eastig added a comment to D43079: [TTI CostModel] change default cost of FP ops to 1 (PR36280).

Hi Sanjay,

Feb 21 2018, 8:00 AM

Feb 20 2018

eastig added a comment to D43079: [TTI CostModel] change default cost of FP ops to 1 (PR36280).

Hi Sanjay,

Feb 20 2018, 8:34 AM

Feb 8 2018

eastig added a comment to D42503: libcxx: Unbreak external thread library configuration..

Ping

Feb 8 2018, 1:42 PM

Jan 31 2018

eastig added a comment to D42503: libcxx: Unbreak external thread library configuration..

Ping

Jan 31 2018, 2:06 PM

Jan 30 2018

eastig added a comment to D42509: [LivePhysRegs] Preserve pristine registers in blocks with no successors..

Hi Eli,

Jan 30 2018, 5:53 AM

Jan 24 2018

eastig added a comment to D42214: libcxx: Move Windows threading support into a .cpp file..

Hi Peter,

Jan 24 2018, 2:41 AM

Jan 23 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Evgeny, I posted an alternate solution https://reviews.llvm.org/D42290. Could you please check whether it fixes your regression and do not introduce others?

Hi Sergey,
I checked it fixes regressions. Could the test I posted here be added as a regression test to D42290?

Did you check whether it introduces new regressions?
I will add. Anyway I will wait for review from Sanjoy...

Jan 23 2018, 1:40 AM

Jan 22 2018

eastig accepted D38722: Added Remarks for Loop Versioning LICM Pass.

LGTM

Jan 22 2018, 3:05 PM
eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Evgeny, I posted an alternate solution https://reviews.llvm.org/D42290. Could you please check whether it fixes your regression and do not introduce others?

Jan 22 2018, 2:24 PM

Jan 19 2018

eastig added a comment to D42263: [ARM] Fix perf regression in compare optimization..

Thanks, Evgeny! I'll fix the comment and commit it now and then continue to work on cleaning up this loop.

Jan 19 2018, 9:39 AM
eastig added a comment to D42263: [ARM] Fix perf regression in compare optimization..

Hi Joel,

Jan 19 2018, 9:32 AM

Jan 18 2018

eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

What command-line arguments are you using?

-O3 -DNDEBUG -mcpu=cortex-a9 -mthumb -fomit-frame-pointer

Jan 18 2018, 2:00 PM
eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

What command-line arguments are you using?

Jan 18 2018, 1:57 PM
eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

The example I found is in equal_data, which I assume is being inlined in make_list.

I have a (one-line) fix for that, and I'm trying to run the test suite to see what else it improves. However, I'm not seeing any changes in fourinarow, and I don't immediately see any obvious bad code in it. Do you happen to know where the regression in it was?

Jan 18 2018, 1:26 PM
eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

Thank you, Joel. The function to look at is make_list.

Jan 18 2018, 12:49 PM
eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

In SingleSource/Benchmarks/McGill/chomp the patch causes generation of subs+cmp_with_0 instead of only a subs.

Jan 18 2018, 10:00 AM
eastig added a comment to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..

The patch caused regressions in LNT benchmarks on Cortex-A9:

Jan 18 2018, 9:56 AM
eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

For "%mul86.i = mul nuw nsw i32 %p280, %p281" isSCEVExprNeverPoison return false which causes the SCEV '(%p280 * %p281)' to have SCEV::FlagAnyWrap instead of a combination of SCEV::FlagNUW and Flags, SCEV::FlagNSW.

Am I correct SCEV::FlagAnyWrap means no poisoned values? If so, this looks strange. Shouldn't it be:

As I understand this flag means have no idea, in other words may overflow.

Jan 18 2018, 3:20 AM

Jan 17 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Hi Sergey and Sanjoy,

Jan 17 2018, 11:12 AM

Jan 16 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

A reproducer:

Jan 16 2018, 2:37 PM

Jan 15 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Hi Evgeny, please let me know if you need some more deep explanation about workaround Sanjoy and I mentioned in terms of stripping nuw/nsw for instruction in case you are in LSR.

This is for the case: the regressions are urgent for you and you need some quick workaround while you are investigating why SCEV lost the poison flags.

Jan 15 2018, 1:48 PM

Jan 12 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

I have found that the patch also caused 7.31% regression in SPEC2k6 401.bzip2 on Cortex-A57 (AArch64).

Jan 12 2018, 5:58 AM

Jan 11 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Sergey,
Thank you for the initial analysis. I'll try to debug SCEV.

Jan 11 2018, 8:06 AM

Jan 10 2018

eastig added a comment to D41578: [SCEV] Do not cache S -> V if S is not equivalent of V.

Hi Sergey,

Jan 10 2018, 9:59 AM

Jan 9 2018

eastig added a comment to D38722: Added Remarks for Loop Versioning LICM Pass.

The patch looks OK to me if using std::to_string is allowed now.

Jan 9 2018, 12:13 PM

Dec 18 2017

eastig added a comment to D41324: [SLPVectorizer] Add shuffle instruction cost for jumbled load.

Regression and LNT test was successful. Bootstrap test is underway.

Hi Shahid,

Do you mean the LNT test code is back to the code before the patch D36130?

Thanks,
Evgeny

Sorry, I could not get your question.
Recently I started running these lit test, LNT test and bootstrap test to make sure build bot does not break upon commit.

Regards,
Shahid

Dec 18 2017, 8:17 AM
eastig accepted D41078: [ARM] Register the Thumb2SizeReducePass.

LGTM

Dec 18 2017, 5:17 AM
eastig added inline comments to D41078: [ARM] Register the Thumb2SizeReducePass.
Dec 18 2017, 4:19 AM
eastig added a comment to D41324: [SLPVectorizer] Add shuffle instruction cost for jumbled load.

Regression and LNT test was successful. Bootstrap test is underway.

Hi Shahid,

Dec 18 2017, 4:11 AM
eastig added a comment to D41324: [SLPVectorizer] Add shuffle instruction cost for jumbled load.
Dec 18 2017, 3:49 AM

Dec 15 2017

eastig added a comment to D36130: [SLP] Vectorize jumbled memory loads..

Hi Shahid,

These changes caused 27.7% and 30.2% regressions on an AArch64 Juno board (http://lnt.llvm.org/db_default/v4/nts/83681):

MultiSource/Benchmarks/mediabench/gsm/toast/toast: 30.20%
MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm: 27.73%

We have the same benchmarks regressed on our AArch64 boards (Cortex-A53, Cortex-A57).

-Evgeny Astigeevich
The ARM Compiler Optimisation team

Dec 15 2017, 9:30 AM

Dec 14 2017

eastig added a comment to D36130: [SLP] Vectorize jumbled memory loads..

Hi Shahid,

Dec 14 2017, 5:32 AM

Dec 5 2017

eastig added a comment to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.
$  llc -O3 test_crash.ll
llc: /home/llvm-test/tmp/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1002: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || TLI.isTypeLegal(Op.getValueType()) || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
...
Dec 5 2017, 1:43 PM
eastig added a comment to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.

Hi Nirav,

Dec 5 2017, 1:30 PM

Dec 4 2017

eastig added a comment to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.

I've disable store merges of FP constants with truncation as it's not clear what is the right behavior at the moment.

Evgeny, can you please test that this works for you?

Dec 4 2017, 1:39 PM

Dec 1 2017

eastig added a comment to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.

There are stability and correctness issues on AArch64. The similar issues might exist on other ARM targets. Could you please disable MergeConsecutiveStores for all ARM targets including AArch64?

Dec 1 2017, 1:33 PM
eastig added a comment to D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection.

These changes caused failures of AArch64 NEON Emperor tests.

Dec 1 2017, 1:26 PM
eastig added inline comments to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.
Dec 1 2017, 1:09 PM
eastig added inline comments to D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.
Dec 1 2017, 12:38 PM
eastig added a comment to D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection.

These changes caused Clang to crash when it compiled spec2006 403.gcc for AArch64. I am working on a reproducer.

Dec 1 2017, 12:35 PM
eastig accepted D40701: [ARM][AArch64][DAG] Reenable post-legalize store merge.

LGTM

Dec 1 2017, 2:00 AM

Nov 30 2017

eastig added a comment to D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection.

A reproducer:

Nov 30 2017, 2:14 PM

Nov 29 2017

eastig added a comment to D33675: [DAG] Do MergeConsecutiveStores again before Instruction Selection.

Hi Nirav,

Nov 29 2017, 9:23 AM

Nov 28 2017

eastig added inline comments to D38722: Added Remarks for Loop Versioning LICM Pass.
Nov 28 2017, 1:52 PM

Nov 22 2017

eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

@evgeny777: I'll try to find some time to look at 401.bzip2.

Nov 22 2017, 5:24 AM

Nov 9 2017

eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

401.bzip2: 5.54% code size increase

That's really strange, any idea how this could happen?

Nov 9 2017, 3:25 AM

Nov 8 2017

eastig added inline comments to D38722: Added Remarks for Loop Versioning LICM Pass.
Nov 8 2017, 8:03 AM
eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

I've got Spec2006 results for Cortex-A57:

Nov 8 2017, 3:30 AM

Nov 3 2017

eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

Cortex-A57 results from another private benchmark (50 sub-benchmarks):

Nov 3 2017, 8:28 AM
eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

Interesting. I'm guessing all TSVC reductions are due to the same function.

It's also interesting that TSVC was the code that changed the most, and had no visible performance benefits.

Nov 3 2017, 8:10 AM
eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

Not very convincing numbers. I guess efficient pipelining can make most of the difference wash away.

Nov 3 2017, 7:05 AM
eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

I've got first results of benchmark runs: the LNT test suite + a private benchmark 01. I used the latest patch.
The configuration is a Juno board Cortex-A57/A53, v8-a, AArch32, Thumb2.
Options: -O3 -mcpu=cortex-a57 -mthumb -fomit-frame-pointer
The runs passed without errors.

Nov 3 2017, 5:09 AM

Oct 31 2017

eastig added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

I'll do AArch32/AArch64 benchmarks runs on our Juno boards. It would be worth to run CTMark to check compilation time.

Oct 31 2017, 3:39 AM

Oct 27 2017

eastig added a comment to D39228: [SCEV] Enhance SCEVFindUnsafe for division.

Hi Max,

Oct 27 2017, 9:24 AM
eastig added a comment to D39228: [SCEV] Enhance SCEVFindUnsafe for division.

Hi Max,

Oct 27 2017, 3:22 AM

Oct 26 2017

eastig added a comment to D39228: [SCEV] Enhance SCEVFindUnsafe for division.

I attached


Oct 26 2017, 9:46 AM
eastig added a comment to D39228: [SCEV] Enhance SCEVFindUnsafe for division.

The benchmark source file: http://www.llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Shootout/sieve.c?view=markup

Oct 26 2017, 8:58 AM
eastig reopened D39228: [SCEV] Enhance SCEVFindUnsafe for division.

Hi,
This patch caused SingleSource/Benchmarks/Shootout/shootout-sieve regression on Arm public bots:

Oct 26 2017, 8:56 AM

Oct 14 2017

eastig added a comment to D38085: Use the basic cost if a GEP is not used as addressing mode.

The patch has caused a few regressions on Arm too. They are within 5%. We investigated some of them. For example, the unrolling is not applied. However the unrolling could figure out that some non-free GEPs are removed during optimisation. Maybe other passes have the similar problem. We currently need more precise cost model for inlining at Oz. However we started looking at the recently introduced TTI code size cost if we can use it.
At which optimisation level is the inlining affected? Could we fix the issues by updating the heuristics?

Oct 14 2017, 12:43 PM

Oct 5 2017

eastig closed D38337: Check for overflows when calculating the offset in GetGEPCost..

Thank you, Justin.

Oct 5 2017, 1:52 AM

Oct 4 2017

eastig reopened D38337: Check for overflows when calculating the offset in GetGEPCost..

Hi Justin,

Oct 4 2017, 6:05 AM

Oct 3 2017

eastig added a comment to D38085: Use the basic cost if a GEP is not used as addressing mode.

Thank you, Jun, for fixing this.
There is PR33642 with a test case when TCC_FREE is returned for non-cost free GEPs.

Oct 3 2017, 5:53 AM
eastig committed rL314787: [InlineCost, NFC] Extract code dealing with inbounds GEPs from….
[InlineCost, NFC] Extract code dealing with inbounds GEPs from…
Oct 3 2017, 5:02 AM
eastig closed D38233: [InlineCost, NFC] Extract code dealing with inbounds GEPs from CallAnalyzer::visitGetElementPtr into separate function by committing rL314787: [InlineCost, NFC] Extract code dealing with inbounds GEPs from….
Oct 3 2017, 5:02 AM
eastig added a comment to D38233: [InlineCost, NFC] Extract code dealing with inbounds GEPs from CallAnalyzer::visitGetElementPtr into separate function.

Thank you, Eli.

Oct 3 2017, 2:28 AM

Oct 2 2017

eastig added a comment to D38233: [InlineCost, NFC] Extract code dealing with inbounds GEPs from CallAnalyzer::visitGetElementPtr into separate function.

Ping

Oct 2 2017, 8:11 AM

Sep 26 2017

eastig added inline comments to D38234: [ARM] isTruncateFree fix.
Sep 26 2017, 3:30 PM

Sep 25 2017

eastig created D38233: [InlineCost, NFC] Extract code dealing with inbounds GEPs from CallAnalyzer::visitGetElementPtr into separate function.
Sep 25 2017, 5:33 AM

Sep 1 2017

eastig added a comment to D37377: [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB.

Thank you, Renato, for clarifying that.

Sep 1 2017, 6:56 AM
eastig added a comment to D37377: [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB.

As I said in D37374, please refrain from approving your own patches within minutes of posting. The community must be part of the process, and if people are not reviewing your patches as fast as you want, then there's either something wrong with the community (and we need to fix), or with your expectations.

If the problem is in the community, then the documented approach to make people care about your work is to care about theirs first. The more you review other people's patches, the more likely they are to review yours. If that doesn't work (after months), then we should discuss the problems in the dev list.

Sep 1 2017, 5:56 AM
eastig accepted D37377: [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUB.

LGTM.
BTW the issue was found during porting micropython for Cortex-M0 from GCC to Clang.

Sep 1 2017, 3:16 AM

Aug 25 2017

eastig added a comment to D36772: Unmerge GEPs to reduce register pressure on IndirectBr edges..

As this patch can affect ARM targets I am doing some benchmarking.
I've got the LNT benchmarks results for AArch64 (Cortex-A57). There is no difference in performance. I'll have got more results soon.
It's interesting to see what benchmarks has been used to measure the improvements.

Aug 25 2017, 1:00 PM
eastig added inline comments to D37087: [InlineCost] Small changes to early exit condition. NFC..
Aug 25 2017, 2:03 AM
eastig accepted D37087: [InlineCost] Small changes to early exit condition. NFC..

LGTM
Thank you, Haicheng.

Aug 25 2017, 1:58 AM

Aug 24 2017

eastig added inline comments to D37087: [InlineCost] Small changes to early exit condition. NFC..
Aug 24 2017, 3:34 AM
eastig added a comment to D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target.

Thank you, Eli.

Aug 24 2017, 3:02 AM
eastig committed rL311649: [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting….
[ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting…
Aug 24 2017, 3:01 AM
eastig closed D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target by committing rL311649: [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting….
Aug 24 2017, 3:01 AM

Aug 22 2017

eastig accepted D36748: [ARM][AArch64] Add Armv8.3-a unittests.

LGTM

Aug 22 2017, 4:57 AM

Aug 21 2017

eastig updated the diff for D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target.
  • Moved Thumb1 related code into a separate function: ARMTargetLowering::isLegalT1ScaledAddressingMode
  • Added support of the case: Scale == 2 and there is no base register
Aug 21 2017, 5:52 AM
eastig added a comment to D35888: Changed basic cost of Store operation on X86..

Just back from vacation.
LGTM.
Thank you, Elena.

Aug 21 2017, 2:01 AM

Aug 10 2017

eastig added a comment to D36234: [InstCombine] Support sext in foldLogicCastConstant.

Fixed the assertion failure in r310639. Looks like a latent bug that was always there. I added a reduced test case with the commit that doesn't rely on any sext folding.

Aug 10 2017, 11:15 AM
eastig reopened D36234: [InstCombine] Support sext in foldLogicCastConstant.

This patch causes an assertion failure on the attached test.ll. Could you please have a look at it?

Aug 10 2017, 9:13 AM
eastig accepted D36559: [ARM] Clarify legal addressing modes for ARM and Thumb2. NFC.

LGTM

Aug 10 2017, 5:40 AM

Aug 9 2017

eastig added a comment to D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target.
$ echo "int a(int x) { return *(int*)(x*2); }" | clang -x c - -S -O2 -mllvm -debug-only=codegenprepare --target=armv7--eabihf -o /dev/null
CGP: Found      local addrmode: [2*%x]
Aug 9 2017, 1:17 PM
eastig added inline comments to D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target.
Aug 9 2017, 12:49 PM
eastig updated the diff for D36467: [ARM, FIX] ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for Thumb1 target.

Added comments that negative scales are not supported in Thumb1.

Aug 9 2017, 4:44 AM