User Details
- User Since
- Aug 22 2022, 1:45 AM (56 w, 5 d)
May 4 2023
May 3 2023
Feb 16 2023
Rebased
Feb 15 2023
It is very similar to this: https://reviews.llvm.org/D132650
Jan 11 2023
- Added autogenerated checks.
- Removed notes completely.
Jan 10 2023
I found a bug in RISCV backend. Reproduction: https://godbolt.org/z/qscGYbWvr
This patch fixes it.
Nov 22 2022
Rebased and resolved merge conflicts.
Thanks! I didn't know that.
I will rebase and ask for merge.
Nov 16 2022
All fixed now. Ping for review.
rebased
Fixed formatting issues.
Nov 15 2022
I want to ping on this again
Nov 8 2022
ping
Nov 2 2022
So, after more running more spec tests in different modes (train and ref) on different RISCV boards (SiFive and THead) I got mixed results on performance. Performance increase on number on tests was insignificant while on other there was a slight decrease. On average performance declined by 0.5%. On the other hand, size reduction can be seen uniformly among all tests. On average it is 20 less bytes or 0.04% of size reduction. I think these amounts can't justify the performance cost.
Considering that some performance reductions are platform specific (like the one I mentioned in previous comment) and rely on internal architecture features, it is not seem possible to come up with general solution here. And more specialized ones will require more time and effort. And possible 0.04% code size reduction just not worth it.
What do you think?
Oct 28 2022
- Removed Operand suffixes
- Added whitespaces between definitons
Oct 27 2022
Oct 7 2022
Sorry for long silence.
I've benchmarked SPEC with llvm-test-suite on Alibaba THead machine and found out that there is slight performance downgrade with this substitution. I've isolated one case:
Aug 22 2022
Fixed missing commit