- User Since
- Apr 12 2019, 2:29 PM (30 w, 5 d)
Sat, Nov 2
Fri, Nov 1
Thu, Oct 31
I am still looking for a better solution for checking if the types are legal and the optimization can be applied.
Right now I get an integer type VT for the rem operation and I check if a type twice as wide (FVT) is legal.
// Check to see if we can do this. if (IsAfterLegalization && !isTypeLegal(FVT)) return SDValue();
On RISCV the first iteration of a 32 bit rem operation will not cause an optimization. After the next round of legalization the operations gets expanded to 64 bit and the the optimization gets applied.
Checking for both VT and FVT at the same time doesn't work since RISCV only has i64 and not i32. Thus VT and FVT are never legal at the same time.
Wed, Oct 30
Oct 10 2019
Oct 9 2019
I tested loops containing a rem operation on AArch64.
With LKK the loop body contains 3 fewer instructions.
Oct 8 2019
ARM performance could still be good in loops once the constant has been loaded.
Need to tests that.
Oct 7 2019
Oct 6 2019
A C implementation of LKK suggests that it should be possible to generate better code on AArch64.
We've got some mixed results here:
Oct 5 2019
I don't have commit access. This is my first patch.
Oct 3 2019
- put tests in separate commit
- ran tests
- fixed comment error
- updated tests
put new tests in a separate commit