llvm-exegesis Analysis Results

Triple: x86_64-unknown-linux-gnu

Cpu: bdver2

Sched Class WriteAESDecEnc contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configlatency
0
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECLASTrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESDECrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCLASTrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • AESENCrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECLASTrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESDECrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCLASTrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
  • VAESENCrr
8.19
[5.03;9.12]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
2
  • 9
  • PdFPMMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdFPMMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class PdWriteZeroLatency contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configlatency
0
  • ANDNPDrr
  • ANDNPDrr
  • ANDNPDrr
  • ANDNPDrr
  • ANDNPDrr
  • ANDNPDrr
  • ANDNPSrr
  • ANDNPSrr
  • ANDNPSrr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PANDNirr
  • MMX_PCMPGTBirr
  • MMX_PCMPGTBirr
  • MMX_PCMPGTBirr
  • MMX_PCMPGTBirr
  • MMX_PCMPGTBirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTDirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PCMPGTWirr
  • MMX_PSUBBirr
  • MMX_PSUBBirr
  • MMX_PSUBBirr
  • MMX_PSUBBirr
  • MMX_PSUBBirr
  • MMX_PSUBBirr
  • MMX_PSUBDirr
  • MMX_PSUBDirr
  • MMX_PSUBDirr
  • MMX_PSUBDirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBQirr
  • MMX_PSUBWirr
  • MMX_PSUBWirr
  • MMX_PSUBWirr
  • MMX_PSUBWirr
  • MMX_PSUBWirr
  • MMX_PSUBWirr
  • MMX_PXORirr
  • MMX_PXORirr
  • MMX_PXORirr
  • MMX_PXORirr
  • MMX_PXORirr
  • MMX_PXORirr
  • MMX_PXORirr
  • PANDNrr
  • PANDNrr
  • PANDNrr
  • PANDNrr
  • PANDNrr
  • PANDNrr
  • PANDNrr
  • PCMPGTBrr
  • PCMPGTBrr
  • PCMPGTDrr
  • PCMPGTDrr
  • PCMPGTDrr
  • PCMPGTWrr
  • PCMPGTWrr
  • PCMPGTWrr
  • PCMPGTWrr
  • PCMPGTWrr
  • PSUBBrr
  • PSUBBrr
  • PSUBBrr
  • PSUBBrr
  • PSUBDrr
  • PSUBDrr
  • PSUBDrr
  • PSUBDrr
  • PSUBDrr
  • PSUBDrr
  • PSUBDrr
  • PSUBQrr
  • PSUBQrr
  • PSUBQrr
  • PSUBQrr
  • PSUBQrr
  • PSUBWrr
  • PSUBWrr
  • PSUBWrr
  • PSUBWrr
  • PSUBWrr
  • PXORrr
  • PXORrr
  • PXORrr
  • PXORrr
  • SUB32rr
  • SUB32rr
  • SUB32rr
  • SUB32rr
  • SUB32rr
  • SUB32rr
  • SUB32rr
  • SUB64rr
  • SUB64rr
  • SUB64rr
  • VANDNPDrr
  • VANDNPSrr
  • VANDNPSrr
  • VPANDNrr
  • VPCMPGTBrr
  • VPCMPGTBrr
  • VPCMPGTBrr
  • VPSUBBrr
  • VPSUBDrr
  • VPSUBQrr
  • VPSUBWrr
  • VPSUBWrr
  • VXORPSrr
  • XOR32rr
  • XOR32rr
  • XOR32rr
  • XOR32rr
  • XOR32rr
  • XOR32rr
  • XOR32rr
  • XOR64rr
  • XOR64rr
  • XOR64rr
  • XOR64rr
  • XOR64rr
  • XOR64rr
  • XORPDrr
  • XORPDrr
  • XORPDrr
  • XORPDrr
  • XORPDrr
  • XORPSrr
  • XORPSrr
  • XORPSrr
  • XORPSrr
  • XORPSrr
  • XORPSrr
0.66
[0.52;1.09]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
1
  • 0

      Sched Class ARPL16mr_ARPL16rr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      • ARPL16rr
      1.03
      [1.03;1.05]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 100
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class WriteSystem contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • BNDMOVrr_REV
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPD
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • RDSSPQ
      • VASTART_SAVE_XMM_REGS → RCR32r1
      • VASTART_SAVE_XMM_REGS → CMOVLE32rr
      • VASTART_SAVE_XMM_REGS → RCL16rCL
      • VASTART_SAVE_XMM_REGS → RCR64r1
      • VASTART_SAVE_XMM_REGS → CMOVAE16rr
      • VASTART_SAVE_XMM_REGS → RCL8rCL
      • VASTART_SAVE_XMM_REGS → CMOVBE16rr
      • VASTART_SAVE_XMM_REGS → CMOVNE32rr
      • VASTART_SAVE_XMM_REGS → SBB64ri8
      • VASTART_SAVE_XMM_REGS → CMOVO32rr
      0.90
      [0.53;6.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 100
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class WriteBitTest contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • BT16ri8 → CMOVLE64rr
      • BT16ri8 → SBB32ri8
      • BT16ri8 → RCR8ri
      • BT16ri8 → RCR32r1
      • BT16ri8 → CMOVG64rr
      • BT16ri8 → SETNSr
      • BT16ri8 → RCL64r1
      • BT16ri8 → CMOVBE32rr
      • BT16rr → ADC32ri
      • BT16rr → SBB16rr_REV
      • BT16rr → RCR8ri
      • BT16rr → CMOVA64rr
      • BT16rr → ADC64i32
      • BT16rr → ADC64rr
      • BT16rr → RCL8ri
      • BT16rr → SETGr
      • BT16rr → CMOVG32rr
      • BT32ri8 → CMOVAE16rr
      • BT32ri8 → ADC8rr_REV
      • BT32ri8 → CMOVL16rr
      • BT32ri8 → RCR16rCL
      • BT32ri8 → CMOVBE32rr
      • BT32ri8 → SETGEr
      • BT32ri8 → SBB64rr_REV
      • BT32ri8 → CMOVNO16rr
      • BT32ri8 → CMOVBE16rr
      • BT32ri8 → CMOVNE16rr
      • BT32rr → RCL32r1
      • BT32rr → SBB32i32
      • BT32rr → SBB64rr
      • BT32rr → ADC8i8
      • BT32rr → RCL8rCL
      • BT32rr → SETNSr
      • BT32rr → SETGr
      • BT32rr → CMOVS16rr
      • BT64ri8 → SETBEr
      • BT64ri8 → LAHF
      • BT64ri8 → SBB64rr
      • BT64ri8 → CMOVNO16rr
      • BT64ri8 → ADC32rr_REV
      • BT64ri8 → CMOVGE16rr
      • BT64ri8 → RCL64rCL
      • BT64ri8 → RCR8rCL
      • BT64ri8 → RCL8r1
      • BT64rr → RCL16r1
      • BT64rr → SBB8rr
      • BT64rr → ADC32i32
      • BT64rr → SETGr
      • BT64rr → CMOV_GR8
      • BT64rr → ADC32rr
      • BT64rr → RCL16rCL
      • BT64rr → RCR8ri
      • BT64rr → RCL16rCL
      1.82
      [0.32;6.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 1
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class CPUID contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      1
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      • CPUID
      122.12
      [122.09;122.17]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 100
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class WriteCRC32 contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r32r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      • CRC32r64r8
      2.35
      [2.03;3.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      3
      • 3
      • PdEX: 4
      • PdEX01: 2
      • PdAGLU01: 2.00
      • PdEX0: 2.00
      • PdEX1: 2.00

      Sched Class CVTSD2SI64rr_Int_CVTSD2SIrr_Int_CVTTSD2SI64rr_CVTTSD2SI64rr_Int_CVTTSD2SIrr_CVTTSD2SIrr_Int_VCVTSD2SI64rr_Int_VCVTSD2SIrr_Int_VCVTTSD2SI64rr_VCVTTSD2SIrr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTSD2SI64rr_Int → VCVTSI2SDrr_Int
      • CVTSD2SI64rr_Int → CVTSI642SSrr
      • CVTSD2SIrr_Int → MOV64toPQIrr
      • CVTSD2SIrr_Int → VCVTSI2SSrr_Int
      • CVTSD2SIrr_Int → VCVTSI2SSrr_Int
      • CVTSD2SIrr_Int → VCVTSI2SSrr_Int
      • CVTSD2SIrr_Int → VMOVDI2SSrr
      • CVTSD2SIrr_Int → CVTSI642SDrr
      • CVTTSD2SI64rr → CVTSI642SDrr
      • CVTTSD2SI64rr → VCVTSI2SSrr_Int
      • CVTTSD2SI64rr_Int → CVTSI642SSrr_Int
      • CVTTSD2SI64rr_Int → CVTSI2SSrr
      • CVTTSD2SI64rr_Int → CVTSI2SSrr_Int
      • CVTTSD2SI64rr_Int → VCVTSI642SDrr
      • CVTTSD2SI64rr_Int → CVTSI2SSrr_Int
      • CVTTSD2SIrr → VMOVDI2PDIrr
      • CVTTSD2SIrr → VCVTSI2SSrr_Int
      • CVTTSD2SIrr → CVTSI2SDrr_Int
      • CVTTSD2SIrr → VMOVDI2SSrr
      • CVTTSD2SIrr_Int → VMOVDI2SSrr
      • CVTTSD2SIrr_Int → CVTSI642SSrr
      • VCVTSD2SI64rr_Int → CVTSI642SDrr_Int
      • VCVTSD2SI64rr_Int → PINSRWrr
      • VCVTSD2SI64rr_Int → PINSRBrr
      • VCVTSD2SI64rr_Int → VCVTSI642SSrr_Int
      • VCVTSD2SIrr_Int → PINSRQrr
      • VCVTSD2SIrr_Int → CVTSI642SDrr_Int
      • VCVTSD2SIrr_Int → VPINSRWrr
      • VCVTTSD2SI64rr → PINSRQrr
      • VCVTTSD2SI64rr → PINSRWrr
      • VCVTTSD2SI64rr → CVTSI2SSrr
      • VCVTTSD2SIrr → MOVDI2PDIrr
      • VCVTTSD2SIrr → CVTSI2SDrr_Int
      • VCVTTSD2SIrr → PINSRDrr
      12.58
      [11.03;13.04]
      2
      • CVTTSD2SIrr_Int → VPCMPESTRMrr
      • VCVTTSD2SI64rr → VPCMPESTRMrr
      17.54
      [17.49;17.58]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSI2SDrr_CVTSI2SDrr_Int_CVTSI642SDrr_CVTSI642SDrr_Int_VCVTSI2SDrr_VCVTSI2SDrr_Int_VCVTSI642SDrr_VCVTSI642SDrr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTSI2SDrr → VPEXTRBrr
      • CVTSI2SDrr → VMOVMSKPDrr
      • CVTSI2SDrr → VEXTRACTPSrr
      • CVTSI2SDrr → VMOVSS2DIrr
      • CVTSI2SDrr → VMOVSDto64rr
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI2SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • CVTSI642SDrr_Int
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI2SDrr_Int
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      • VCVTSI642SDrr_Int
      4.65
      [4.03;12.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 4
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSI2SSrr_CVTSI2SSrr_Int_VCVTSI2SSrr_VCVTSI2SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTSI2SSrr → PEXTRWrr_REV
      • CVTSI2SSrr → CVTTSS2SIrr_Int
      • CVTSI2SSrr → VCVTSD2SI64rr_Int
      • CVTSI2SSrr → EXTRACTPSrr
      • CVTSI2SSrr → MOVMSKPSrr
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • CVTSI2SSrr_Int
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      • VCVTSI2SSrr_Int
      5.28
      [4.03;13.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 4
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSS2SI64rr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTSS2SI64rr_Int → MOVDI2SSrr
      • CVTSS2SI64rr_Int → VCVTSI642SDrr_Int
      • CVTSS2SI64rr_Int → MOVDI2SSrr
      • CVTSS2SI64rr_Int → VCVTSI2SSrr
      • CVTSS2SI64rr_Int → PINSRWrr
      12.13
      [11.03;13.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSS2SIrr_Int_VCVTSS2SI64rr_Int_VCVTSS2SIrr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTSS2SIrr_Int → VPINSRWrr
      • CVTSS2SIrr_Int → VMOV64toPQIrr
      • CVTSS2SIrr_Int → CVTSI2SSrr
      • CVTSS2SIrr_Int → VPINSRDrr
      • CVTSS2SIrr_Int → CVTSI2SDrr_Int
      12.43
      [11.03;13.03]
      2
      • VCVTSS2SIrr_Int → VPCMPESTRMrr
      17.59
      [17.59;17.59]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSS2SI64rr_Int_CVTTSS2SI64rr_CVTTSS2SI64rr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTTSS2SI64rr → CVTSI642SSrr_Int
      • CVTTSS2SI64rr → VCVTSI2SDrr_Int
      • CVTTSS2SI64rr_Int → CVTSI642SSrr
      • CVTTSS2SI64rr_Int → VPINSRWrr
      • CVTTSS2SI64rr_Int → VMOVDI2SSrr
      • CVTTSS2SI64rr_Int → CVTSI2SSrr_Int
      12.61
      [11.03;13.03]
      2
      • CVTTSS2SI64rr_Int → VPCMPESTRMrr
      18.04
      [18.04;18.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class CVTSS2SIrr_Int_CVTTSS2SIrr_CVTTSS2SIrr_Int_VCVTSS2SI64rr_Int_VCVTSS2SIrr_Int_VCVTTSS2SI64rr_VCVTTSS2SI64rr_Int_VCVTTSS2SIrr_VCVTTSS2SIrr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • CVTTSS2SIrr → VMOV64toPQIrr
      • CVTTSS2SIrr → VCVTSI642SDrr_Int
      • CVTTSS2SIrr → PINSRBrr
      • CVTTSS2SIrr_Int → VCVTSI642SSrr_Int
      • VCVTTSS2SIrr → VCVTSI642SDrr
      • VCVTTSS2SIrr → PINSRBrr
      • VCVTTSS2SIrr_Int → PINSRBrr
      • VCVTTSS2SIrr_Int → VCVTSI642SDrr_Int
      • VCVTTSS2SIrr_Int → MOVDI2PDIrr
      • VCVTTSS2SIrr_Int → MOV64toSDrr
      • VCVTTSS2SIrr_Int → PINSRBrr
      12.31
      [11.03;13.05]
      2
      • CVTTSS2SIrr → PCMPESTRMrr
      17.24
      [17.24;17.24]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class EXTRACTPSrr_VEXTRACTPSrr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • EXTRACTPSrr → VMOV64toSDrr
      • EXTRACTPSrr → MOVDI2PDIrr
      • EXTRACTPSrr → PINSRDrr
      • EXTRACTPSrr → PCMPESTRMrr
      • EXTRACTPSrr → PINSRQrr
      • VEXTRACTPSrr → MOV64toSDrr
      11.34
      [10.03;15.86]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class MMX_CVTPS2PIirr_MMX_CVTTPS2PIirr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_CVTPS2PIirr → MMX_CVTPI2PDirr
      • MMX_CVTPS2PIirr → MMX_MOVQ2FR64rr
      • MMX_CVTPS2PIirr → MMX_CVTPI2PDirr
      • MMX_CVTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTPS2PIirr → MMX_CVTPI2PSirr
      • MMX_CVTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTPS2PIirr → MMX_CVTPI2PDirr
      • MMX_CVTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PDirr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PSirr
      • MMX_CVTTPS2PIirr → MMX_MOVQ2FR64rr
      • MMX_CVTTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PSirr
      • MMX_CVTTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PDirr
      • MMX_CVTTPS2PIirr → MMX_MOVQ2DQrr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PSirr
      • MMX_CVTTPS2PIirr → MMX_CVTPI2PSirr
      5.03
      [4.03;6.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 4
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class MMX_MOVDQ2Qrr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_MOVDQ2Qrr → MMX_MOVQ2DQrr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2DQrr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2DQrr
      • MMX_MOVDQ2Qrr → MMX_CVTPI2PDirr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVDQ2Qrr → MMX_CVTPI2PSirr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2DQrr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVDQ2Qrr → MMX_CVTPI2PDirr
      • MMX_MOVDQ2Qrr → MMX_MOVQ2DQrr
      2.93
      [2.03;5.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 2
      • PdFPMAL: 1
      • PdFPU: 1
      • PdFPU01: 1
      • PdFPMAL: 1.00
      • PdFPU0: 0.75
      • PdFPU1: 0.75
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteVecMoveX contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_MOVFR642Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVFR642Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVFR642Qrr → MMX_CVTPI2PDirr
      • MMX_MOVFR642Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVFR642Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVFR642Qrr → MMX_MOVQ2FR64rr
      • MMX_MOVFR642Qrr → MMX_CVTPI2PSirr
      • MMX_MOVFR642Qrr → MMX_CVTPI2PDirr
      • MMX_MOVFR642Qrr → MMX_CVTPI2PSirr
      • MMX_MOVFR642Qrr → MMX_MOVQ2DQrr
      • MMX_MOVQ2FR64rr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2FR64rr → MMX_CVTTPD2PIirr
      • MMX_MOVQ2FR64rr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2FR64rr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2FR64rr → MMX_CVTPD2PIirr
      • MMX_MOVQ2FR64rr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2FR64rr → MMX_CVTPD2PIirr
      • MMX_MOVQ2FR64rr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2FR64rr → MMX_CVTPS2PIirr
      • MMX_MOVQ2FR64rr → MMX_CVTTPD2PIirr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQArr_REV
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • MOVDQUrr_REV
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQArr_REV
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      • VMOVDQUrr_REV
      1.30
      [0.60;5.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 2
      • PdFPMAL: 1
      • PdFPU: 1
      • PdFPU01: 1
      • PdFPMAL: 1.00
      • PdFPU0: 0.75
      • PdFPU1: 0.75
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class MMX_MOVQ2DQrr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_MOVQ2DQrr → MMX_CVTPS2PIirr
      • MMX_MOVQ2DQrr → MMX_CVTPS2PIirr
      • MMX_MOVQ2DQrr → MMX_MOVFR642Qrr
      • MMX_MOVQ2DQrr → MMX_MOVFR642Qrr
      • MMX_MOVQ2DQrr → MMX_MOVFR642Qrr
      • MMX_MOVQ2DQrr → MMX_CVTTPD2PIirr
      • MMX_MOVQ2DQrr → MMX_MOVFR642Qrr
      • MMX_MOVQ2DQrr → MMX_CVTPD2PIirr
      • MMX_MOVQ2DQrr → MMX_MOVDQ2Qrr
      • MMX_MOVQ2DQrr → MMX_CVTPS2PIirr
      3.24
      [2.03;5.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 2
      • PdFPMAL: 1
      • PdFPU: 1
      • PdFPU01: 1
      • PdFPMAL: 1.00
      • PdFPU0: 0.75
      • PdFPU1: 0.75
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class MMX_PEXTRWrr_PEXTRWrr_PEXTRWrr_REV contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_PEXTRWrr → MMX_MOVD64rr
      • MMX_PEXTRWrr → MMX_MOVD64to64rr
      • MMX_PEXTRWrr → MMX_MOVD64to64rr
      • MMX_PEXTRWrr → MMX_PINSRWrr
      • MMX_PEXTRWrr → MMX_PINSRWrr
      • MMX_PEXTRWrr → MMX_MOVD64rr
      • MMX_PEXTRWrr → MMX_MOVD64to64rr
      • MMX_PEXTRWrr → MMX_MOVD64to64rr
      • MMX_PEXTRWrr → MMX_MOVD64rr
      • MMX_PEXTRWrr → MMX_MOVD64rr
      • PEXTRWrr → MOVDI2SSrr
      • PEXTRWrr → VMOV64toPQIrr
      • PEXTRWrr → CVTSI642SDrr
      • PEXTRWrr → MOV64toPQIrr
      • PEXTRWrr_REV → CVTSI642SSrr
      • PEXTRWrr_REV → VPCMPESTRMrr
      • PEXTRWrr_REV → PINSRDrr
      • PEXTRWrr_REV → PCMPESTRMrr
      11.15
      [10.03;16.18]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class MMX_PSUBSBirr_MMX_PSUBSWirr_MMX_PSUBUSBirr_MMX_PSUBUSWirr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSBirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBSWirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSBirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      • MMX_PSUBUSWirr
      1.29
      [0.53;2.05]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 2
      • PdFPMAL: 1
      • PdFPU: 1
      • PdFPU01: 1
      • PdFPMAL: 1.00
      • PdFPU0: 0.75
      • PdFPU1: 0.75
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteFMOVMSK contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • MOVMSKPDrr → MOV64toSDrr
      • MOVMSKPDrr → VCVTSI2SDrr_Int
      • MOVMSKPDrr → VCVTSI2SSrr_Int
      • MOVMSKPSrr → PINSRQrr
      • MOVMSKPSrr → VCVTSI2SSrr_Int
      • MOVMSKPSrr → CVTSI642SDrr
      • MOVMSKPSrr → MOVDI2PDIrr
      • VMOVMSKPDYrr → MOVDI2PDIrr
      • VMOVMSKPDrr → VMOVDI2SSrr
      • VMOVMSKPDrr → VCVTSI642SDrr_Int
      • VMOVMSKPSYrr → VCVTSI642SSrr_Int
      • VMOVMSKPSYrr → MOV64toSDrr
      • VMOVMSKPSYrr → CVTSI2SSrr_Int
      • VMOVMSKPSrr → PINSRWrr
      • VMOVMSKPSrr → CVTSI2SSrr_Int
      • VMOVMSKPSrr → VPINSRBrr
      11.47
      [10.03;12.55]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 10
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteCLMul contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      • PCLMULQDQrr
      12.73
      [12.03;13.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      5
      • 12
      • PdFPMMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdFPMMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WritePCmpEStrI contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • PCMPESTRIrr → MOV32rr
      • PCMPESTRIrr → ADC32rr
      • PCMPESTRIrr → SETPr
      • VPCMPESTRIrr → BLSMSK32rr
      • VPCMPESTRIrr → SBB64i32
      • VPCMPESTRIrr → ROR8rCL
      15.13
      [14.61;15.55]
      2
      • PCMPESTRIrr → BSR64rr
      17.28
      [17.28;17.28]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      27
      • 15
      • PdEX: 9
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPMAL: 4
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 4.50
      • PdEX0: 3.25
      • PdEX1: 2.25
      • PdFPFMA: 1.00
      • PdFPMAL: 4.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WritePCmpIStrI contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • PCMPISTRIrr → CVTSI642SSrr_Int
      • PCMPISTRIrr → CVTSI642SSrr
      • VPCMPISTRIrr → CMOV_VR256X
      • VPCMPISTRIrr → CVTSI2SSrr_Int
      • VPCMPISTRIrr → CVTSI642SSrr_Int
      11.63
      [1.53;14.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      7
      • 14
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 2
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 2.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteVecExtract contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • PEXTRBrr → CVTSI2SDrr
      • PEXTRBrr → VPCMPESTRMrr
      • PEXTRBrr → VCVTSI2SDrr
      • PEXTRDrr → VCVTSI2SDrr
      • PEXTRDrr → VCVTSI642SDrr
      • PEXTRDrr → CVTSI2SDrr_Int
      • PEXTRDrr → MOVDI2PDIrr
      • PEXTRQrr → VCVTSI642SDrr
      • PEXTRQrr → VPINSRDrr
      • PEXTRQrr → CVTSI2SDrr
      • PEXTRQrr → VMOV64toPQIrr
      • PEXTRQrr → PINSRWrr
      • PEXTRQrr → CVTSI642SDrr_Int
      • VPEXTRBrr → CVTSI642SSrr_Int
      • VPEXTRBrr → PINSRWrr
      • VPEXTRBrr → CVTSI642SSrr_Int
      • VPEXTRBrr → CVTSI642SSrr
      • VPEXTRDrr → VMOVDI2SSrr
      • VPEXTRDrr → VMOVDI2PDIrr
      • VPEXTRDrr → VPCMPESTRMrr
      • VPEXTRDrr → CVTSI2SDrr
      • VPEXTRQrr → PINSRQrr
      • VPEXTRQrr → VCVTSI642SDrr
      • VPEXTRQrr → VMOVDI2SSrr
      • VPEXTRQrr → VPINSRBrr
      • VPEXTRQrr → CVTSI2SSrr
      • VPEXTRWrr → VCVTSI2SDrr
      • VPEXTRWrr → VMOV64toPQIrr
      • VPEXTRWrr → CVTSI642SSrr
      • VPEXTRWrr_REV → PINSRWrr
      • VPEXTRWrr_REV → PINSRBrr
      • VPEXTRWrr_REV → VCVTSI642SSrr
      • VPEXTRWrr_REV → CVTSI2SSrr_Int
      • VPEXTRWrr_REV → VPINSRBrr
      • VPEXTRWrr_REV → VCVTSI642SSrr
      11.96
      [10.03;16.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteVecMOVMSK contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • PMOVMSKBrr → MOV64toPQIrr
      • PMOVMSKBrr → PINSRDrr
      • PMOVMSKBrr → VCVTSI2SDrr
      • PMOVMSKBrr → CVTSI2SDrr
      • VPMOVMSKBrr → CVTSI2SSrr_Int
      • VPMOVMSKBrr → CVTSI2SSrr
      • VPMOVMSKBrr → VPINSRDrr
      • VPMOVMSKBrr → VMOV64toSDrr
      11.53
      [10.03;12.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class WriteMicrocoded contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      2
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_32
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSB_64
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_32
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSD_64
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_32
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSQ_64
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_32
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_MOVSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      18.02
      [17.42;18.08]
      0
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_32
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSB_64
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_32
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSD_64
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_32
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSQ_64
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_32
      • REP_STOSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      • REP_STOSW_64
      16.03
      [16.03;16.20]
      5
      • REP_STOSQ_32
      • REP_STOSW_64
      18.89
      [18.77;19.01]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 100
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class SAHF contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SAHF → CMOVNP16rr
      • SAHF → CMOVE64rr
      • SAHF → SBB16i16
      • SAHF → CMOVBE16rr
      • SAHF → SETB_C32r
      • SAHF → ADC16i16
      • SAHF → CMOVG16rr
      • SAHF → CMOVBE32rr
      • SAHF → SETB_C16r
      • SAHF → SETAEr
      1.33
      [0.53;1.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 2
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class WriteSETCC contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SETAEr → TEST8i8
      • SETAEr → XADD64rr
      • SETAEr → SHRD32rri8
      • SETAEr → CMP16i16
      • SETAEr → SAR16rCL
      • SETAEr → CMP16rr_REV
      • SETAEr → OR8ri
      • SETAEr → SUB32ri
      • SETAEr → ADD64rr_REV
      • SETAEr → ROR16ri
      • SETBr → SHLD16rri8
      • SETBr → RCL32r1
      • SETBr → SBB64rr
      • SETBr → ANDN32rr
      • SETBr → TEST32i32
      • SETBr → XOR64rr_REV
      • SETBr → SBB32rr
      • SETBr → ROL8r1
      • SETBr → IMUL8r
      • SETEr → TEST64rr
      • SETEr → ROR32r1
      • SETEr → AND16rr
      • SETEr → RCL16ri
      • SETEr → BEXTRI64ri
      • SETEr → CMP64ri32
      • SETEr → TEST16i16
      • SETEr → CMP64i32
      • SETEr → SAR32rCL
      • SETGEr → XOR64i32
      • SETGEr → SUB64rr
      • SETGEr → ADD64i32
      • SETGEr → ADD64ri8_DB
      • SETGEr → ROL16rCL
      • SETGEr → MUL32r
      • SETGEr → ROL16r1
      • SETGEr → SHL64r1
      • SETGEr → BSR16rr
      • SETGEr → BLCIC32rr
      • SETGr → CMP64i32
      • SETGr → XOR16ri8
      • SETGr → BLSIC64rr
      • SETGr → TEST32rr
      • SETGr → BTS16rr
      • SETGr → ROR64ri
      • SETGr → SHR8rCL
      • SETGr → ROL32rCL
      • SETGr → ROR16r1
      • SETLEr → OR64ri8
      • SETLEr → XADD16rr
      • SETLEr → SHL8rCL
      • SETLEr → BTS64ri8
      • SETLEr → ADD32ri
      • SETLEr → CMP32ri
      • SETLEr → BLCFILL32rr
      • SETLEr → SUB64i32
      • SETLEr → XOR64rr
      • SETLr → SUB8rr
      • SETLr → ADD32ri8_DB
      • SETLr → ROR64ri
      • SETLr → TZCNT64rr
      • SETLr → BT64rr
      • SETLr → SHL64ri
      • SETLr → NEG64r
      • SETLr → DEC16r_alt
      • SETLr → SHL64ri
      • SETNEr → SHR8r1
      • SETNEr → CMP32ri8
      • SETNEr → SHRD64rrCL
      • SETNEr → POPCNT32rr
      • SETNEr → SUB64rr
      • SETNEr → SAR32ri
      • SETNEr → SAR8r1
      • SETNEr → SAR32ri
      • SETNEr → SAR32r1
      • SETNOr → POPCNT16rr
      • SETNOr → CMP16rr
      • SETNOr → RCR16r1
      • SETNOr → BTS16ri8
      • SETNOr → AND64ri32
      • SETNOr → SUB8i8
      • SETNPr → RCL8rCL
      • SETNPr → IMUL16r
      • SETNPr → PCMPESTRMrr
      • SETNPr → SBB64rr_REV
      • SETNPr → TEST16rr
      • SETNPr → SHL32rCL
      • SETNPr → OR32rr_REV
      • SETNPr → CMP64ri8
      • SETNSr → ADD16rr_DB
      • SETNSr → IDIV8r
      • SETNSr → BTC64rr
      • SETNSr → MUL64r
      • SETNSr → BLSI32rr
      • SETNSr → ADC32rr
      • SETOr → DEC8r
      • SETOr → BT64rr
      • SETOr → SUB64ri8
      • SETOr → ADC16i16
      • SETOr → OR16ri8
      • SETOr → AND32i32
      • SETOr → SUB64i32
      • SETOr → IMUL64r
      • SETOr → IMUL64rr
      • SETPr → ROR64ri
      • SETPr → IMUL64rri32
      • SETPr → ROR8rCL
      • SETPr → ROR16rCL
      • SETPr → AND32ri
      • SETPr → TEST8ri
      • SETPr → BLSR32rr
      • SETPr → ADC8rr_REV
      • SETPr → ROR32rCL
      • SETSr → SBB32ri8
      • SETSr → IMUL16r
      • SETSr → BTR64ri8
      • SETSr → CMP64rr_REV
      • SETSr → BTR64ri8
      • SETSr → SHR32rCL
      • SETSr → BTC32ri8
      • SETSr → SBB64rr
      • SETSr → XADD64rr
      2.48
      [0.53;15.10]
      5
      • SETLEr → RCR64rCL
      19.09
      [19.09;19.09]
      2
      • SETSr → SHLD16rrCL
      17.63
      [17.63;17.63]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 1
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class SETAr_SETBEr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SETAr → ADC8i8
      • SETAr → IMUL16r
      • SETAr → IMUL16r
      • SETAr → ANDN32rr
      • SETAr → SBB64i32
      • SETAr → SHLD32rri8
      • SETAr → CMP64ri8
      • SETAr → CMP32rr_REV
      • SETAr → CMP32rr
      • SETBEr → AND64rr
      • SETBEr → SHLD16rri8
      • SETBEr → ADD8i8
      • SETBEr → RCR8ri
      • SETBEr → XOR64_FP
      • SETBEr → BLCI32rr
      • SETBEr → CMP32rr_REV
      • SETBEr → TEST8i8
      • SETBEr → SHLD16rri8
      1.76
      [0.53;6.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 1
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75

      Sched Class SHLD32rrCL_SHRD32rrCL contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHLD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      • SHRD32rrCL
      3.43
      [3.03;4.05]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      7
      • 4
      • PdEX: 8
      • PdEX01: 4
      • PdAGLU01: 4.00
      • PdEX0: 4.00
      • PdEX1: 4.00

      Sched Class SHLD32rri8 contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      • SHLD32rri8
      3.63
      [3.03;4.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      6
      • 3
      • PdEX: 6
      • PdEX01: 3
      • PdAGLU01: 3.00
      • PdEX0: 3.00
      • PdEX1: 3.00

      Sched Class SHLD64rrCL_SHRD64rrCL contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHLD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      • SHRD64rrCL
      3.43
      [3.03;4.03]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      7
      • 4
      • PdEX: 8
      • PdEX01: 4
      • PdAGLU01: 4.00
      • PdEX0: 4.00
      • PdEX1: 4.00

      Sched Class WriteSHDrri contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      • SHRD32rri8
      3.44
      [3.03;4.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      6
      • 4
      • PdEX: 6
      • PdEX01: 3
      • PdAGLU01: 3.00
      • PdEX0: 3.00
      • PdEX1: 3.00

      Sched Class VCVTTSD2SI64rr_Int_VCVTTSD2SIrr_Int_CVTSS2SIrr_Int_CVTTSS2SIrr_CVTTSS2SIrr_Int_VCVTSS2SI64rr_Int_VCVTSS2SIrr_Int_VCVTTSS2SI64rr_VCVTTSS2SI64rr_Int_VCVTTSS2SIrr_VCVTTSS2SIrr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • VCVTTSD2SI64rr_Int → VCVTSI2SSrr_Int
      • VCVTTSD2SI64rr_Int → VCVTSI642SSrr_Int
      • VCVTTSD2SI64rr_Int → PINSRDrr
      • VCVTTSD2SIrr_Int → CVTSI2SDrr
      • VCVTTSD2SIrr_Int → VPINSRBrr
      • VCVTTSD2SIrr_Int → PINSRWrr
      • VCVTTSD2SIrr_Int → PINSRBrr
      • VCVTTSD2SIrr_Int → VMOV64toSDrr
      • VCVTTSD2SIrr_Int → VCVTSI2SSrr_Int
      12.59
      [11.03;13.03]
      2
      • VCVTTSD2SIrr_Int → VPCMPESTRMrr
      17.52
      [17.52;17.52]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class VCVTTSS2SI64rr_VCVTTSS2SI64rr_Int contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • VCVTTSS2SI64rr → VCVTSI642SSrr
      • VCVTTSS2SI64rr → VPINSRQrr
      • VCVTTSS2SI64rr_Int → CVTSI642SSrr_Int
      • VCVTTSS2SI64rr_Int → VPINSRQrr
      • VCVTTSS2SI64rr_Int → MOVDI2SSrr
      • VCVTTSS2SI64rr_Int → MOVDI2PDIrr
      • VCVTTSS2SI64rr_Int → PINSRDrr
      12.25
      [11.04;13.04]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 13
      • PdEX: 1
      • PdEX0: 1
      • PdFPFMA: 1
      • PdFPSTO: 1
      • PdFPU: 1
      • PdFPU1: 1
      • PdAGLU01: 0.50
      • PdEX0: 1.25
      • PdEX1: 0.25
      • PdFPFMA: 1.00
      • PdFPSTO: 1.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class VDPPSrri contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      3
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      25.04
      [25.03;25.07]
      7
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      • VDPPSrri
      30.04
      [30.03;30.06]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      17
      • 25
      • PdFPFMA: 3
      • PdFPU: 1
      • PdFPU1: 1
      • PdFPFMA: 3.00
      • PdFPU0: 0.25
      • PdFPU1: 1.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class VPCLMULQDQrr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      • VPCLMULQDQrr
      12.05
      [12.03;12.12]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      6
      • 13
      • PdFPMMA: 1
      • PdFPU: 1
      • PdFPU0: 1
      • PdFPMMA: 1.00
      • PdFPU0: 1.25
      • PdFPU1: 0.25
      • PdFPU2: 0.25
      • PdFPU3: 0.25

      Sched Class XCHG16rr contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      • XCHG16rr
      1.34
      [1.03;2.05]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      2
      • 2
      • PdEX: 1
      • PdEX1: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.25
      • PdEX1: 1.25

      Sched Class XGETBV contains instructions whose performance characteristics do not match that of LLVM:

      ClusterIdOpcode/Configlatency
      0
      • XGETBV → SHRD32rrCL
      15.53
      [15.53;15.53]

      llvm SchedModel data:

      ValidVariantNumMicroOpsLatencyWriteProcResIdealized Resource Pressure
      1
      • 100
      • PdEX: 1
      • PdEX01: 1
      • PdAGLU01: 0.50
      • PdEX0: 0.75
      • PdEX1: 0.75