llvm-exegesis Analysis Results

ClusterId	Opcode/Config	latency
0	XCHG16rr	1.13 [1.13;1.13]

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	2	PdEX: 1 PdEX1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 1.25

ClusterId	Opcode/Config	latency
0	VXORPDrr VXORPSrr XORPDrr XORPSrr	1.82 [1.27;2.01]

Sched Class CVTSS2SIrr_Int_VCVTSS2SI64rr_Int_VCVTSS2SIrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	VCVTSS2SIrr_Int → MOV64toSDrr	11.00 [11.00;11.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	13	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class SUB32rr_SUB64rr_XOR32rr_XOR64rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	SUB32rr SUB64rr XOR32rr XOR64rr	0.74 [0.55;1.02]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class CVTSS2SIrr_Int_CVTTSS2SIrr_CVTTSS2SIrr_Int_VCVTSS2SI64rr_Int_VCVTSS2SIrr_Int_VCVTTSS2SI64rr_VCVTTSS2SI64rr_Int_VCVTTSS2SIrr_VCVTTSS2SIrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	CVTTSS2SIrr → MOV64toPQIrr VCVTTSS2SIrr_Int → VCVTSI2SDrr	12.00 [11.00;13.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	13	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteMicrocoded contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
10	REP_MOVSB_32 REP_MOVSB_64 REP_MOVSD_32 REP_MOVSD_64 REP_MOVSQ_32 REP_MOVSQ_64 REP_MOVSW_32 REP_MOVSW_64	18.01 [18.00;18.01]
9	REP_STOSB_32 REP_STOSB_64 REP_STOSD_32 REP_STOSD_64 REP_STOSQ_32 REP_STOSQ_64 REP_STOSW_32 REP_STOSW_64	16.01 [16.00;16.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteCRC32 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	CRC32r64r8	2.11 [2.11;2.11]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	3	PdEX: 4 PdEX01: 2	PdAGLU01: 2.00 PdEX0: 2.00 PdEX1: 2.00

Sched Class PANDNrr_VPANDNrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	PANDNrr VPANDNrr	1.45 [0.89;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class WriteVecMoveX contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
1	MMX_MOVFR642Qrr → MMX_CVTPI2PDirr	5.00 [5.00;5.00]
4	MMX_MOVQ2FR64rr → MMX_CVTPS2PIirr	4.01 [4.01;4.01]
0	MOVDQArr MOVDQArr_REV MOVDQUrr MOVDQUrr_REV VMOVDQArr VMOVDQArr_REV VMOVDQUrr VMOVDQUrr_REV	0.98 [0.85;1.25]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class ANDNPSrr_VANDNPSrr_ANDNPDrr_VANDNPDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	ANDNPDrr ANDNPSrr VANDNPDrr VANDNPSrr	1.44 [0.87;2.02]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class CVTSI642SSrr_CVTSI642SSrr_Int_VCVTSI642SSrr_VCVTSI642SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	CVTSI642SSrr → VCVTTSD2SIrr	13.00 [13.00;13.00]
4	CVTSI642SSrr_Int VCVTSI642SSrr VCVTSI642SSrr_Int	4.01 [4.00;4.03]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteAESDecEnc contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
2	AESDECLASTrr AESDECrr AESENCLASTrr AESENCrr VAESDECLASTrr	9.01 [9.01;9.01]
1	VAESDECrr VAESENCLASTrr VAESENCrr	5.01 [5.00;5.03]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	9	PdFPMMA: 1 PdFPU: 1 PdFPU0: 1	PdFPMMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteVecExtract contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	VPEXTRWrr_REV → VCVTSI2SSrr	12.51 [12.51;12.51]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	11	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDSWrr_VPHADDSWrr_PHSUBSWrr_VPHSUBSWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
1	PHADDSWrr PHSUBSWrr VPHADDSWrr VPHSUBSWrr	5.01 [5.00;5.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class ARPL16mr_ARPL16rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	ARPL16rr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CVTSI2SSrr_CVTSI2SSrr_Int_VCVTSI2SSrr_VCVTSI2SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	CVTSI2SSrr → VPEXTRBrr	12.51 [12.51;12.51]
4	CVTSI2SSrr_Int VCVTSI2SSrr VCVTSI2SSrr_Int	4.02 [4.01;4.04]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPI2PDirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
7	MMX_CVTPI2PDirr → MMX_CVTPD2PIirr	7.01 [7.01;7.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteALU contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	ADD16i16 ADD16ri ADD16ri8 ADD16ri8_DB ADD16ri_DB ADD16rr ADD16rr_DB ADD16rr_REV ADD32i32 ADD32ri ADD32ri8 ADD32ri8_DB ADD32ri_DB ADD32rr ADD32rr_DB ADD32rr_REV ADD64i32 ADD64ri32 ADD64ri32_DB ADD64ri8 ADD64ri8_DB ADD64rr ADD64rr_DB ADD64rr_REV ADD8i8 ADD8ri ADD8rr ADD8rr_REV AND16i16 AND16ri AND16ri8 AND16rr AND16rr_REV AND32i32 AND32ri AND32ri8 AND32rr AND32rr_REV AND64i32 AND64ri32 AND64ri8 AND64rr AND64rr_REV AND8i8 AND8ri AND8rr AND8rr_REV BLCFILL32rr BLCFILL64rr BLCI32rr BLCI64rr BLCIC32rr BLCIC64rr BLCMSK32rr BLCMSK64rr BLCS32rr BLCS64rr BLSFILL32rr BLSFILL64rr BLSIC32rr BLSIC64rr CMP16ri → CMOVNS32rr CMP16ri8 → SETB_C32r CMP16rr → ADC32rr_REV CMP32i32 → RCL32r1 CMP32ri → ADC32rr CMP32ri8 → CMOVE32rr CMP32rr → SBB16i16 CMP32rr_REV → SBB16i16 CMP64i32 → CMOVL64rr CMP64ri32 → SETLEr CMP64rr → SBB16rr_REV CMP64rr_REV → SETSr CMP8i8 → ADC32ri8 CMP8ri → CMOVNO32rr CMP8rr → SBB64i32 CMP8rr_REV → CMOV_GR16 DEC16r DEC32r DEC64r DEC8r INC16r INC32r INC64r INC8r MOVSX16rr16 MOVZX16rr16 NEG16r NEG32r NEG64r NEG8r NOT16r NOT32r NOT64r NOT8r OR16i16 OR16ri OR16ri8 OR16rr OR16rr_REV OR32i32 OR32ri OR32ri8 OR32rr OR32rr_REV OR64i32 OR64ri32 OR64ri8 OR64rr OR64rr_REV OR8i8 OR8ri OR8rr OR8rr_REV SUB16i16 SUB16ri SUB16ri8 SUB16rr SUB16rr_REV SUB32i32 SUB32ri SUB32ri8 SUB32rr_REV SUB64i32 SUB64ri32 SUB64ri8 SUB64rr_REV SUB8i8 SUB8ri SUB8rr SUB8rr_REV T1MSKC32rr T1MSKC64rr TEST16i16 → SETEr TEST16ri → SBB64ri8 TEST16rr → SETPr TEST32i32 → ADC16rr TEST32ri → SETB_C8r TEST32rr → CMOVS32rr TEST64i32 → ADC8i8 TEST64ri32 → SBB16rr TEST64rr → SETGEr TZMSK32rr TZMSK64rr XOR16i16 XOR16ri XOR16ri8 XOR16rr XOR16rr_REV XOR32i32 XOR32ri XOR32ri8 XOR32rr_REV XOR64i32 XOR64ri32 XOR64ri8 XOR64rr_REV XOR8i8 XOR8ri XOR8rr	1.26 [0.35;2.09]
5	CMP16rr_REV → RCR8ri	6.00 [6.00;6.00]
4	CMP64ri8 → RCL32rCL	3.76 [3.76;3.76]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CRC32r32r8 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	CRC32r32r8	2.13 [2.13;2.13]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	3	PdEX: 4 PdEX01: 2	PdAGLU01: 2.00 PdEX0: 2.00 PdEX1: 2.00

Sched Class WriteBEXTR contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	BEXTR32rr BEXTR64rr	1.66 [1.31;2.02]
3	BEXTRI32ri BEXTRI64ri	2.92 [2.92;2.92]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	2	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteSystem contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	BNDMOVrr BNDMOVrr_REV RDSSPD RDSSPQ VASTART_SAVE_XMM_REGS → CMOVBE32rr	0.92 [0.50;1.19]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteVecMoveToGpr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	MMX_MOVD64from64rr → MMX_PINSRWrr VMOVPDI2DIrr → VCVTSI642SDrr_Int	10.51 [10.00;11.01]
2	MMX_MOVD64grr → MMX_MOVD64rr MOVSS2DIrr → VMOV64toSDrr	9.00 [9.00;9.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	10	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTSI2SDrr_CVTSI2SDrr_Int_CVTSI642SDrr_CVTSI642SDrr_Int_VCVTSI2SDrr_VCVTSI2SDrr_Int_VCVTSI642SDrr_VCVTSI642SDrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
4	CVTSI2SDrr_Int CVTSI642SDrr_Int VCVTSI2SDrr VCVTSI2SDrr_Int VCVTSI642SDrr VCVTSI642SDrr_Int	4.01 [4.00;4.03]
6	CVTSI642SDrr → VPEXTRWrr_REV	12.50 [12.50;12.50]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteVecMoveFromGpr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
2	MMX_MOVD64rr → MMX_MOVD64from64rr MOVDI2PDIrr → VMOVPDI2DIrr VMOVDI2SSrr → VMOVPQIto64rr	9.00 [9.00;9.01]
6	MMX_MOVD64to64rr → MMX_PEXTRWrr MOV64toPQIrr → VPEXTRWrr VMOV64toSDrr → VCVTTSD2SIrr	10.34 [10.01;11.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	10	PdFPFMA: 1 PdFPU: 1 PdFPU01: 1	PdFPFMA: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_PCMPGTBirr_MMX_PCMPGTDirr_MMX_PCMPGTWirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	MMX_PCMPGTBirr MMX_PCMPGTDirr MMX_PCMPGTWirr	1.13 [0.67;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class LAHF contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
10	LAHF → SHLD16rrCL	18.52 [18.52;18.52]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	4	2	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteMMXMOVMSK contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	MMX_PMOVMSKBrr → MMX_PINSRWrr	11.00 [11.00;11.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	10	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPD2PIirr_MMX_CVTTPD2PIirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
7	MMX_CVTPD2PIirr → MMX_CVTPI2PSirr	7.01 [7.01;7.01]
1	MMX_CVTTPD2PIirr → MMX_MOVQ2FR64rr	5.00 [5.00;5.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteCLMul contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	PCLMULQDQrr	13.01 [13.01;13.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	5	12	PdFPMMA: 1 PdFPU: 1 PdFPU0: 1	PdFPMMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_PXORirr_MMX_PANDNirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	MMX_PANDNirr MMX_PXORirr	0.69 [0.65;0.74]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class MMX_PSUBSBirr_MMX_PSUBSWirr_MMX_PSUBUSBirr_MMX_PSUBUSWirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	MMX_PSUBSBirr MMX_PSUBSWirr MMX_PSUBUSBirr MMX_PSUBUSWirr	1.35 [0.64;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_PSUBBirr_MMX_PSUBDirr_MMX_PSUBWirr_MMX_PCMPGTBirr_MMX_PCMPGTDirr_MMX_PCMPGTWirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	MMX_PSUBBirr MMX_PSUBDirr MMX_PSUBWirr	0.65 [0.63;0.66]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class MMX_PADDQirr_MMX_PSUBQirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	MMX_PSUBQirr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class WriteFMOVMSK contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	MOVMSKPDrr → VCVTSI2SSrr VMOVMSKPDrr → MOV64toSDrr	11.26 [10.01;12.51]
9	VMOVMSKPSYrr → PCMPESTRMrr	16.04 [16.04;16.04]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	10	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteMPSAD contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	MPSADBWrri	10.01 [10.01;10.01]
2	VMPSADBWrri	9.01 [9.01;9.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	9	8	PdFPMMA: 2 PdFPU: 1 PdFPU0: 1	PdFPMMA: 2.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PSUBQrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	PSUBQrr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class MMX_CVTPS2PIirr_MMX_CVTTPS2PIirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
4	MMX_CVTPS2PIirr → MMX_MOVQ2DQrr	4.01 [4.01;4.01]
5	MMX_CVTTPS2PIirr → MMX_CVTPI2PSirr	6.01 [6.01;6.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePCmpEStrI contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
9	PCMPESTRIrr → SBB64ri32	15.51 [15.51;15.51]
10	VPCMPESTRIrr → RCR32rCL	18.42 [18.42;18.42]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	27	5	PdEX: 9 PdEX0: 1 PdFPFMA: 1 PdFPMAL: 4 PdFPU: 1 PdFPU1: 1	PdAGLU01: 4.50 PdEX0: 3.25 PdEX1: 2.25 PdFPFMA: 1.00 PdFPMAL: 4.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PSUBBrr_VPSUBBrr_PSUBDrr_VPSUBDrr_VPSUBQrr_PSUBWrr_VPSUBWrr_PCMPGTBrr_VPCMPGTBrr_PCMPGTDrr_VPCMPGTDrr_PCMPGTWrr_VPCMPGTWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	PCMPGTBrr PCMPGTDrr PCMPGTWrr VPCMPGTBrr VPCMPGTDrr VPCMPGTWrr	1.88 [1.25;2.02]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class WritePCmpIStrI contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
6	PCMPISTRIrr → VMOV64toSDrr	11.51 [11.51;11.51]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	7	15	PdEX: 1 PdEX0: 1 PdFPFMA: 2 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 2.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDDrr_PHSUBDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
1	PHADDDrr PHSUBDrr	5.01 [5.00;5.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PXORrr_VPXORrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	PXORrr VPXORrr	2.01 [2.01;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class WritePHAddX contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
1	PHADDWrr PHSUBWrr VPHADDDrr VPHADDWrr VPHSUBDrr VPHSUBWrr	5.01 [5.00;5.01]
0	VPHADDBDrr VPHADDBQrr VPHADDBWrr VPHADDDQrr VPHADDUBDrr VPHADDUBQrr VPHADDUBWrr VPHADDUDQrr VPHADDUWDrr VPHADDUWQrr VPHADDWDrr VPHADDWQrr VPHSUBBWrr VPHSUBDQrr VPHSUBWDrr	2.02 [2.01;2.06]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePMULLD contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
1	PMULLDrr VPMACSDDrr VPMACSSDDrr VPMULLDrr	5.01 [5.00;5.04]
4	VPMACSDQHrr VPMACSDQLrr VPMACSSDQHrr VPMACSSDQLrr	4.01 [4.01;4.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPMAL: 1 PdFPMMA: 2 PdFPU: 3 PdFPU0: 2	PdFPMAL: 1.00 PdFPMMA: 2.00 PdFPU0: 2.75 PdFPU1: 0.75 PdFPU2: 0.75 PdFPU3: 0.75

Sched Class WriteVarShuffleX contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
3	PSHUFBrr VPSHUFBrr	3.00 [3.00;3.01]
0	VPPERMrrr VPPERMrrr_REV	2.12 [2.11;2.12]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	3	PdFPMAL: 4 PdFPU: 1 PdFPU01: 1	PdFPMAL: 4.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PSUBBrr_PSUBDrr_PSUBWrr_VPSUBBrr_VPSUBDrr_VPSUBQrr_VPSUBWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	latency
0	PSUBBrr PSUBDrr PSUBWrr VPSUBBrr VPSUBDrr VPSUBQrr VPSUBWrr	1.93 [1.41;2.03]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

llvm-exegesis Analysis Results

Triple: x86_64-unknown-linux-gnu

Cpu: bdver2