llvm-exegesis Analysis Results

Triple: x86_64-unknown-linux-gnu

Cpu: bdver2

Sched Class WriteFSign contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ABS_F
  • ABS_F
  • ABS_F
2.03
[2.02;2.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
1.00
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteALULd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ADD16rm (x14)
  • ADD32rm (x14)
  • ADD64rm (x14)
  • ADD8rm (x18)
  • AND16rm (x14)
  • AND32rm (x14)
  • AND64rm (x14)
  • AND8rm (x18)
  • CMP16rm (x6)
  • CMP32rm (x6)
  • CMP64rm (x6)
  • CMP8rm (x6)
  • OR16rm (x14)
  • OR32rm (x14)
  • OR64rm (x14)
  • OR8rm (x18)
  • SUB16rm (x14)
  • SUB32rm (x14)
  • SUB64rm (x14)
  • SUB8rm (x18)
  • XOR16rm (x14)
  • XOR32rm (x14)
  • XOR64rm (x14)
  • XOR8rm (x18)
  • ADD16rm (x14)
  • ADD32rm (x14)
  • ADD64rm (x14)
  • ADD8rm (x18)
  • AND16rm (x14)
  • AND32rm (x14)
  • AND64rm (x14)
  • AND8rm (x18)
  • CMP16rm (x6)
  • CMP32rm (x6)
  • CMP64rm (x6)
  • CMP8rm (x6)
  • OR16rm (x14)
  • OR32rm (x14)
  • OR64rm (x14)
  • OR8rm (x18)
  • SUB16rm (x14)
  • SUB32rm (x14)
  • SUB64rm (x14)
  • SUB8rm (x18)
  • XOR16rm (x14)
  • XOR32rm (x14)
  • XOR64rm (x14)
  • XOR8rm (x18)
  • ADD16rm (x14)
  • ADD32rm (x14)
  • ADD64rm (x14)
  • ADD8rm (x18)
  • AND16rm (x14)
  • AND32rm (x14)
  • AND64rm (x14)
  • AND8rm (x18)
  • CMP16rm (x6)
  • CMP32rm (x6)
  • CMP64rm (x6)
  • CMP8rm (x6)
  • OR16rm (x14)
  • OR32rm (x14)
  • OR64rm (x14)
  • OR8rm (x18)
  • SUB16rm (x14)
  • SUB32rm (x14)
  • SUB64rm (x14)
  • SUB8rm (x18)
  • XOR16rm (x14)
  • XOR32rm (x14)
  • XOR64rm (x14)
  • XOR8rm (x18)
1.35
[1.05;1.81]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class ADD_F32m_ADD_F64m_SUBR_F32m_SUBR_F64m_SUB_F32m_SUB_F64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ADD_F32m (x6)
  • ADD_F64m (x6)
  • SUBR_F32m (x6)
  • SUBR_F64m (x6)
  • SUB_F32m (x6)
  • SUB_F64m (x6)
  • ADD_F32m (x6)
  • ADD_F64m (x6)
  • SUBR_F32m (x6)
  • SUBR_F64m (x6)
  • SUB_F32m (x6)
  • SUB_F64m (x6)
  • ADD_F32m (x6)
  • ADD_F64m (x6)
  • SUBR_F32m (x6)
  • SUBR_F64m (x6)
  • SUB_F32m (x6)
  • SUB_F64m (x6)
5.04
[5.03;5.11]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 10
1.00
  • PdAGLU01: 1
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class ADD_FI16m_ADD_FI32m_SUBR_FI16m_SUBR_FI32m_SUB_FI16m_SUB_FI32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ADD_FI16m (x6)
  • ADD_FI32m (x6)
  • SUBR_FI16m (x6)
  • SUBR_FI32m (x6)
  • SUB_FI16m (x6)
  • SUB_FI32m (x6)
  • ADD_FI16m (x6)
  • ADD_FI32m (x6)
  • SUBR_FI16m (x6)
  • SUBR_FI32m (x6)
  • SUB_FI16m (x6)
  • SUB_FI32m (x6)
  • ADD_FI16m (x6)
  • ADD_FI32m (x6)
  • SUBR_FI16m (x6)
  • SUBR_FI32m (x6)
  • SUB_FI16m (x6)
  • SUB_FI32m (x6)
5.04
[5.03;5.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 10
1.00
  • PdAGLU01: 1
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteAESDecEncLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • AESDECLASTrm (x16)
  • AESDECrm (x16)
  • AESENCLASTrm (x16)
  • AESENCrm (x16)
  • VAESDECLASTrm (x6)
  • VAESDECrm (x6)
  • VAESENCLASTrm (x6)
  • VAESENCrm (x6)
  • AESDECLASTrm (x16)
  • AESDECrm (x16)
  • AESENCLASTrm (x16)
  • AESENCrm (x16)
  • VAESDECLASTrm (x6)
  • VAESDECrm (x6)
  • VAESENCLASTrm (x6)
  • VAESENCrm (x6)
  • AESDECLASTrm (x16)
  • AESDECrm (x16)
  • AESENCLASTrm (x16)
  • AESENCrm (x16)
  • VAESDECLASTrm (x6)
  • VAESDECrm (x6)
  • VAESENCLASTrm (x6)
  • VAESENCrm (x6)
1.90
[1.60;2.60]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 14
1.00
  • PdAGLU01: 1
  • PdFPMMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPMMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteAESIMCLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • AESIMCrm (x6)
  • VAESIMCrm (x6)
  • AESIMCrm (x6)
  • VAESIMCrm (x6)
  • AESIMCrm (x6)
  • VAESIMCrm (x6)
1.72
[1.61;1.92]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 10
1.00
  • PdAGLU01: 1
  • PdFPMMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPMMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteAESKeyGenLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • AESKEYGENASSIST128rm (x6)
  • VAESKEYGENASSIST128rm (x6)
  • AESKEYGENASSIST128rm (x6)
  • VAESKEYGENASSIST128rm (x6)
  • AESKEYGENASSIST128rm (x6)
  • VAESKEYGENASSIST128rm (x6)
2.06
[1.84;2.62]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 10
1.00
  • PdAGLU01: 1
  • PdFPMMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPMMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class AND16mi_AND16mi8_AND16mr_AND32mi_AND32mi8_AND32mr_AND64mi32_AND64mi8_AND64mr_AND8mi_AND8mi8_AND8mr_OR16mi_OR16mi8_OR16mr_OR32mi_OR32mi8_OR32mi8Locked_OR32mr_OR64mi32_OR64mi8_OR64mr_OR8mi_OR8mi8_OR8mr_XOR16mi_XOR16mi8_XOR16mr_XOR32mi_XOR32mi8_XOR32mr_XOR64mi32_XOR64mi8_XOR64mr_XOR8mi_XOR8mi8_XOR8mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • AND16mi (x6)
  • AND16mi8 (x6)
  • AND16mr (x6)
  • AND32mi (x6)
  • AND32mi8 (x6)
  • AND32mr (x6)
  • AND64mi32 (x6)
  • AND64mi8 (x6)
  • AND64mr (x6)
  • AND8mi (x6)
  • AND8mr (x6)
  • OR16mi (x6)
  • OR16mi8 (x6)
  • OR16mr (x6)
  • OR32mi (x6)
  • OR32mi8 (x6)
  • OR32mr (x6)
  • OR64mi32 (x6)
  • OR64mi8 (x6)
  • OR64mr (x6)
  • OR8mi (x6)
  • OR8mr (x6)
  • XOR16mi (x6)
  • XOR16mi8 (x6)
  • XOR16mr (x6)
  • XOR32mi (x6)
  • XOR32mi8 (x6)
  • XOR32mr (x6)
  • XOR64mi32 (x6)
  • XOR64mi8 (x6)
  • XOR64mr (x6)
  • XOR8mi (x6)
  • XOR8mr (x6)
  • AND16mi (x6)
  • AND16mi8 (x6)
  • AND16mr (x6)
  • AND32mi (x6)
  • AND32mi8 (x6)
  • AND32mr (x6)
  • AND64mi32 (x6)
  • AND64mi8 (x6)
  • AND64mr (x6)
  • AND8mi (x6)
  • AND8mr (x6)
  • OR16mi (x6)
  • OR16mi8 (x6)
  • OR16mr (x6)
  • OR32mi (x6)
  • OR32mi8 (x6)
  • OR32mr (x6)
  • OR64mi32 (x6)
  • OR64mi8 (x6)
  • OR64mr (x6)
  • OR8mi (x6)
  • OR8mr (x6)
  • XOR16mi (x6)
  • XOR16mi8 (x6)
  • XOR16mr (x6)
  • XOR32mi (x6)
  • XOR32mi8 (x6)
  • XOR32mr (x6)
  • XOR64mi32 (x6)
  • XOR64mi8 (x6)
  • XOR64mr (x6)
  • XOR8mi (x6)
  • XOR8mr (x6)
  • AND16mi (x6)
  • AND16mi8 (x6)
  • AND16mr (x6)
  • AND32mi (x6)
  • AND32mi8 (x6)
  • AND32mr (x6)
  • AND64mi32 (x6)
  • AND64mi8 (x6)
  • AND64mr (x6)
  • AND8mi (x6)
  • AND8mr (x6)
  • OR16mi (x6)
  • OR16mi8 (x6)
  • OR16mr (x6)
  • OR32mi (x6)
  • OR32mi8 (x6)
  • OR32mr (x6)
  • OR64mi32 (x6)
  • OR64mi8 (x6)
  • OR64mr (x6)
  • OR8mi (x6)
  • OR8mr (x6)
  • XOR16mi (x6)
  • XOR16mi8 (x6)
  • XOR16mr (x6)
  • XOR32mi (x6)
  • XOR32mi8 (x6)
  • XOR32mr (x6)
  • XOR64mi32 (x6)
  • XOR64mi8 (x6)
  • XOR64mr (x6)
  • XOR8mi (x6)
  • XOR8mr (x6)
1.59
[1.16;2.52]
3
  • OR32mi8Locked (x6)
  • OR32mi8Locked (x6)
  • OR32mi8Locked (x6)
43.38
[42.25;45.04]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 6
1.00
  • PdAGLU01: 2
  • PdEX01: 1
  • PdLoad: 1
  • PdStore: 1
  • PdAGLU01: 2.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00
  • PdStore: 1.00

Sched Class ANDN32rm_ANDN64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ANDN32rm (x6)
  • ANDN64rm (x6)
  • ANDN32rm (x6)
  • ANDN64rm (x6)
  • ANDN32rm (x6)
  • ANDN64rm (x6)
1.67
[1.62;1.73]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteFLogicLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • ANDNPDrm (x16)
  • ANDNPSrm (x16)
  • ANDPDrm (x16)
  • ANDPSrm (x16)
  • ORPDrm (x16)
  • ORPSrm (x16)
  • VANDNPDrm (x6)
  • VANDNPSrm (x6)
  • VANDPDrm (x6)
  • VANDPSrm (x6)
  • VORPDrm (x6)
  • VORPSrm (x6)
  • VXORPDrm (x6)
  • VXORPSrm (x6)
  • XORPDrm (x16)
  • XORPSrm (x16)
  • ANDNPDrm (x16)
  • ANDNPSrm (x16)
  • ANDPDrm (x16)
  • ANDPSrm (x16)
  • ORPDrm (x16)
  • ORPSrm (x16)
  • VANDNPDrm (x6)
  • VANDNPSrm (x6)
  • VANDPDrm (x6)
  • VANDPSrm (x6)
  • VORPDrm (x6)
  • VORPSrm (x6)
  • VXORPDrm (x6)
  • VXORPSrm (x6)
  • XORPDrm (x16)
  • XORPSrm (x16)
  • ANDNPDrm (x16)
  • ANDNPSrm (x16)
  • ANDPDrm (x16)
  • ANDPSrm (x16)
  • ORPDrm (x16)
  • ORPSrm (x16)
  • VANDNPDrm (x6)
  • VANDNPSrm (x6)
  • VANDPDrm (x6)
  • VANDPSrm (x6)
  • VORPDrm (x6)
  • VORPSrm (x6)
  • VXORPDrm (x6)
  • VXORPSrm (x6)
  • XORPDrm (x16)
  • XORPSrm (x16)
1.60
[1.38;2.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 7
0.50
  • PdAGLU01: 1
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 1.00
  • PdFPU0: 0.75
  • PdFPU1: 0.75
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteBEXTRLd_ReadDefault_ReadDefault_ReadDefault_ReadDefault_ReadDefault_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BEXTR32rm (x6)
  • BEXTR64rm (x6)
  • BEXTR32rm (x6)
  • BEXTR64rm (x6)
  • BEXTR32rm (x6)
  • BEXTR64rm (x6)
1.65
[1.60;1.74]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 6
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteBEXTRLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BEXTRI32mi (x6)
  • BEXTRI64mi (x6)
  • BEXTRI32mi (x6)
  • BEXTRI64mi (x6)
  • BEXTRI32mi (x6)
  • BEXTRI64mi (x6)
2.64
[2.47;3.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 6
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class BLCFILL32rm_BLCFILL64rm_BLCI32rm_BLCI64rm_BLCIC32rm_BLCIC64rm_BLCMSK32rm_BLCMSK64rm_BLCS32rm_BLCS64rm_BLSFILL32rm_BLSFILL64rm_BLSIC32rm_BLSIC64rm_T1MSKC32rm_T1MSKC64rm_TZMSK32rm_TZMSK64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLCFILL32rm (x6)
  • BLCFILL64rm (x6)
  • BLCI32rm (x6)
  • BLCI64rm (x6)
  • BLCIC32rm (x6)
  • BLCIC64rm (x6)
  • BLCMSK32rm (x6)
  • BLCMSK64rm (x6)
  • BLCS32rm (x6)
  • BLCS64rm (x6)
  • BLSFILL32rm (x6)
  • BLSFILL64rm (x6)
  • BLSIC32rm (x6)
  • BLSIC64rm (x6)
  • T1MSKC32rm (x6)
  • T1MSKC64rm (x6)
  • TZMSK32rm (x6)
  • TZMSK64rm (x6)
  • BLCFILL32rm (x6)
  • BLCFILL64rm (x6)
  • BLCI32rm (x6)
  • BLCI64rm (x6)
  • BLCIC32rm (x6)
  • BLCIC64rm (x6)
  • BLCMSK32rm (x6)
  • BLCMSK64rm (x6)
  • BLCS32rm (x6)
  • BLCS64rm (x6)
  • BLSFILL32rm (x6)
  • BLSFILL64rm (x6)
  • BLSIC32rm (x6)
  • BLSIC64rm (x6)
  • T1MSKC32rm (x6)
  • T1MSKC64rm (x6)
  • TZMSK32rm (x6)
  • TZMSK64rm (x6)
  • BLCFILL32rm (x6)
  • BLCFILL64rm (x6)
  • BLCI32rm (x6)
  • BLCI64rm (x6)
  • BLCIC32rm (x6)
  • BLCIC64rm (x6)
  • BLCMSK32rm (x6)
  • BLCMSK64rm (x6)
  • BLCS32rm (x6)
  • BLCS64rm (x6)
  • BLSFILL32rm (x6)
  • BLSFILL64rm (x6)
  • BLSIC32rm (x6)
  • BLSIC64rm (x6)
  • T1MSKC32rm (x6)
  • T1MSKC64rm (x6)
  • TZMSK32rm (x6)
  • TZMSK64rm (x6)
1.69
[1.59;2.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 6
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class BLCFILL32rr_BLCFILL64rr_BLCI32rr_BLCI64rr_BLCIC32rr_BLCIC64rr_BLCMSK32rr_BLCMSK64rr_BLCS32rr_BLCS64rr_BLSFILL32rr_BLSFILL64rr_BLSIC32rr_BLSIC64rr_T1MSKC32rr_T1MSKC64rr_TZMSK32rr_TZMSK64rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLCFILL32rr
  • BLCFILL64rr
  • BLCI32rr
  • BLCI64rr
  • BLCIC32rr
  • BLCIC64rr
  • BLCMSK32rr
  • BLCMSK64rr
  • BLCS32rr
  • BLCS64rr
  • BLSFILL32rr
  • BLSFILL64rr
  • BLSIC32rr
  • BLSIC64rr
  • T1MSKC32rr
  • T1MSKC64rr
  • TZMSK32rr
  • TZMSK64rr
  • BLCFILL32rr
  • BLCFILL64rr
  • BLCI32rr
  • BLCI64rr
  • BLCIC32rr
  • BLCIC64rr
  • BLCMSK32rr
  • BLCMSK64rr
  • BLCS32rr
  • BLCS64rr
  • BLSFILL32rr
  • BLSFILL64rr
  • BLSIC32rr
  • BLSIC64rr
  • T1MSKC32rr
  • T1MSKC64rr
  • TZMSK32rr
  • TZMSK64rr
  • BLCFILL32rr
  • BLCFILL64rr
  • BLCI32rr
  • BLCI64rr
  • BLCIC32rr
  • BLCIC64rr
  • BLCMSK32rr
  • BLCMSK64rr
  • BLCS32rr
  • BLCS64rr
  • BLSFILL32rr
  • BLSFILL64rr
  • BLSIC32rr
  • BLSIC64rr
  • T1MSKC32rr
  • T1MSKC64rr
  • TZMSK32rr
  • TZMSK64rr
1.08
[1.03;1.27]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 2
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteFBlendLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLENDPDrmi (x16)
  • BLENDPSrmi (x16)
  • VBLENDPDrmi (x6)
  • VBLENDPSrmi (x6)
  • BLENDPDrmi (x16)
  • BLENDPSrmi (x16)
  • VBLENDPDrmi (x6)
  • VBLENDPSrmi (x6)
  • BLENDPDrmi (x16)
  • BLENDPSrmi (x16)
  • VBLENDPDrmi (x6)
  • VBLENDPSrmi (x6)
2.15
[1.86;2.38]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 7
0.50
  • PdAGLU01: 1
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 1.00
  • PdFPU0: 0.75
  • PdFPU1: 0.75
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFBlend contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLENDPDrri (x16)
  • BLENDPSrri (x16)
  • VBLENDPDrri
  • VBLENDPSrri
  • BLENDPDrri (x16)
  • BLENDPSrri (x16)
  • VBLENDPDrri
  • VBLENDPSrri
  • BLENDPDrri (x16)
  • BLENDPSrri (x16)
  • VBLENDPDrri
  • VBLENDPSrri
1.43
[1.18;1.61]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 2
0.50
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU01: 1
  • PdFPFMA: 1.00
  • PdFPU0: 0.75
  • PdFPU1: 0.75
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteFVarBlend contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLENDVPDrr0 (x16)
  • BLENDVPSrr0 (x16)
  • VBLENDVPDrr
  • VBLENDVPSrr
  • BLENDVPDrr0 (x16)
  • BLENDVPSrr0 (x16)
  • VBLENDVPDrr
  • VBLENDVPSrr
  • BLENDVPDrr0 (x16)
  • BLENDVPSrr0 (x16)
  • VBLENDVPDrr
  • VBLENDVPSrr
1.28
[1.19;1.42]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 2
2.00
  • PdFPFMA: 4
  • PdFPU: 1
  • PdFPU01: 1
  • PdFPFMA: 4.00
  • PdFPU0: 0.75
  • PdFPU1: 0.75
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteBLSLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLSI32rm (x6)
  • BLSI64rm (x6)
  • BLSMSK32rm (x6)
  • BLSMSK64rm (x6)
  • BLSR32rm (x6)
  • BLSR64rm (x6)
  • BLSI32rm (x6)
  • BLSI64rm (x6)
  • BLSMSK32rm (x6)
  • BLSMSK64rm (x6)
  • BLSR32rm (x6)
  • BLSR64rm (x6)
  • BLSI32rm (x6)
  • BLSI64rm (x6)
  • BLSMSK32rm (x6)
  • BLSMSK64rm (x6)
  • BLSR32rm (x6)
  • BLSR64rm (x6)
1.71
[1.60;1.98]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 6
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteBLS contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BLSI32rr
  • BLSI64rr
  • BLSMSK32rr
  • BLSMSK64rr
  • BLSR32rr
  • BLSR64rr
  • BLSI32rr
  • BLSI64rr
  • BLSMSK32rr
  • BLSMSK64rr
  • BLSR32rr
  • BLSR64rr
  • BLSI32rr
  • BLSI64rr
  • BLSMSK32rr
  • BLSMSK64rr
  • BLSR32rr
  • BLSR64rr
1.13
[1.03;1.60]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 2
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteSystem contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BNDCL32rm (x6)
  • BNDCL32rr
  • BNDCL64rm (x6)
  • BNDCL64rr
  • BNDCN32rm (x6)
  • BNDCN32rr
  • BNDCN64rm (x6)
  • BNDCN64rr
  • BNDCU32rm (x6)
  • BNDCU32rr
  • BNDCU64rm (x6)
  • BNDCU64rr
  • BNDLDXrm (x6)
  • BNDMK32rm (x6)
  • BNDMK64rm (x6)
  • BNDMOV32mr (x6)
  • BNDMOV32rm (x6)
  • BNDMOV64mr (x6)
  • BNDMOV64rm (x6)
  • BNDMOVrr
  • BNDMOVrr_REV
  • BNDSTXmr (x6)
  • ENDBR32
  • ENDBR64
  • RDSSPD (x15)
  • RDSSPQ (x15)
  • SLDT16m (x6)
  • SMSW16r
  • SMSW32r
  • SMSW64r
  • BNDCL32rm (x6)
  • BNDCL32rr
  • BNDCL64rm (x6)
  • BNDCL64rr
  • BNDCN32rm (x6)
  • BNDCN32rr
  • BNDCN64rm (x6)
  • BNDCN64rr
  • BNDCU32rm (x6)
  • BNDCU32rr
  • BNDCU64rm (x6)
  • BNDCU64rr
  • BNDLDXrm (x6)
  • BNDMK32rm (x6)
  • BNDMK64rm (x6)
  • BNDMOV32mr (x6)
  • BNDMOV32rm (x6)
  • BNDMOV64mr (x6)
  • BNDMOV64rm (x6)
  • BNDMOVrr
  • BNDMOVrr_REV
  • BNDSTXmr (x6)
  • ENDBR32
  • ENDBR64
  • RDSSPD (x15)
  • RDSSPQ (x15)
  • SLDT16m (x6)
  • SMSW16r
  • SMSW32r
  • SMSW64r
  • BNDCL32rm (x6)
  • BNDCL32rr
  • BNDCL64rm (x6)
  • BNDCL64rr
  • BNDCN32rm (x6)
  • BNDCN32rr
  • BNDCN64rm (x6)
  • BNDCN64rr
  • BNDCU32rm (x6)
  • BNDCU32rr
  • BNDCU64rm (x6)
  • BNDCU64rr
  • BNDLDXrm (x6)
  • BNDMK32rm (x6)
  • BNDMK64rm (x6)
  • BNDMOV32mr (x6)
  • BNDMOV32rm (x6)
  • BNDMOV64mr (x6)
  • BNDMOV64rm (x6)
  • BNDMOVrr
  • BNDMOVrr_REV
  • BNDSTXmr (x6)
  • ENDBR32
  • ENDBR64
  • RDSSPD (x15)
  • RDSSPQ (x15)
  • SLDT16m (x6)
  • SMSW16r
  • SMSW32r
  • SMSW64r
1.44
[0.72;4.57]
21
  • LFS16rm (x6)
  • LFS32rm (x6)
  • LFS64rm (x6)
  • LGS16rm (x6)
  • LGS32rm (x6)
  • LGS64rm (x6)
  • LFS16rm (x6)
  • LFS32rm (x6)
  • LFS64rm (x6)
  • LGS16rm (x6)
  • LGS32rm (x6)
  • LGS64rm (x6)
  • LFS16rm (x6)
  • LFS32rm (x6)
  • LFS64rm (x6)
  • LGS16rm (x6)
  • LGS32rm (x6)
  • LGS64rm (x6)
311.25
[311.21;311.31]
8
  • SGDT16m (x6)
  • SGDT32m (x6)
  • SIDT16m (x6)
  • SIDT32m (x6)
  • SGDT16m (x6)
  • SGDT32m (x6)
  • SIDT16m (x6)
  • SIDT32m (x6)
  • SGDT16m (x6)
  • SGDT32m (x6)
  • SIDT16m (x6)
  • SIDT32m (x6)
6.66
[6.60;6.76]
27
  • VERRr
  • VERWr
  • VERRr
  • VERWr
  • VERRr
  • VERWr
184.14
[184.09;184.19]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteBSFLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BSF16rm (x6)
  • BSF32rm (x6)
  • BSF64rm (x6)
  • BSF16rm (x6)
  • BSF32rm (x6)
  • BSF64rm (x6)
  • BSF16rm (x6)
  • BSF32rm (x6)
  • BSF64rm (x6)
4.05
[4.03;4.16]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
8
  • 7
2.00
  • PdAGLU01: 1
  • PdEX: 2
  • PdEX01: 3
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 2.50
  • PdEX1: 2.50
  • PdLoad: 1.00

Sched Class WriteBSF contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BSF16rr
  • BSF32rr
  • BSF64rr
  • BSF16rr
  • BSF32rr
  • BSF64rr
  • BSF16rr
  • BSF32rr
  • BSF64rr
3.04
[3.03;3.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
6
  • 3
2.00
  • PdEX: 4
  • PdEX01: 2
  • PdAGLU01: 2.00
  • PdEX0: 2.00
  • PdEX1: 2.00

Sched Class WriteBSRLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BSR16rm (x6)
  • BSR32rm (x6)
  • BSR64rm (x6)
  • BSR16rm (x6)
  • BSR32rm (x6)
  • BSR64rm (x6)
  • BSR16rm (x6)
  • BSR32rm (x6)
  • BSR64rm (x6)
5.06
[5.03;5.20]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
9
  • 8
2.00
  • PdAGLU01: 1
  • PdEX: 2
  • PdEX01: 3
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 2.50
  • PdEX1: 2.50
  • PdLoad: 1.00

Sched Class WriteBSR contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BSR16rr
  • BSR32rr
  • BSR64rr
  • BSR16rr
  • BSR32rr
  • BSR64rr
  • BSR16rr
  • BSR32rr
  • BSR64rr
4.03
[4.03;4.04]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
7
  • 4
2.00
  • PdEX: 4
  • PdEX01: 2
  • PdAGLU01: 2.00
  • PdEX0: 2.00
  • PdEX1: 2.00

Sched Class WriteBitTestImmLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BT16mi8 (x6)
  • BT32mi8 (x6)
  • BT64mi8 (x6)
  • BT16mi8 (x6)
  • BT32mi8 (x6)
  • BT64mi8 (x6)
  • BT16mi8 (x6)
  • BT32mi8 (x6)
  • BT64mi8 (x6)
1.62
[1.40;1.86]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteBitTestRegLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BT16mr (x6)
  • BT32mr (x6)
  • BT64mr (x6)
  • BT16mr (x6)
  • BT32mr (x6)
  • BT64mr (x6)
  • BT16mr (x6)
  • BT32mr (x6)
  • BT64mr (x6)
3.54
[3.53;3.56]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
7
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteBitTestSetImmRMW contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
1
  • BTC16mi8 (x6)
  • BTC32mi8 (x6)
  • BTC64mi8 (x6)
  • BTR16mi8 (x6)
  • BTR32mi8 (x6)
  • BTR64mi8 (x6)
  • BTS16mi8 (x6)
  • BTS32mi8 (x6)
  • BTS64mi8 (x6)
  • BTC16mi8 (x6)
  • BTC32mi8 (x6)
  • BTC64mi8 (x6)
  • BTR16mi8 (x6)
  • BTR32mi8 (x6)
  • BTR64mi8 (x6)
  • BTS16mi8 (x6)
  • BTS32mi8 (x6)
  • BTS64mi8 (x6)
  • BTC16mi8 (x6)
  • BTC32mi8 (x6)
  • BTC64mi8 (x6)
  • BTR16mi8 (x6)
  • BTR32mi8 (x6)
  • BTR64mi8 (x6)
  • BTS16mi8 (x6)
  • BTS32mi8 (x6)
  • BTS64mi8 (x6)
21.06
[21.03;21.26]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
5
  • 7
1.00
  • PdAGLU01: 2
  • PdEX01: 1
  • PdLoad: 1
  • PdStore: 1
  • PdAGLU01: 2.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00
  • PdStore: 1.00

Sched Class WriteBitTestSetRegRMW contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
2
  • BTC16mr (x6)
  • BTC32mr (x6)
  • BTC64mr (x6)
  • BTR16mr (x6)
  • BTR32mr (x6)
  • BTR64mr (x6)
  • BTS16mr (x6)
  • BTS32mr (x6)
  • BTS64mr (x6)
  • BTC16mr (x6)
  • BTC32mr (x6)
  • BTC64mr (x6)
  • BTR16mr (x6)
  • BTR32mr (x6)
  • BTR64mr (x6)
  • BTS16mr (x6)
  • BTS32mr (x6)
  • BTS64mr (x6)
  • BTC16mr (x6)
  • BTC32mr (x6)
  • BTC64mr (x6)
  • BTR16mr (x6)
  • BTR32mr (x6)
  • BTR64mr (x6)
  • BTS16mr (x6)
  • BTS32mr (x6)
  • BTS64mr (x6)
22.06
[22.03;22.16]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
11
  • 7
1.00
  • PdAGLU01: 2
  • PdEX01: 1
  • PdLoad: 1
  • PdStore: 1
  • PdAGLU01: 2.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00
  • PdStore: 1.00

Sched Class WriteBitTestSet contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • BTC16ri8 (x15)
  • BTC16rr (x15)
  • BTC32ri8 (x15)
  • BTC32rr (x15)
  • BTC64ri8 (x15)
  • BTC64rr (x15)
  • BTR16ri8 (x15)
  • BTR16rr (x15)
  • BTR32ri8 (x15)
  • BTR32rr (x15)
  • BTR64ri8 (x15)
  • BTR64rr (x15)
  • BTS16ri8 (x15)
  • BTS16rr (x15)
  • BTS32ri8 (x15)
  • BTS32rr (x15)
  • BTS64ri8 (x15)
  • BTS64rr (x15)
  • BTC16ri8 (x15)
  • BTC16rr (x15)
  • BTC32ri8 (x15)
  • BTC32rr (x15)
  • BTC64ri8 (x15)
  • BTC64rr (x15)
  • BTR16ri8 (x15)
  • BTR16rr (x15)
  • BTR32ri8 (x15)
  • BTR32rr (x15)
  • BTR64ri8 (x15)
  • BTR64rr (x15)
  • BTS16ri8 (x15)
  • BTS16rr (x15)
  • BTS32ri8 (x15)
  • BTS32rr (x15)
  • BTS64ri8 (x15)
  • BTS64rr (x15)
  • BTC16ri8 (x15)
  • BTC16rr (x15)
  • BTC32ri8 (x15)
  • BTC32rr (x15)
  • BTC64ri8 (x15)
  • BTC64rr (x15)
  • BTR16ri8 (x15)
  • BTR16rr (x15)
  • BTR32ri8 (x15)
  • BTR32rr (x15)
  • BTR64ri8 (x15)
  • BTR64rr (x15)
  • BTS16ri8 (x15)
  • BTS16rr (x15)
  • BTS32ri8 (x15)
  • BTS32rr (x15)
  • BTS64ri8 (x15)
  • BTS64rr (x15)
1.10
[1.03;1.38]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 2
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class CBW_CWD_CWDE_CDQ_CDQE_CQO contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CBW
  • CDQE
  • CWDE
  • CBW
  • CDQE
  • CWDE
  • CBW
  • CDQE
  • CWDE
1.03
[1.02;1.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class CHS_F_CHS_Fp32_CHS_Fp64_CHS_Fp80 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CHS_F
  • CHS_F
  • CHS_F
2.03
[2.03;2.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
1.00
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class CLD contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CLD
  • CLD
  • CLD
3.03
[3.03;3.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class CLDEMOTE contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CLDEMOTE (x6)
  • CLDEMOTE (x6)
  • CLDEMOTE (x6)
1.22
[1.15;1.30]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdLoad: 1.00

Sched Class CLFLUSH_CLFLUSHOPT contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
3
  • CLFLUSH (x6)
  • CLFLUSH (x6)
45.60
[45.51;45.70]
30
  • CLFLUSH (x6)
46.99
[46.99;46.99]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdLoad: 1.00

Sched Class WriteCMOV2Ld_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMOVA16rm (x14)
  • CMOVA32rm (x14)
  • CMOVA64rm (x14)
  • CMOVBE16rm (x14)
  • CMOVBE32rm (x14)
  • CMOVBE64rm (x14)
  • CMOVA16rm (x14)
  • CMOVA32rm (x14)
  • CMOVA64rm (x14)
  • CMOVBE16rm (x14)
  • CMOVBE32rm (x14)
  • CMOVBE64rm (x14)
  • CMOVA16rm (x14)
  • CMOVA32rm (x14)
  • CMOVA64rm (x14)
  • CMOVBE16rm (x14)
  • CMOVBE32rm (x14)
  • CMOVBE64rm (x14)
1.60
[1.44;1.86]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteCMOVLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMOVAE16rm (x14)
  • CMOVAE32rm (x14)
  • CMOVAE64rm (x14)
  • CMOVB16rm (x14)
  • CMOVB32rm (x14)
  • CMOVB64rm (x14)
  • CMOVE16rm (x14)
  • CMOVE32rm (x14)
  • CMOVE64rm (x14)
  • CMOVNE16rm (x14)
  • CMOVNE32rm (x14)
  • CMOVNE64rm (x14)
  • CMOVNO16rm (x14)
  • CMOVNO32rm (x14)
  • CMOVNO64rm (x14)
  • CMOVNP16rm (x14)
  • CMOVNP32rm (x14)
  • CMOVNP64rm (x14)
  • CMOVNS16rm (x14)
  • CMOVNS32rm (x14)
  • CMOVNS64rm (x14)
  • CMOVO16rm (x14)
  • CMOVO32rm (x14)
  • CMOVO64rm (x14)
  • CMOVP16rm (x14)
  • CMOVP32rm (x14)
  • CMOVP64rm (x14)
  • CMOVS16rm (x14)
  • CMOVS32rm (x14)
  • CMOVS64rm (x14)
  • CMOVAE16rm (x14)
  • CMOVAE32rm (x14)
  • CMOVAE64rm (x14)
  • CMOVB16rm (x14)
  • CMOVB32rm (x14)
  • CMOVB64rm (x14)
  • CMOVE16rm (x14)
  • CMOVE32rm (x14)
  • CMOVE64rm (x14)
  • CMOVNE16rm (x14)
  • CMOVNE32rm (x14)
  • CMOVNE64rm (x14)
  • CMOVNO16rm (x14)
  • CMOVNO32rm (x14)
  • CMOVNO64rm (x14)
  • CMOVNP16rm (x14)
  • CMOVNP32rm (x14)
  • CMOVNP64rm (x14)
  • CMOVNS16rm (x14)
  • CMOVNS32rm (x14)
  • CMOVNS64rm (x14)
  • CMOVO16rm (x14)
  • CMOVO32rm (x14)
  • CMOVO64rm (x14)
  • CMOVP16rm (x14)
  • CMOVP32rm (x14)
  • CMOVP64rm (x14)
  • CMOVS16rm (x14)
  • CMOVS32rm (x14)
  • CMOVS64rm (x14)
  • CMOVAE16rm (x14)
  • CMOVAE32rm (x14)
  • CMOVAE64rm (x14)
  • CMOVB16rm (x14)
  • CMOVB32rm (x14)
  • CMOVB64rm (x14)
  • CMOVE16rm (x14)
  • CMOVE32rm (x14)
  • CMOVE64rm (x14)
  • CMOVNE16rm (x14)
  • CMOVNE32rm (x14)
  • CMOVNE64rm (x14)
  • CMOVNO16rm (x14)
  • CMOVNO32rm (x14)
  • CMOVNO64rm (x14)
  • CMOVNP16rm (x14)
  • CMOVNP32rm (x14)
  • CMOVNP64rm (x14)
  • CMOVNS16rm (x14)
  • CMOVNS32rm (x14)
  • CMOVNS64rm (x14)
  • CMOVO16rm (x14)
  • CMOVO32rm (x14)
  • CMOVO64rm (x14)
  • CMOVP16rm (x14)
  • CMOVP32rm (x14)
  • CMOVP64rm (x14)
  • CMOVS16rm (x14)
  • CMOVS32rm (x14)
  • CMOVS64rm (x14)
1.65
[1.42;2.12]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class CMOVG16rm_CMOVG32rm_CMOVG64rm_CMOVGE16rm_CMOVGE32rm_CMOVGE64rm_CMOVL16rm_CMOVL32rm_CMOVL64rm_CMOVLE16rm_CMOVLE32rm_CMOVLE64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMOVG16rm (x14)
  • CMOVG32rm (x14)
  • CMOVG64rm (x14)
  • CMOVGE16rm (x14)
  • CMOVGE32rm (x14)
  • CMOVGE64rm (x14)
  • CMOVL16rm (x14)
  • CMOVL32rm (x14)
  • CMOVL64rm (x14)
  • CMOVLE16rm (x14)
  • CMOVLE32rm (x14)
  • CMOVLE64rm (x14)
  • CMOVG16rm (x14)
  • CMOVG32rm (x14)
  • CMOVG64rm (x14)
  • CMOVGE16rm (x14)
  • CMOVGE32rm (x14)
  • CMOVGE64rm (x14)
  • CMOVL16rm (x14)
  • CMOVL32rm (x14)
  • CMOVL64rm (x14)
  • CMOVLE16rm (x14)
  • CMOVLE32rm (x14)
  • CMOVLE64rm (x14)
  • CMOVG16rm (x14)
  • CMOVG32rm (x14)
  • CMOVG64rm (x14)
  • CMOVGE16rm (x14)
  • CMOVGE32rm (x14)
  • CMOVGE64rm (x14)
  • CMOVL16rm (x14)
  • CMOVL32rm (x14)
  • CMOVL64rm (x14)
  • CMOVLE16rm (x14)
  • CMOVLE32rm (x14)
  • CMOVLE64rm (x14)
1.62
[1.42;2.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class WriteALULd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMP16mi (x6)
  • CMP16mi8 (x6)
  • CMP32mi (x6)
  • CMP32mi8 (x6)
  • CMP64mi32 (x6)
  • CMP64mi8 (x6)
  • CMP8mi (x6)
  • TEST16mi (x6)
  • TEST32mi (x6)
  • TEST64mi32 (x6)
  • TEST8mi (x6)
  • CMP16mi (x6)
  • CMP16mi8 (x6)
  • CMP32mi (x6)
  • CMP32mi8 (x6)
  • CMP64mi32 (x6)
  • CMP64mi8 (x6)
  • CMP8mi (x6)
  • TEST16mi (x6)
  • TEST32mi (x6)
  • TEST64mi32 (x6)
  • TEST8mi (x6)
  • CMP16mi (x6)
  • CMP16mi8 (x6)
  • CMP32mi (x6)
  • CMP32mi8 (x6)
  • CMP64mi32 (x6)
  • CMP64mi8 (x6)
  • CMP8mi (x6)
  • TEST16mi (x6)
  • TEST32mi (x6)
  • TEST64mi32 (x6)
  • TEST8mi (x6)
1.62
[1.14;2.15]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdEX01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 0.50
  • PdEX1: 0.50
  • PdLoad: 1.00

Sched Class CMPXCHG16B contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
4
  • CMPXCHG16B (x6)
  • CMPXCHG16B (x6)
  • CMPXCHG16B (x6)
69.04
[69.03;69.04]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
22
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class CMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
2
  • CMPXCHG16rm (x6)
  • CMPXCHG16rm (x6)
  • CMPXCHG16rm (x6)
22.63
[22.37;22.86]
1
  • CMPXCHG32rm (x6)
  • CMPXCHG64rm (x6)
  • CMPXCHG32rm (x6)
  • CMPXCHG64rm (x6)
  • CMPXCHG32rm (x6)
  • CMPXCHG64rm (x6)
21.12
[21.04;21.25]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
6
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class WriteCMPXCHG contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMPXCHG16rr
  • CMPXCHG32rr
  • CMPXCHG64rr
  • CMPXCHG16rr
  • CMPXCHG32rr
  • CMPXCHG64rr
  • CMPXCHG16rr
  • CMPXCHG32rr
  • CMPXCHG64rr
3.04
[3.03;3.06]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
5
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class CMPXCHG8B contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
5
  • CMPXCHG8B (x6)
  • CMPXCHG8B (x6)
  • CMPXCHG8B (x6)
26.33
[26.32;26.35]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
18
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class CMPXCHG8rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
2
  • CMPXCHG8rm (x6)
  • CMPXCHG8rm (x6)
  • CMPXCHG8rm (x6)
23.46
[23.36;23.58]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
5
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class CMPXCHG8rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CMPXCHG8rr
  • CMPXCHG8rr
  • CMPXCHG8rr
3.03
[3.03;3.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
3
  • 3
1.00
  • PdEX: 1
  • PdEX1: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.25
  • PdEX1: 1.25

Sched Class COS_F_COS_Fp32_COS_Fp64_COS_Fp80_SIN_F_SIN_Fp32_SIN_Fp64_SIN_Fp80 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
6
  • COS_F
  • COS_F
  • COS_F
64.05
[64.03;64.07]
9
  • SIN_F
  • SIN_F
  • SIN_F
63.08
[63.03;63.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class CPUID contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
7
  • CPUID
  • CPUID
  • CPUID
122.15
[122.12;122.18]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteCRC32Ld_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • CRC32r32m16 (x14)
  • CRC32r32m32 (x14)
  • CRC32r64m64 (x14)
  • CRC32r32m16 (x14)
  • CRC32r32m32 (x14)
  • CRC32r64m64 (x14)
  • CRC32r32m16 (x14)
  • CRC32r32m32 (x14)
  • CRC32r64m64 (x14)
7.05
[6.04;8.05]
0
  • CRC32r32m8 (x14)
  • CRC32r64m8 (x14)
  • CRC32r32m8 (x14)
  • CRC32r64m8 (x14)
  • CRC32r32m8 (x14)
  • CRC32r64m8 (x14)
2.21
[2.05;2.46]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
3
  • 7
2.00
  • PdAGLU01: 1
  • PdEX: 2
  • PdEX01: 3
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 2.50
  • PdEX1: 2.50
  • PdLoad: 1.00

Sched Class CRC32r32r16 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CRC32r32r16 (x15)
  • CRC32r32r16 (x15)
  • CRC32r32r16 (x15)
5.04
[5.03;5.04]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
5
  • 5
2.00
  • PdEX: 4
  • PdEX01: 2
  • PdAGLU01: 2.00
  • PdEX0: 2.00
  • PdEX1: 2.00

Sched Class CRC32r32r32 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • CRC32r32r32 (x15)
  • CRC32r32r32 (x15)
  • CRC32r32r32 (x15)
6.04
[6.03;6.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
7
  • 6
2.00
  • PdEX: 4
  • PdEX01: 2
  • PdAGLU01: 2.00
  • PdEX0: 2.00
  • PdEX1: 2.00

Sched Class CRC32r64r64 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • CRC32r64r64 (x15)
  • CRC32r64r64 (x15)
  • CRC32r64r64 (x15)
8.35
[8.32;8.38]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
11
  • 10
2.00
  • PdEX: 4
  • PdEX01: 2
  • PdAGLU01: 2.00
  • PdEX0: 2.00
  • PdEX1: 2.00

Sched Class WriteCvtI2SDLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CVTSI2SDrm (x6)
  • CVTSI642SDrm (x6)
  • CVTSI2SDrm (x6)
  • CVTSI642SDrm (x6)
  • CVTSI2SDrm (x6)
  • CVTSI642SDrm (x6)
1.68
[1.55;1.86]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 9
1.00
  • PdAGLU01: 1
  • PdFPSTO: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPSTO: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class CVTSI642SSrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CVTSI642SSrr
  • CVTSI642SSrr
  • CVTSI642SSrr
4.03
[4.03;4.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 13
1.00
  • PdFPSTO: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPSTO: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class CVTSS2SI64rm_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CVTSS2SI64rm_Int (x6)
  • CVTSS2SI64rm_Int (x6)
  • CVTSS2SI64rm_Int (x6)
1.63
[1.60;1.68]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 18
1.00
  • PdAGLU01: 1
  • PdEX0: 1
  • PdFPFMA: 1
  • PdFPSTO: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 1.00
  • PdFPFMA: 1.00
  • PdFPSTO: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class CVTSS2SI64rm_Int_CVTTSS2SI64rm_CVTTSS2SI64rm_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CVTTSS2SI64rm (x6)
  • CVTTSS2SI64rm_Int (x6)
  • CVTTSS2SI64rm (x6)
  • CVTTSS2SI64rm_Int (x6)
  • CVTTSS2SI64rm (x6)
  • CVTTSS2SI64rm_Int (x6)
1.69
[1.60;1.96]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 18
1.00
  • PdAGLU01: 1
  • PdEX0: 1
  • PdFPFMA: 1
  • PdFPSTO: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdEX0: 1.00
  • PdFPFMA: 1.00
  • PdFPSTO: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class CWD contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • CWD
  • CWD
  • CWD
1.10
[1.10;1.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteFDiv64XLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVPDrm (x16)
  • VDIVPDrm (x6)
  • DIVPDrm (x16)
  • VDIVPDrm (x6)
  • DIVPDrm (x16)
  • VDIVPDrm (x6)
4.60
[4.53;4.66]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 14
9.50
  • PdAGLU01: 1
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFDiv64X contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVPDrr (x16)
  • VDIVPDrr
  • DIVPDrr (x16)
  • VDIVPDrr
  • DIVPDrr (x16)
  • VDIVPDrr
4.58
[4.53;4.65]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 9
9.50
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteFDivXLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVPSrm (x16)
  • VDIVPSrm (x6)
  • DIVPSrm (x16)
  • VDIVPSrm (x6)
  • DIVPSrm (x16)
  • VDIVPSrm (x6)
4.59
[4.54;4.65]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 14
9.50
  • PdAGLU01: 1
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFDivX contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVPSrr (x16)
  • VDIVPSrr
  • DIVPSrr (x16)
  • VDIVPSrr
  • DIVPSrr (x16)
  • VDIVPSrr
4.59
[4.53;4.64]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 9
9.50
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteFDiv64Ld_ReadAfterVecLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVSDrm (x16)
  • DIVSDrm_Int (x16)
  • VDIVSDrm (x6)
  • VDIVSDrm_Int (x6)
  • DIVSDrm (x16)
  • DIVSDrm_Int (x16)
  • VDIVSDrm (x6)
  • VDIVSDrm_Int (x6)
  • DIVSDrm (x16)
  • DIVSDrm_Int (x16)
  • VDIVSDrm (x6)
  • VDIVSDrm_Int (x6)
4.61
[4.53;4.82]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 14
9.50
  • PdAGLU01: 1
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFDiv64 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVSDrr (x16)
  • DIVSDrr_Int (x16)
  • VDIVSDrr
  • VDIVSDrr_Int
  • DIVSDrr (x16)
  • DIVSDrr_Int (x16)
  • VDIVSDrr
  • VDIVSDrr_Int
  • DIVSDrr (x16)
  • DIVSDrr_Int (x16)
  • VDIVSDrr
  • VDIVSDrr_Int
4.59
[4.54;4.64]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 9
9.50
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteFDivLd_ReadAfterVecLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVSSrm (x16)
  • DIVSSrm_Int (x16)
  • VDIVSSrm (x6)
  • VDIVSSrm_Int (x6)
  • DIVSSrm (x16)
  • DIVSSrm_Int (x16)
  • VDIVSSrm (x6)
  • VDIVSSrm_Int (x6)
  • DIVSSrm (x16)
  • DIVSSrm_Int (x16)
  • VDIVSSrm (x6)
  • VDIVSSrm_Int (x6)
4.59
[4.53;4.65]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 14
9.50
  • PdAGLU01: 1
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFDiv contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DIVSSrr (x16)
  • DIVSSrr_Int (x16)
  • VDIVSSrr
  • VDIVSSrr_Int
  • DIVSSrr (x16)
  • DIVSSrr_Int (x16)
  • VDIVSSrr
  • VDIVSSrr_Int
  • DIVSSrr (x16)
  • DIVSSrr_Int (x16)
  • VDIVSSrr
  • VDIVSSrr_Int
4.61
[4.53;4.85]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 9
9.50
  • PdFPFMA: 19
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 19.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteDPPDLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • DPPDrmi (x16)
  • VDPPDrmi (x6)
  • DPPDrmi (x16)
  • VDPPDrmi (x6)
  • DPPDrmi (x16)
  • VDPPDrmi (x6)
6.87
[6.04;8.67]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
17
  • 20
1.50
  • PdAGLU01: 1
  • PdFPFMA: 3
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 3.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteDPPD contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • DPPDrri (x16)
  • VDPPDrri
  • DPPDrri (x16)
  • VDPPDrri
  • DPPDrri (x16)
  • VDPPDrri
5.27
[5.04;5.45]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
15
  • 15
1.50
  • PdFPFMA: 3
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 3.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class WriteDPPSLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • DPPSrmi (x16)
  • VDPPSrmi (x6)
  • DPPSrmi (x16)
  • VDPPSrmi (x6)
  • DPPSrmi (x16)
  • VDPPSrmi (x6)
8.60
[7.60;9.69]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
18
  • 30
1.50
  • PdAGLU01: 1
  • PdFPFMA: 3
  • PdFPU: 1
  • PdFPU1: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 3.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteDPPS contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
8
  • DPPSrri (x16)
  • DPPSrri (x16)
  • DPPSrri (x16)
7.13
[6.86;7.47]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
16
  • 25
1.50
  • PdFPFMA: 3
  • PdFPU: 1
  • PdFPU1: 1
  • PdFPFMA: 3.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class EXTRACTPSmr_VEXTRACTPSmr contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • EXTRACTPSmr (x6)
  • VEXTRACTPSmr (x6)
  • EXTRACTPSmr (x6)
  • VEXTRACTPSmr (x6)
  • EXTRACTPSmr (x6)
  • VEXTRACTPSmr (x6)
2.10
[1.96;2.38]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
2
  • 13
1.00
  • PdAGLU01: 1
  • PdFPSTO: 1
  • PdFPU: 1
  • PdFPU1: 1
  • PdStore: 1
  • PdAGLU01: 1.00
  • PdFPSTO: 1.00
  • PdFPU0: 0.25
  • PdFPU1: 1.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdStore: 1.00

Sched Class EXTRQ_EXTRQI contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • EXTRQ (x16)
  • EXTRQI (x16)
  • EXTRQ (x16)
  • EXTRQI (x16)
  • EXTRQ (x16)
  • EXTRQI (x16)
1.35
[1.14;1.52]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 3
0.50
  • PdFPMAL: 1
  • PdFPU: 1
  • PdFPU01: 1
  • PdFPMAL: 1.00
  • PdFPU0: 0.75
  • PdFPU1: 0.75
  • PdFPU2: 0.25
  • PdFPU3: 0.25

Sched Class F2XM1 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
9
  • F2XM1
  • F2XM1
  • F2XM1
63.06
[63.03;63.12]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FBLDm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
10
  • FBLDm (x6)
  • FBLDm (x6)
  • FBLDm (x6)
35.68
[35.66;35.72]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FBSTPm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
11
  • FBSTPm (x6)
  • FBSTPm (x6)
  • FBSTPm (x6)
90.05
[90.04;90.06]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FLDCW16m contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • FLDCW16m (x6)
  • FLDCW16m (x6)
  • FLDCW16m (x6)
3.04
[3.04;3.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 5
0.50
  • PdAGLU01: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdLoad: 1.00

Sched Class FLDENVm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
12
  • FLDENVm (x6)
  • FLDENVm (x6)
  • FLDENVm (x6)
249.18
[249.15;249.22]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FNCLEX_FXTRACT contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
13
  • FNCLEX
  • FNCLEX
  • FNCLEX
57.05
[57.03;57.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FNINIT contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
14
  • FNINIT
  • FNINIT
  • FNINIT
140.05
[140.05;140.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FNSTCW16m contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • FNSTCW16m (x6)
  • FNSTCW16m (x6)
  • FNSTCW16m (x6)
2.07
[2.06;2.10]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FNSTSW16r contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
15
  • FNSTSW16r
  • FNSTSW16r
  • FNSTSW16r
20.03
[20.02;20.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 1
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FNSTSWm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
16
  • FNSTSWm (x6)
  • FNSTSWm (x6)
  • FNSTSWm (x6)
18.05
[18.04;18.06]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FPATAN contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
17
  • FPATAN
  • FPATAN
  • FPATAN
62.06
[62.04;62.08]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FPREM contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
18
  • FPREM
  • FPREM
  • FPREM
16.03
[16.03;16.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FPREM1 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
18
  • FPREM1
  • FPREM1
  • FPREM1
16.03
[16.02;16.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FPTAN contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
19
  • FPTAN
  • FPTAN
  • FPTAN
70.04
[70.03;70.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FRNDINT contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • FRNDINT
  • FRNDINT
  • FRNDINT
4.03
[4.02;4.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FRSTORm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
20
  • FRSTORm (x6)
  • FRSTORm (x6)
  • FRSTORm (x6)
247.18
[247.17;247.21]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FSAVEm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
21
  • FSAVEm (x6)
  • FSAVEm (x6)
  • FSAVEm (x6)
311.05
[311.05;311.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FSCALE contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
22
  • FSCALE
  • FSCALE
  • FSCALE
58.03
[58.03;58.03]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FSINCOS contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
4
  • FSINCOS
  • FSINCOS
  • FSINCOS
69.04
[69.03;69.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FSTENVm contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
23
  • FSTENVm (x6)
  • FSTENVm (x6)
  • FSTENVm (x6)
218.04
[218.04;218.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FXSAVE_FXSAVE64 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
24
  • FXSAVE (x6)
  • FXSAVE64 (x6)
  • FXSAVE (x6)
  • FXSAVE64 (x6)
  • FXSAVE (x6)
  • FXSAVE64 (x6)
142.22
[142.20;142.25]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FXTRACT contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
25
  • FXTRACT
  • FXTRACT
  • FXTRACT
83.08
[83.03;83.16]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FYL2X contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
17
  • FYL2X
  • FYL2X
  • FYL2X
62.04
[62.03;62.05]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class FYL2XP1 contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
17
  • FYL2XP1
  • FYL2XP1
62.06
[62.03;62.09]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
1
  • 100
0.50
  • PdEX: 1
  • PdEX01: 1
  • PdAGLU01: 0.50
  • PdEX0: 0.75
  • PdEX1: 0.75

Sched Class WriteFHAddLd_ReadAfterVecXLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • HADDPDrm (x16)
  • HADDPSrm (x16)
  • HSUBPDrm (x16)
  • HSUBPSrm (x16)
  • VHADDPDrm (x6)
  • VHADDPSrm (x6)
  • VHSUBPDrm (x6)
  • VHSUBPSrm (x6)
  • HADDPDrm (x16)
  • HADDPSrm (x16)
  • HSUBPDrm (x16)
  • HSUBPSrm (x16)
  • VHADDPDrm (x6)
  • VHADDPSrm (x6)
  • VHSUBPDrm (x6)
  • VHSUBPSrm (x6)
  • HADDPDrm (x16)
  • HADDPSrm (x16)
  • HSUBPDrm (x16)
  • HSUBPSrm (x16)
  • VHADDPDrm (x6)
  • VHADDPSrm (x6)
  • VHSUBPDrm (x6)
  • VHSUBPSrm (x6)
2.23
[2.04;3.07]

llvm SchedModel data:

ValidVariantNumMicroOpsLatencyRThroughputWriteProcResIdealized Resource Pressure
4
  • 16
1.00
  • PdAGLU01: 1
  • PdFPFMA: 1
  • PdFPU: 1
  • PdFPU0: 1
  • PdLoad: 1
  • PdAGLU01: 1.00
  • PdFPFMA: 1.00
  • PdFPU0: 1.25
  • PdFPU1: 0.25
  • PdFPU2: 0.25
  • PdFPU3: 0.25
  • PdLoad: 1.00

Sched Class WriteFHAdd contains instructions whose performance characteristics do not match that of LLVM:

ClusterIdOpcode/Configinverse_throughput
0
  • HADDPDrr (x16)
  • HADDPSrr (x16)
  • HSUBPDrr (x16)
  • HSUBPSrr (x16)
  • VHADDPDrr
  • VHADDPSrr
  • VHSUBPDrr
  • VHSUBPSrr
  • HADDPDrr (x16)
  • HADDPSrr (x16)
  • HSUBPDrr (x16)
  • HSUBPSrr (x16)
  • VHADDPDrr