llvm-exegesis Analysis Results

ClusterId	Opcode/Config	NumMicroOps
6	XGETBV	4.00 [4.00;4.00]

Sched Class WriteFTestYLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	VTESTPDYrm (x6) VTESTPSYrm (x6)	6.00 [6.00;6.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	4	11	PdEX: 3 PdEX0: 1 PdFPFMA: 2 PdFPU: 2 PdFPU01: 1	PdAGLU01: 1.50 PdEX0: 1.75 PdEX1: 0.75 PdFPFMA: 2.00 PdFPU0: 1.00 PdFPU1: 1.00 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class WriteVecTestYLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	VPTESTYrm (x6)	6.00 [6.00;6.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	4	11	PdEX: 3 PdEX0: 1 PdFPFMA: 2 PdFPU: 2 PdFPU01: 1	PdAGLU01: 1.50 PdEX0: 1.75 PdEX1: 0.75 PdFPFMA: 2.00 PdFPU0: 1.00 PdFPU1: 1.00 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class VINSERTF128rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VINSERTF128rr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPFMA: 1 PdFPU: 1 PdFPU01: 1	PdFPFMA: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteFHAddYLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
7	VHADDPDYrm (x6) VHADDPSYrm (x6) VHSUBPDYrm (x6) VHSUBPSYrm (x6)	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	8	21	PdEX: 2 PdFPFMA: 1 PdFPU: 2 PdFPU0: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPU0: 2.50 PdFPU1: 0.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class WriteFRndYLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	VFRCZPDYrm (x6) VFRCZPSYrm (x6)	8.00 [8.00;8.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	14	PdEX: 2 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class WriteCvtPH2PSLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	VCVTPH2PSrm (x6)	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteCvtPH2PSYLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
5	VCVTPH2PSYrm (x6)	7.00 [7.00;7.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	4	18	PdEX: 2 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class WriteCvtPD2PSLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VCVTPD2PSrm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteCvtPD2PSYLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	VCVTPD2PSYrm (x6)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	18	PdEX: 2 PdFPFMA: 1 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class VCOMISDrr_VCOMISDrr_Int_VCOMISSrr_VCOMISSrr_Int_VUCOMISDrr_VUCOMISDrr_Int_VUCOMISSrr_VUCOMISSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VCOMISDrr VCOMISDrr_Int VCOMISSrr VCOMISSrr_Int VUCOMISDrr VUCOMISDrr_Int VUCOMISSrr VUCOMISSrr_Int	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class VBROADCASTF128 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VBROADCASTF128 (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	7	PdEX: 1 PdFPFMA: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class ST_FP32m_ST_FP64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	ST_FP32m (x6) ST_FP64m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class ISTT_FP16m_ISTT_FP32m_ISTT_FP64m_ST_F32m_ST_F64m_ST_FP32m_ST_FP64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	ST_F32m (x6) ST_F64m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class SGDT64m_SIDT64m_SMSW16m_STRm_SYSCALL contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
4	SGDT64m (x6) SIDT64m (x6)	9.00 [9.00;9.00]
3	SMSW16m (x6) STRm (x6)	6.00 [6.00;6.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class SFENCE contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
5	SFENCE	7.00 [7.00;7.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class SAR16mCL_SAR32mCL_SAR64mCL_SAR8mCL_SHL16mCL_SHL32mCL_SHL64mCL_SHL8mCL_SHR16mCL_SHR32mCL_SHR64mCL_SHR8mCL contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	SAR16mCL (x6) SAR32mCL (x6) SAR64mCL (x6) SAR8mCL (x6) SHL16mCL (x6) SHL32mCL (x6) SHL64mCL (x6) SHL8mCL (x6) SHR16mCL (x6) SHR32mCL (x6) SHR64mCL (x6) SHR8mCL (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class SAR16m1_SAR16mi_SAR32m1_SAR32mi_SAR64m1_SAR64mi_SAR8m1_SAR8mi_SHL16m1_SHL16mi_SHL32m1_SHL32mi_SHL64m1_SHL64mi_SHL8m1_SHL8mi_SHR16m1_SHR16mi_SHR32m1_SHR32mi_SHR64m1_SHR64mi_SHR8m1_SHR8mi contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	SAR16m1 (x6) SAR16mi (x6) SAR32m1 (x6) SAR32mi (x6) SAR64m1 (x6) SAR64mi (x6) SAR8m1 (x6) SAR8mi (x6) SHL16m1 (x6) SHL16mi (x6) SHL32m1 (x6) SHL32mi (x6) SHL64m1 (x6) SHL64mi (x6) SHL8m1 (x6) SHL8mi (x6) SHR16m1 (x6) SHR16mi (x6) SHR32m1 (x6) SHR32mi (x6) SHR64m1 (x6) SHR64mi (x6) SHR8m1 (x6) SHR8mi (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class ROL16mCL_ROL32mCL_ROL64mCL_ROL8mCL_ROR16mCL_ROR32mCL_ROR64mCL_ROR8mCL contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ROL16mCL (x6) ROL32mCL (x6) ROL64mCL (x6) ROL8mCL (x6) ROR16mCL (x6) ROR32mCL (x6) ROR64mCL (x6) ROR8mCL (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class RDTSC_RDTSCP contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
22	RDTSCP	40.00 [40.00;40.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class RDTSC contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
22	RDTSC	40.00 [40.00;40.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteFRndLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ROUNDSDm (x6) ROUNDSDm_Int (x16) ROUNDSSm (x6) ROUNDSSm_Int (x16) VROUNDSDm (x6) VROUNDSDm_Int (x6) VROUNDSSm (x6) VROUNDSSm_Int (x6)	1.00 [1.00;1.00]
12	VFRCZPDrm (x6) VFRCZPSrm (x6) VFRCZSDrm (x6) VFRCZSSrm (x6)	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	9	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class RCL16mCL_RCL32mCL_RCL64mCL_RCL8mCL_RCR16mCL_RCR32mCL_RCR64mCL_RCR8mCL_ROL16mCL_ROL32mCL_ROL64mCL_ROL8mCL_ROR16mCL_ROR32mCL_ROR64mCL_ROR8mCL contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
15	RCR16mCL (x6) RCR32mCL (x6) RCR64mCL (x6)	15.00 [15.00;15.00]
21	RCR8mCL (x6)	19.00 [19.00;19.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class RCL16m1_RCL16mi_RCL32m1_RCL32mi_RCL64m1_RCL64mi_RCL8m1_RCL8mi_RCR16m1_RCR16mi_RCR32m1_RCR32mi_RCR64m1_RCR64mi_RCR8m1_RCR8mi_ROL16m1_ROL16mi_ROL32m1_ROL32mi_ROL64m1_ROL64mi_ROL8m1_ROL8mi_ROR16m1_ROR16mi_ROR32m1_ROR32mi_ROR64m1_ROR64mi_ROR8m1_ROR8mi contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	RCL16m1 (x6) RCL32m1 (x6) RCL64m1 (x6) RCL8m1 (x6) RCR16m1 (x6) RCR32m1 (x6) RCR64m1 (x6) RCR8m1 (x6)	1.00 [1.00;1.00]
11	RCL16mi (x6)	18.00 [18.00;18.00]
14	RCL32mi (x6) RCL64mi (x6)	17.00 [17.00;17.01]
9	RCL8mi (x6)	22.00 [22.00;22.00]
16	RCR16mi (x6) RCR32mi (x6) RCR64mi (x6)	16.00 [16.00;16.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class PSUBBrr_PSUBDrr_PSUBWrr_VPSUBBrr_VPSUBDrr_VPSUBQrr_VPSUBWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	PSUBBrr (x16) PSUBDrr (x16) PSUBWrr (x16) VPSUBBrr VPSUBDrr VPSUBQrr VPSUBWrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class VCVTPD2DQYrm_VCVTTPD2DQYrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	VCVTPD2DQYrm (x6) VCVTTPD2DQYrm (x6)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	18	PdEX: 2 PdFPFMA: 1 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class VCVTPD2DQrm_VCVTTPD2DQrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VCVTPD2DQrm (x6) VCVTTPD2DQrm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class VEXTRACTF128mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VEXTRACTF128mr (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePHAddX contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	PHADDWrr (x16) PHSUBWrr (x16) VPHADDDrr VPHADDWrr VPHSUBDrr VPHSUBWrr	3.00 [3.00;3.00]
0	VPHADDBDrr VPHADDBQrr VPHADDBWrr VPHADDDQrr VPHADDUBDrr VPHADDUBQrr VPHADDUBWrr VPHADDUDQrr VPHADDUWDrr VPHADDUWQrr VPHADDWDrr VPHADDWQrr VPHSUBBWrr VPHSUBDQrr VPHSUBWDrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePHAddXLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	PHADDWrm (x16) PHSUBWrm (x16) VPHADDDrm (x6) VPHADDWrm (x6) VPHSUBDrm (x6) VPHSUBWrm (x6)	4.00 [4.00;4.00]
0	VPHADDBDrm (x6) VPHADDBQrm (x6) VPHADDBWrm (x6) VPHADDDQrm (x6) VPHADDUBDrm (x6) VPHADDUBQrm (x6) VPHADDUBWrm (x6) VPHADDUDQrm (x6) VPHADDUWDrm (x6) VPHADDUWQrm (x6) VPHADDWDrm (x6) VPHADDWQrm (x6) VPHSUBBWrm (x6) VPHSUBDQrm (x6) VPHSUBWDrm (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	7	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDSWrr_VPHADDSWrr_PHSUBSWrr_VPHSUBSWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	PHADDSWrr (x16) PHSUBSWrr (x16) VPHADDSWrr VPHSUBSWrr	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDSWrm_VPHADDSWrm_PHSUBSWrm_VPHSUBSWrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	PHADDSWrm (x16) PHSUBSWrm (x16) VPHADDSWrm (x6) VPHSUBSWrm (x6)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	7	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDDrr_PHSUBDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	PHADDDrr (x16) PHSUBDrr (x16)	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PHADDDrm_PHSUBDrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	PHADDDrm (x16) PHSUBDrm (x16)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	7	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePCmpIStrMLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
4	PCMPISTRMrm (x6) VPCMPISTRMrm (x6)	9.00 [9.00;9.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	7	12	PdEX: 2 PdEX0: 1 PdFPFMA: 2 PdFPU: 1 PdFPU1: 1	PdAGLU01: 1.00 PdEX0: 1.50 PdEX1: 0.50 PdFPFMA: 2.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePCmpIStrILd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	PCMPISTRIrm (x6) VPCMPISTRIrm (x6)	8.00 [8.00;8.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	7	20	PdEX: 2 PdEX0: 1 PdFPFMA: 2 PdFPU: 1 PdFPU1: 1	PdAGLU01: 1.00 PdEX0: 1.50 PdEX1: 0.50 PdFPFMA: 2.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePCmpEStrMLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
19	PCMPESTRMrm (x6) VPCMPESTRMrm (x6)	28.00 [28.00;28.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	27	15	PdEX: 10 PdEX0: 1 PdFPFMA: 1 PdFPMAL: 4 PdFPU: 1 PdFPU1: 1	PdAGLU01: 5.00 PdEX0: 3.50 PdEX1: 2.50 PdFPFMA: 1.00 PdFPMAL: 4.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WritePCmpEStrILd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
19	PCMPESTRIrm (x6) VPCMPESTRIrm (x6)	28.00 [28.00;28.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	27	10	PdEX: 10 PdEX0: 1 PdFPFMA: 1 PdFPMAL: 4 PdFPU: 1 PdFPU1: 1	PdAGLU01: 5.00 PdEX0: 3.50 PdEX1: 2.50 PdFPFMA: 1.00 PdFPMAL: 4.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteCLMulLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	PCLMULQDQrm (x16)	6.01 [6.01;6.01]
5	VPCLMULQDQrm (x6)	7.00 [7.00;7.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	5	17	PdEX: 1 PdFPMMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class PAUSE contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	PAUSE	8.00 [8.00;8.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class PANDNrr_VPANDNrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	PANDNrr (x16) VPANDNrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class ANDNPSrr_VANDNPSrr_ANDNPDrr_VANDNPDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ANDNPDrr (x16) ANDNPSrr (x16) VANDNPDrr VANDNPSrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class FNCLEX_FXTRACT contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
11	FNCLEX	18.01 [18.01;18.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class MMX_PHADDSWrm_MMX_PHADDWrm_MMX_PHSUBSWrm_MMX_PHSUBWrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	MMX_PHADDWrm (x8) MMX_PHSUBWrm (x8)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	10	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteDPPSLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
11	DPPSrmi (x16)	18.00 [18.00;18.00]
21	VDPPSrmi (x6)	19.00 [19.00;19.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	16	30	PdEX: 1 PdFPFMA: 3 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 3.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteDPPDLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
14	DPPDrmi (x16) VDPPDrmi (x6)	17.00 [17.00;17.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	15	20	PdEX: 1 PdFPFMA: 3 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 3.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class DIVR_FI16m_DIVR_FI32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	DIVR_FI16m (x6) DIVR_FI32m (x6)	2.00 [2.00;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	14	PdEX: 1 PdFPFMA: 19 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 19.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class FXTRACT contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
16	FXTRACT	16.00 [16.00;16.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteMPSAD contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	MPSADBWrri (x16)	8.00 [8.00;8.00]
7	VMPSADBWrri	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	9	8	PdFPMMA: 2 PdFPU: 1 PdFPU0: 1	PdFPMMA: 2.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class DEC16m_DEC32m_DEC64m_DEC8m_INC16m_INC32m_INC64m_INC8m_NEG16m_NEG32m_NEG64m_NEG8m_NOT16m_NOT32m_NOT64m_NOT8m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	DEC16m (x6) DEC32m (x6) DEC64m (x6) DEC8m (x6) INC16m (x6) INC32m (x6) INC64m (x6) INC8m (x6) NEG16m (x6) NEG32m (x6) NEG64m (x6) NEG8m (x6) NOT16m (x6) NOT32m (x6) NOT64m (x6) NOT8m (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class DIVR_FI16m_DIVR_FI32m_DIV_FI16m_DIV_FI32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	DIV_FI16m (x6) DIV_FI32m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	14	PdEX: 1 PdFPFMA: 19 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 19.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class RCL16mCL_RCL32mCL_RCL64mCL_RCL8mCL contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
14	RCL16mCL (x6)	17.01 [17.01;17.01]
16	RCL32mCL (x6) RCL64mCL (x6)	16.00 [16.00;16.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class STR16r_STR32r_STR64r contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	STR16r STR32r STR64r	6.00 [6.00;6.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CVTPD2PSrr_VCVTPD2PSrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTPD2PSrr VCVTPD2PSrr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteIMul64ImmLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	IMUL64rmi32 (x6) IMUL64rmi8 (x6)	2.00 [2.00;2.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	10	PdEX: 2 PdEX1: 1 PdMul: 4	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 1.50 PdMul: 4.00

Sched Class BTC16mr_BTC32mr_BTC64mr_BTR16mr_BTR32mr_BTR64mr_BTS16mr_BTS32mr_BTS64mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
7	BTC16mr (x6) BTC32mr (x6) BTC64mr (x6) BTR16mr (x6) BTR32mr (x6) BTR64mr (x6) BTS16mr (x6) BTS32mr (x6) BTS64mr (x6)	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	11	7	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteCRC32Ld_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
10	CRC32r32m16 (x14)	5.00 [5.00;5.00]
5	CRC32r32m32 (x14)	7.00 [7.00;7.00]
12	CRC32r32m8 (x14) CRC32r64m8 (x14)	3.00 [3.00;3.00]
13	CRC32r64m64 (x14)	11.00 [11.00;11.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	7	PdEX: 5 PdEX01: 2	PdAGLU01: 2.50 PdEX0: 2.25 PdEX1: 2.25

Sched Class COMISDrm_COMISDrm_Int_COMISSrm_COMISSrm_Int_UCOMISDrm_UCOMISDrm_Int_UCOMISSrm_UCOMISSrm_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	COMISDrm (x6) COMISDrm_Int (x6) COMISSrm (x6) COMISSrm_Int (x6) UCOMISDrm (x6) UCOMISDrm_Int (x6) UCOMISSrm (x6) UCOMISSrm_Int (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	6	PdEX: 2 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 1.00 PdEX0: 1.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CMPXCHG8rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	CMPXCHG8rr	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	5	3	PdEX: 1 PdEX1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 1.25

Sched Class CMPXCHG8rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
10	CMPXCHG8rm (x6)	5.00 [5.00;5.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	3	PdEX: 3 PdEX1: 1	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 1.75

Sched Class CMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	CMPXCHG16rm (x6) CMPXCHG32rm (x6) CMPXCHG64rm (x6)	6.00 [6.00;6.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	3	PdEX: 3 PdEX1: 1	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 1.75

Sched Class CMPXCHG8B contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
11	CMPXCHG8B (x6)	18.00 [18.00;18.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	3	PdEX: 3 PdEX1: 1	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 1.75

Sched Class CMPXCHG16B contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
9	CMPXCHG16B (x6)	22.01 [22.01;22.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	3	PdEX: 3 PdEX1: 1	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 1.75

Sched Class FPATAN contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
7	FPATAN	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class SUB32rr_SUB64rr_XOR32rr_XOR64rr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	SUB32rr (x15) SUB64rr (x15) XOR32rr (x15) XOR64rr (x15)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class COS_F_COS_Fp32_COS_Fp64_COS_Fp80_SIN_F_SIN_Fp32_SIN_Fp64_SIN_Fp80 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
13	COS_F SIN_F	11.01 [11.00;11.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class SETAm_SETBEm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	SETAm (x6) SETBEm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50

Sched Class FNSTCW16m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	FNSTCW16m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CVTDQ2PDrr_VCVTDQ2PDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTDQ2PDrr VCVTDQ2PDrr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class FYL2X contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
4	FYL2X	9.00 [9.00;9.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class MMX_PHADDSWrm_MMX_PHSUBSWrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	MMX_PHADDSWrm (x8) MMX_PHSUBSWrm (x8)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	10	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CLD contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CLD	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class F2XM1 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
7	F2XM1	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CVTPD2DQrr_CVTTPD2DQrr_VCVTPD2DQrr_VCVTTPD2DQrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTPD2DQrr CVTTPD2DQrr VCVTPD2DQrr VCVTTPD2DQrr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class XSAVE contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
22	XSAVE (x6)	40.00 [40.00;40.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class ADD16mi_ADD16mi8_ADD16mr_ADD32mi_ADD32mi8_ADD32mr_ADD64mi32_ADD64mi8_ADD64mr_ADD8mi_ADD8mi8_ADD8mr_SUB16mi_SUB16mi8_SUB16mr_SUB32mi_SUB32mi8_SUB32mr_SUB64mi32_SUB64mi8_SUB64mr_SUB8mi_SUB8mi8_SUB8mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ADD16mi (x6) ADD16mi8 (x6) ADD16mr (x6) ADD32mi (x6) ADD32mi8 (x6) ADD32mr (x6) ADD64mi32 (x6) ADD64mi8 (x6) ADD64mr (x6) ADD8mi (x6) ADD8mr (x6) SUB16mi (x6) SUB16mi8 (x6) SUB16mr (x6) SUB32mi (x6) SUB32mi8 (x6) SUB32mr (x6) SUB64mi32 (x6) SUB64mi8 (x6) SUB64mr (x6) SUB8mi (x6) SUB8mr (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CVTSD2SSrr_CVTSD2SSrr_Int_VCVTSD2SSrr_VCVTSD2SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	CVTSD2SSrr CVTSD2SSrr_Int (x16) VCVTSD2SSrr VCVTSD2SSrr_Int	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTSI2SDrr_CVTSI2SDrr_Int_CVTSI642SDrr_CVTSI642SDrr_Int_VCVTSI2SDrr_VCVTSI2SDrr_Int_VCVTSI642SDrr_VCVTSI642SDrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTSI2SDrr CVTSI2SDrr_Int (x16) CVTSI642SDrr CVTSI642SDrr_Int (x16) VCVTSI2SDrr VCVTSI2SDrr_Int VCVTSI642SDrr VCVTSI642SDrr_Int	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTSI2SSrr_CVTSI2SSrr_Int_VCVTSI2SSrr_VCVTSI2SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTSI2SSrr CVTSI2SSrr_Int (x16) VCVTSI2SSrr VCVTSI2SSrr_Int	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class XSAVE64 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
22	XSAVE64 (x6)	40.01 [40.01;40.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class FYL2XP1 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
7	FYL2XP1	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class VINSERTF128rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VINSERTF128rm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	7	PdEX: 1 PdFPFMA: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteALULd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	BLCFILL32rm (x6) BLCFILL64rm (x6) BLCI32rm (x6) BLCI64rm (x6) BLCIC32rm (x6) BLCIC64rm (x6) BLCMSK32rm (x6) BLCMSK64rm (x6) BLCS32rm (x6) BLCS64rm (x6) BLSFILL32rm (x6) BLSFILL64rm (x6) BLSIC32rm (x6) BLSIC64rm (x6) T1MSKC32rm (x6) T1MSKC64rm (x6) TZMSK32rm (x6) TZMSK64rm (x6)	2.00 [2.00;2.00]
0	CMP16mi (x6) CMP16mi8 (x6) CMP32mi (x6) CMP32mi8 (x6) CMP64mi32 (x6) CMP64mi8 (x6) CMP8mi (x6) TEST16mi (x6) TEST32mi (x6) TEST64mi32 (x6) TEST8mi (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50

Sched Class WriteALU contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ADD16i16 ADD16ri (x15) ADD16ri8 (x15) ADD16ri8_DB (x15) ADD16ri_DB (x15) ADD16rr (x15) ADD16rr_DB (x15) ADD16rr_REV (x15) ADD32i32 ADD32ri (x15) ADD32ri8 (x15) ADD32ri8_DB (x15) ADD32ri_DB (x15) ADD32rr (x15) ADD32rr_DB (x15) ADD32rr_REV (x15) ADD64i32 ADD64ri32 (x15) ADD64ri32_DB (x15) ADD64ri8 (x15) ADD64ri8_DB (x15) ADD64rr (x15) ADD64rr_DB (x15) ADD64rr_REV (x15) ADD8i8 ADD8ri (x19) AND16i16 AND16ri (x15) AND16ri8 (x15) AND16rr (x15) AND16rr_REV (x15) AND32i32 AND32ri (x15) AND32ri8 (x15) AND32rr (x15) AND32rr_REV (x15) AND64i32 AND64ri32 (x15) AND64ri8 (x15) AND64rr (x15) AND64rr_REV (x15) AND8i8 AND8ri (x19) CMP16i16 CMP16ri CMP16ri8 CMP16rr CMP16rr_REV CMP32i32 CMP32ri CMP32ri8 CMP32rr CMP32rr_REV CMP64i32 CMP64ri32 CMP64ri8 CMP64rr CMP64rr_REV CMP8i8 CMP8ri CMP8rr CMP8rr_REV DEC16r (x15) DEC32r (x15) DEC64r (x15) DEC8r (x19) INC16r (x15) INC32r (x15) INC64r (x15) INC8r (x19) MOVSX16rr16 MOVZX16rr16 NEG16r (x15) NEG32r (x15) NEG64r (x15) NEG8r (x19) NOT16r (x15) NOT32r (x15) NOT64r (x15) NOT8r (x19) OR16i16 OR16ri (x15) OR16ri8 (x15) OR16rr (x15) OR16rr_REV (x15) OR32i32 OR32ri (x15) OR32ri8 (x15) OR32rr (x15) OR32rr_REV (x15) OR64i32 OR64ri32 (x15) OR64ri8 (x15) OR64rr (x15) OR64rr_REV (x15) OR8i8 OR8ri (x19) SUB16i16 SUB16ri (x15) SUB16ri8 (x15) SUB16rr (x15) SUB16rr_REV (x15) SUB32i32 SUB32ri (x15) SUB32ri8 (x15) SUB32rr_REV (x15) SUB64i32 SUB64ri32 (x15) SUB64ri8 (x15) SUB64rr_REV (x15) SUB8i8 SUB8ri (x19) TEST16i16 TEST16ri TEST16rr TEST32i32 TEST32ri TEST32rr TEST64i32 TEST64ri32 TEST64rr TEST8i8 TEST8ri TEST8rr XOR16i16 XOR16ri (x15) XOR16ri8 (x15) XOR16rr (x15) XOR16rr_REV (x15) XOR32i32 XOR32ri (x15) XOR32ri8 (x15) XOR32rr_REV (x15) XOR64i32 XOR64ri32 (x15) XOR64ri8 (x15) XOR64rr_REV (x15) XOR8i8 XOR8ri (x19)	1.00 [1.00;1.01]
1	BLCFILL32rr BLCFILL64rr BLCI32rr BLCI64rr BLCIC32rr BLCIC64rr BLCMSK32rr BLCMSK64rr BLCS32rr BLCS64rr BLSFILL32rr BLSFILL64rr BLSIC32rr BLSIC64rr T1MSKC32rr T1MSKC64rr TZMSK32rr TZMSK64rr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class CWD contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CWD	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class VERRm_VERWm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
17	VERRm (x6) VERWm (x6)	45.00 [45.00;45.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteALULd_WriteRMW contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	LCMPXCHG16 (x6) LCMPXCHG32 (x6) LCMPXCHG64 (x6)	6.00 [6.00;6.01]
9	LCMPXCHG16B (x6)	22.00 [22.00;22.00]
10	LCMPXCHG8 (x6)	5.00 [5.00;5.00]
11	LCMPXCHG8B (x6)	18.00 [18.00;18.00]
0	LOCK_ADD16mi (x6) LOCK_ADD16mi8 (x6) LOCK_ADD16mr (x6) LOCK_ADD32mi (x6) LOCK_ADD32mi8 (x6) LOCK_ADD32mr (x6) LOCK_ADD64mi32 (x6) LOCK_ADD64mi8 (x6) LOCK_ADD64mr (x6) LOCK_ADD8mi (x6) LOCK_ADD8mr (x6) LOCK_AND16mi (x6) LOCK_AND16mi8 (x6) LOCK_AND16mr (x6) LOCK_AND32mi (x6) LOCK_AND32mi8 (x6) LOCK_AND32mr (x6) LOCK_AND64mi32 (x6) LOCK_AND64mi8 (x6) LOCK_AND64mr (x6) LOCK_AND8mi (x6) LOCK_AND8mr (x6) LOCK_DEC16m (x6) LOCK_DEC32m (x6) LOCK_DEC64m (x6) LOCK_DEC8m (x6) LOCK_INC16m (x6) LOCK_INC32m (x6) LOCK_INC64m (x6) LOCK_INC8m (x6) LOCK_OR16mi (x6) LOCK_OR16mi8 (x6) LOCK_OR16mr (x6) LOCK_OR32mi (x6) LOCK_OR32mi8 (x6) LOCK_OR32mr (x6) LOCK_OR64mi32 (x6) LOCK_OR64mi8 (x6) LOCK_OR64mr (x6) LOCK_OR8mi (x6) LOCK_OR8mr (x6) LOCK_SUB16mi (x6) LOCK_SUB16mi8 (x6) LOCK_SUB16mr (x6) LOCK_SUB32mi (x6) LOCK_SUB32mi8 (x6) LOCK_SUB32mr (x6) LOCK_SUB64mi32 (x6) LOCK_SUB64mi8 (x6) LOCK_SUB64mr (x6) LOCK_SUB8mi (x6) LOCK_SUB8mr (x6) LOCK_XOR16mi (x6) LOCK_XOR16mi8 (x6) LOCK_XOR16mr (x6) LOCK_XOR32mi (x6) LOCK_XOR32mi8 (x6) LOCK_XOR32mr (x6) LOCK_XOR64mi32 (x6) LOCK_XOR64mi8 (x6) LOCK_XOR64mr (x6) LOCK_XOR8mi (x6) LOCK_XOR8mr (x6)	1.00 [1.00;1.01]
6	LXADD16 (x14) LXADD32 (x14) LXADD64 (x14) LXADD8 (x18)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class COMISDrr_COMISDrr_Int_COMISSrr_COMISSrr_Int_UCOMISDrr_UCOMISDrr_Int_UCOMISSrr_UCOMISSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	COMISDrr COMISDrr_Int COMISSrr COMISSrr_Int UCOMISDrr UCOMISDrr_Int UCOMISSrr UCOMISSrr_Int	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 1.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class FNSTSWm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	FNSTSWm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class SLDT16r_SLDT32r_SLDT64r_STR16r_STR32r_STR64r contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
3	SLDT16r SLDT32r SLDT64r	6.00 [6.00;6.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class ADC8mr_ADC16mr_ADC32mr_ADC64mr_SBB8mr_SBB16mr_SBB32mr_SBB64mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ADC16mr (x6) ADC32mr (x6) ADC64mr (x6) ADC8mr (x6) SBB16mr (x6) SBB32mr (x6) SBB64mr (x6) SBB8mr (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 4	PdAGLU01: 2.00 PdEX0: 1.00 PdEX1: 1.00

Sched Class BTC16mi8_BTC32mi8_BTC64mi8_BTR16mi8_BTR32mi8_BTR64mi8_BTS16mi8_BTS32mi8_BTS64mi8 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	BTC16mi8 (x6) BTC32mi8 (x6) BTC64mi8 (x6) BTR16mi8 (x6) BTR32mi8 (x6) BTR64mi8 (x6) BTS16mi8 (x6) BTS32mi8 (x6) BTS64mi8 (x6)	4.00 [4.00;4.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	5	7	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteSystem contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	BNDCL32rm (x6) BNDCL32rr BNDCL64rm (x6) BNDCL64rr BNDCN32rm (x6) BNDCN32rr BNDCN64rm (x6) BNDCN64rr BNDCU32rm (x6) BNDCU32rr BNDCU64rm (x6) BNDCU64rr BNDLDXrm (x6) BNDMK32rm (x6) BNDMK64rm (x6) BNDMOV32mr (x6) BNDMOV32rm (x6) BNDMOV64mr (x6) BNDMOV64rm (x6) BNDMOVrr BNDMOVrr_REV BNDSTXmr (x6) ENDBR32 ENDBR64 RDSSPD (x15) RDSSPQ (x15)	1.00 [1.00;1.00]
8	CATCHPAD CLZERO (x6) EH_RESTORE EH_SjLj_LongJmp32 (x6) EH_SjLj_LongJmp64 (x6) EH_SjLj_SetJmp32 (x6) EH_SjLj_SetJmp64 (x6) Int_eh_sjlj_setup_dispatch MONITOR (x6) MONITORX (x6) VAARG_64 (x6) VASTART_SAVE_XMM_REGS XBEGIN	0.00 [0.00;0.00]
18	LFS16rm (x6) LFS32rm (x6) LFS64rm (x6) LGS16rm (x6) LGS32rm (x6) LGS64rm (x6)	70.01 [70.00;70.01]
4	SGDT16m (x6) SGDT32m (x6) SIDT16m (x6) SIDT32m (x6)	9.00 [9.00;9.00]
3	SLDT16m (x6) SMSW16r SMSW32r SMSW64r	6.00 [6.00;6.00]
17	VERRr VERWr	45.01 [45.01;45.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class LEA32r_LEA64r_LEA64_32r contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	LEA32r (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteBSFLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	BSF16rm (x6) BSF32rm (x6) BSF64rm (x6)	8.00 [8.00;8.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	6	7	PdEX: 5 PdEX01: 2	PdAGLU01: 2.50 PdEX0: 2.25 PdEX1: 2.25

Sched Class VCOMISDrm_VCOMISDrm_Int_VCOMISSrm_VCOMISSrm_Int_VUCOMISDrm_VUCOMISDrm_Int_VUCOMISSrm_VUCOMISSrm_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	VCOMISDrm (x6) VCOMISDrm_Int (x6) VCOMISSrm (x6) VCOMISSrm_Int (x6) VUCOMISDrm (x6) VUCOMISDrm_Int (x6) VUCOMISSrm (x6) VUCOMISSrm_Int (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	6	PdEX: 2 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 1.00 PdEX0: 1.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteMicrocoded contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
8	RELEASE_FADD32mr (x6) RELEASE_FADD64mr (x6)	0.00 [0.00;0.00]
12	REP_MOVSB_32 REP_MOVSB_64 REP_MOVSD_32 REP_MOVSD_64 REP_MOVSQ_32 REP_MOVSQ_64 REP_MOVSW_32 REP_MOVSW_64	3.00 [3.00;3.01]
3	REP_STOSB_32 REP_STOSB_64 REP_STOSD_32 REP_STOSD_64 REP_STOSQ_32 REP_STOSQ_64 REP_STOSW_32 REP_STOSW_64	6.00 [6.00;6.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteBSRLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
4	BSR16rm (x6) BSR32rm (x6) BSR64rm (x6)	9.00 [9.00;9.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	7	8	PdEX: 5 PdEX01: 2	PdAGLU01: 2.50 PdEX0: 2.25 PdEX1: 2.25

Sched Class ROL16m1_ROL16mi_ROL32m1_ROL32mi_ROL64m1_ROL64mi_ROL8m1_ROL8mi_ROR16m1_ROR16mi_ROR32m1_ROR32mi_ROR64m1_ROR64mi_ROR8m1_ROR8mi contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ROL16m1 (x6) ROL16mi (x6) ROL32m1 (x6) ROL32mi (x6) ROL64m1 (x6) ROL64mi (x6) ROL8m1 (x6) ROL8mi (x6) ROR16m1 (x6) ROR16mi (x6) ROR32m1 (x6) ROR32mi (x6) ROR64m1 (x6) ROR64mi (x6) ROR8m1 (x6) ROR8mi (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class XADD16rm_XADD32rm_XADD64rm_XADD8rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	XADD16rm (x14) XADD32rm (x14) XADD64rm (x14) XADD8rm (x18)	4.00 [4.00;4.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class VCVTDQ2PDYrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
10	VCVTDQ2PDYrm (x6)	5.00 [5.00;5.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	18	PdEX: 2 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class ADD_FI16m_ADD_FI32m_SUBR_FI16m_SUBR_FI32m_SUB_FI16m_SUB_FI32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	ADD_FI16m (x6) ADD_FI32m (x6) SUBR_FI16m (x6) SUBR_FI32m (x6) SUB_FI16m (x6) SUB_FI32m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	10	PdEX: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class InvalidSchedClass contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
8	CMOV_F128 CMOV_FR32 CMOV_FR64 CMOV_GR16 CMOV_GR32 CMOV_GR8 CMOV_V16F32 CMOV_V16I1 CMOV_V2F64 CMOV_V2I64 CMOV_V32I1 CMOV_V4F32 CMOV_V4F64 CMOV_V4I64 CMOV_V64I1 CMOV_V8F32 CMOV_V8F64 CMOV_V8I1 CMOV_V8I64 RDPKRU WRPKRU	0.00 [0.00;0.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✕

Sched Class XORPSrr_VXORPSrr_XORPDrr_VXORPDrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	VXORPDrr VXORPSrr XORPDrr (x16) XORPSrr (x16)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class PXORrr_VPXORrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	PXORrr (x16) VPXORrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class PSUBBrr_VPSUBBrr_PSUBDrr_VPSUBDrr_VPSUBQrr_PSUBWrr_VPSUBWrr_PCMPGTBrr_VPCMPGTBrr_PCMPGTDrr_VPCMPGTDrr_PCMPGTWrr_VPCMPGTWrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	PCMPGTBrr (x16) PCMPGTDrr (x16) PCMPGTWrr (x16) VPCMPGTBrr VPCMPGTDrr VPCMPGTWrr	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class PSUBQrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	PSUBQrr (x16)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class FSCALE contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
13	FSCALE	11.01 [11.01;11.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteFHAddLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	HADDPDrm (x16) HADDPSrm (x16) HSUBPDrm (x16) HSUBPSrm (x16) VHADDPDrm (x6) VHADDPSrm (x6) VHSUBPDrm (x6) VHSUBPSrm (x6)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	16	PdEX: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class VCVTPS2PDYrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
10	VCVTPS2PDYrm (x6)	5.00 [5.00;5.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	4	18	PdEX: 2 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class CVTPD2PSrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTPD2PSrm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTDQ2PDrm_VCVTDQ2PDrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTDQ2PDrm (x6) VCVTDQ2PDrm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTSD2SSrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	CVTSD2SSrm (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	9	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MFENCE contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
5	MFENCE	7.00 [7.00;7.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class VCVTSD2SSrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	VCVTSD2SSrm (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	9	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteIMul32ImmLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	IMUL32rmi (x6) IMUL32rmi8 (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdEX: 2 PdEX1: 1 PdMul: 1	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 1.50 PdMul: 1.00

Sched Class CVTSI642SSrr_CVTSI642SSrr_Int_VCVTSI642SSrr_VCVTSI642SSrr_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTSI642SSrr CVTSI642SSrr_Int (x16) VCVTSI642SSrr VCVTSI642SSrr_Int	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class VCVTDQ2PDYrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	VCVTDQ2PDYrr	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	8	PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class VCVTPD2PSYrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	VCVTPD2PSYrr	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	8	PdFPFMA: 1 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class ISTT_FP16m_ISTT_FP32m_ISTT_FP64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	ISTT_FP16m (x6) ISTT_FP32m (x6) ISTT_FP64m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class IST_F16m_IST_F32m_IST_FP16m_IST_FP32m_IST_FP64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	IST_F16m (x6) IST_F32m (x6) IST_FP16m (x6) IST_FP32m (x6) IST_FP64m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class FICOM16m_FICOM32m_FICOMP16m_FICOMP32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	FICOM16m (x6) FICOM32m (x6) FICOMP16m (x6) FICOMP32m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	6	PdEX: 2 PdEX0: 1 PdFPFMA: 1 PdFPU: 1 PdFPU0: 1	PdAGLU01: 1.00 PdEX0: 1.50 PdEX1: 0.50 PdFPFMA: 1.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class WriteLoad contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
8	Int_MemBarrier	0.00 [0.00;0.00]
0	MOV32rm (x6) MOV64rm (x6) MOV8rm (x6) MOV8rm_NOREX (x6) PREFETCH (x6) PREFETCHNTA (x6) PREFETCHT0 (x6) PREFETCHT1 (x6) PREFETCHT2 (x6) PREFETCHW (x6) PREFETCHWT1 (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class LAR16rm_LAR32rm_LAR64rm_LSL16rm_LSL32rm_LSL64rm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
17	LAR16rm (x6) LAR32rm (x6) LAR64rm (x6) LSL16rm (x6) LSL32rm (x6) LSL64rm (x6)	45.01 [45.00;45.02]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	100	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WritePHAddLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	MMX_PHADDDrm (x8) MMX_PHSUBDrm (x8)	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	10	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPD2PIirr_MMX_CVTTPD2PIirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MMX_CVTPD2PIirr MMX_CVTTPD2PIirr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class LD_F32m_LD_F64m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
9	LD_F32m (x6) LD_F64m (x6)	22.01 [22.00;22.01]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class LD_F80m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
2	LD_F80m (x6)	8.00 [8.00;8.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25

Sched Class CVTPD2DQrm_CVTTPD2DQrm_MMX_CVTPD2PIirm_MMX_CVTTPD2PIirm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MMX_CVTPD2PIirm (x6) MMX_CVTTPD2PIirm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPI2PDirm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MMX_CVTPI2PDirm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPI2PDirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MMX_CVTPI2PDirr	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	8	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_CVTPI2PSirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MMX_CVTPI2PSirr (x16)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	4	PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class VCVTPD2DQYrr_VCVTTPD2DQYrr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
6	VCVTPD2DQYrr VCVTTPD2DQYrr	4.00 [4.00;4.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	3	8	PdFPFMA: 1 PdFPSTO: 1 PdFPU: 2 PdFPU1: 2	PdFPFMA: 1.00 PdFPSTO: 1.00 PdFPU0: 0.50 PdFPU1: 2.50 PdFPU2: 0.50 PdFPU3: 0.50

Sched Class MMX_PXORirr_MMX_PANDNirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	MMX_PANDNirr (x8) MMX_PXORirr (x8)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class MMX_PCMPGTBirr_MMX_PCMPGTDirr_MMX_PCMPGTWirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	MMX_PCMPGTBirr (x8) MMX_PCMPGTDirr (x8) MMX_PCMPGTWirr (x8)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class WriteVecInsertLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	MMX_PINSRWrm (x8) PINSRBrm (x16) PINSRDrm (x16) PINSRQrm (x16) PINSRWrm (x16) VPINSRBrm (x6) VPINSRDrm (x6) VPINSRQrm (x6) VPINSRWrm (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 1 PdFPMAL: 1 PdFPU: 1 PdFPU01: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMAL: 1.00 PdFPU0: 0.75 PdFPU1: 0.75 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTPD2DQrm_CVTTPD2DQrm contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CVTPD2DQrm (x6) CVTTPD2DQrm (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	13	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class CVTSD2SSrm_Int_VCVTSD2SSrm_Int contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	CVTSD2SSrm_Int (x16) VCVTSD2SSrm_Int (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	9	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class MMX_PSUBBirr_MMX_PSUBDirr_MMX_PSUBWirr_MMX_PCMPGTBirr_MMX_PCMPGTDirr_MMX_PCMPGTWirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	MMX_PSUBBirr (x8) MMX_PSUBDirr (x8) MMX_PSUBWirr (x8)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class MMX_PADDQirr_MMX_PSUBQirr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	MMX_PSUBQirr (x8)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✔	16382

Sched Class FNSTSW16r contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
12	FNSTSW16r	3.00 [3.00;3.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	1	PdEX: 1 PdEX01: 1	PdAGLU01: 0.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteFStore contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MOVHPDmr (x6) MOVHPSmr (x6) VMOVHPDmr (x6) VMOVHPSmr (x6)	2.00 [2.00;2.00]
0	MOVLPDmr (x6) MOVLPSmr (x6) MOVSDmr (x6) MOVSSmr (x6) VMOVLPDmr (x6) VMOVLPSmr (x6) VMOVSDmr (x6) VMOVSSmr (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	2	PdEX: 1 PdFPSTO: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPSTO: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class ADC16mi_ADC16mi8_ADC32mi_ADC32mi8_ADC64mi32_ADC64mi8_ADC8mi_ADC8mi8_SBB16mi_SBB16mi8_SBB32mi_SBB32mi8_SBB64mi32_SBB64mi8_SBB8mi_SBB8mi8 contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	ADC16mi (x6) ADC16mi8 (x6) ADC32mi (x6) ADC32mi8 (x6) ADC64mi32 (x6) ADC64mi8 (x6) ADC8mi (x6) SBB16mi (x6) SBB16mi8 (x6) SBB32mi (x6) SBB32mi8 (x6) SBB64mi32 (x6) SBB64mi8 (x6) SBB8mi (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 4	PdAGLU01: 2.00 PdEX0: 1.00 PdEX1: 1.00

Sched Class WriteMPSADLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
4	MPSADBWrmi (x16)	9.00 [9.00;9.00]
7	VMPSADBWrmi (x6)	10.00 [10.00;10.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	9	13	PdEX: 1 PdFPMMA: 2 PdFPU: 1 PdFPU0: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPMMA: 2.00 PdFPU0: 1.25 PdFPU1: 0.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class AND16mi_AND16mi8_AND16mr_AND32mi_AND32mi8_AND32mr_AND64mi32_AND64mi8_AND64mr_AND8mi_AND8mi8_AND8mr_OR16mi_OR16mi8_OR16mr_OR32mi_OR32mi8_OR32mr_OR64mi32_OR64mi8_OR64mr_OR8mi_OR8mi8_OR8mr_XOR16mi_XOR16mi8_XOR16mr_XOR32mi_XOR32mi8_XOR32mr_XOR64mi32_XOR64mi8_XOR64mr_XOR8mi_XOR8mi8_XOR8mr contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	AND16mi (x6) AND16mi8 (x6) AND16mr (x6) AND32mi (x6) AND32mi8 (x6) AND32mr (x6) AND64mi32 (x6) AND64mi8 (x6) AND64mr (x6) AND8mi (x6) AND8mr (x6) OR16mi (x6) OR16mi8 (x6) OR16mr (x6) OR32mi (x6) OR32mi8 (x6) OR32mr (x6) OR64mi32 (x6) OR64mi8 (x6) OR64mr (x6) OR8mi (x6) OR8mr (x6) XOR16mi (x6) XOR16mi8 (x6) XOR16mr (x6) XOR32mi (x6) XOR32mi8 (x6) XOR32mr (x6) XOR64mi32 (x6) XOR64mi8 (x6) XOR64mr (x6) XOR8mi (x6) XOR8mr (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	6	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

Sched Class WriteCMOV2Ld_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	CMOVA16rm (x14) CMOVA32rm (x14) CMOVA64rm (x14) CMOVBE16rm (x14) CMOVBE32rm (x14) CMOVBE64rm (x14)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50

Sched Class WriteCMOVLd_ReadAfterLd contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	CMOVAE16rm (x14) CMOVAE32rm (x14) CMOVAE64rm (x14) CMOVB16rm (x14) CMOVB32rm (x14) CMOVB64rm (x14) CMOVE16rm (x14) CMOVE32rm (x14) CMOVE64rm (x14) CMOVNE16rm (x14) CMOVNE32rm (x14) CMOVNE64rm (x14) CMOVNO16rm (x14) CMOVNO32rm (x14) CMOVNO64rm (x14) CMOVNP16rm (x14) CMOVNP32rm (x14) CMOVNP64rm (x14) CMOVNS16rm (x14) CMOVNS32rm (x14) CMOVNS64rm (x14) CMOVO16rm (x14) CMOVO32rm (x14) CMOVO64rm (x14) CMOVP16rm (x14) CMOVP32rm (x14) CMOVP64rm (x14) CMOVS16rm (x14) CMOVS32rm (x14) CMOVS64rm (x14)	1.00 [1.00;1.00]
1	CMOVG16rm (x14) CMOVG32rm (x14) CMOVG64rm (x14) CMOVGE16rm (x14) CMOVGE32rm (x14) CMOVGE64rm (x14) CMOVL16rm (x14) CMOVL32rm (x14) CMOVL64rm (x14) CMOVLE16rm (x14) CMOVLE32rm (x14) CMOVLE64rm (x14)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	5	PdEX: 2	PdAGLU01: 1.00 PdEX0: 0.50 PdEX1: 0.50

Sched Class MUL_FI16m_MUL_FI32m contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
1	MUL_FI16m (x6) MUL_FI32m (x6)	2.00 [2.00;2.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	1	10	PdEX: 1 PdFPFMA: 1 PdFPU: 1 PdFPU1: 1	PdAGLU01: 0.50 PdEX0: 0.25 PdEX1: 0.25 PdFPFMA: 1.00 PdFPU0: 0.25 PdFPU1: 1.25 PdFPU2: 0.25 PdFPU3: 0.25

Sched Class OR32mrLocked contains instructions whose performance characteristics do not match that of LLVM:

ClusterId	Opcode/Config	NumMicroOps
0	OR32mrLocked (x6)	1.00 [1.00;1.00]

llvm SchedModel data:

Valid	Variant	NumMicroOps	Latency	WriteProcRes	Idealized Resource Pressure
✔	✕	2	5 (WriteResourceID 0) 1 (WriteResourceID 0)	PdEX: 3	PdAGLU01: 1.50 PdEX0: 0.75 PdEX1: 0.75

llvm-exegesis Analysis Results

Triple: x86_64-unknown-linux-gnu

Cpu: bdver2