INSTCOMBINE ITERATION #1 on fold_lshr
IC: ADD:   ret i8 %v8
IC: ADD:   %v8 = add nuw nsw i8 %v7, %v6
IC: ADD:   %v7 = and i8 %v4, 61
IC: ADD:   %v6 = and i8 %v5, 91
IC: ADD:   %v5 = sub nsw i8 0, %v2
IC: ADD:   %v4 = ashr exact i8 %v3, 63
IC: ADD:   %v3 = shl nuw i8 %v0, 57
IC: ADD:   %v2 = xor i8 %v1, 1
IC: ADD:   %v1 = lshr exact i8 %v0, 6
IC: ADD:   %v0 = select i1 %arg, i8 64, i8 0
IC: Visiting:   %v0 = select i1 %arg, i8 64, i8 0
IC: Visiting:   %v1 = lshr exact i8 %v0, 6
ICE: GetShiftedValue propagating shift through expression to eliminate shift:
  IN:   %v0 = select i1 %arg, i8 64, i8 0
  SH:   %v1 = lshr exact i8 %v0, 6
IC: ADD:   %v0 = select i1 %arg, i8 64, i8 0
IC: Replacing   %v1 = lshr exact i8 %v0, 6
    with   %v0 = select i1 %arg, i8 1, i8 0
IC: Mod =   %v1 = lshr exact i8 %v0, 6
    New =   %v1 = lshr exact i8 %v0, 6
IC: ERASE   %v1 = lshr exact i8 %v0, 6
IC: ADD DEFERRED:   %v0 = select i1 %arg, i8 1, i8 0
IC: Visiting:   %v0 = select i1 %arg, i8 1, i8 0
IC: Old =   %v0 = select i1 %arg, i8 1, i8 0
    New =   <badref> = zext i1 %arg to i8
IC: ADD:   %v0 = zext i1 %arg to i8
IC: ERASE   %0 = select i1 %arg, i8 1, i8 0
IC: Visiting:   %v0 = zext i1 %arg to i8
IC: Visiting:   %v2 = xor i8 %v0, 1
IC: Visiting:   %v3 = shl nuw i8 %v0, 57
IC: Replacing   %v3 = shl nuw i8 %v0, 57
    with i8 undef
IC: Mod =   %v3 = shl nuw i8 %v0, 57
    New =   %v3 = shl nuw i8 %v0, 57
IC: ERASE   %v3 = shl nuw i8 %v0, 57
IC: ADD DEFERRED:   %v0 = zext i1 %arg to i8
IC: ADD:   %v0 = zext i1 %arg to i8
IC: Visiting:   %v0 = zext i1 %arg to i8
IC: ConstFold to: i8 0 from:   %v4 = ashr exact i8 undef, 63
IC: Replacing   %v4 = ashr exact i8 undef, 63
    with i8 0
IC: ERASE   %v4 = ashr exact i8 undef, 63
IC: Visiting:   %v5 = sub nsw i8 0, %v2
Negator: attempting to sink negation into   %v2 = xor i8 %v0, 1
Negator: successfully sunk negation into   %v2 = xor i8 %v0, 1
         NEW:   %v2.neg = add i8 %0, 1
Negator: Propagating 2 instrs to InstCombine
IC: ADD DEFERRED:   %0 = xor i8 %v0, -2
IC: ADD DEFERRED:   %v2.neg = add i8 %0, 1
IC: Old =   %v5 = sub nsw i8 0, %v2
    New =   <badref> = add i8 %v2.neg, 0
IC: ADD:   %v5 = add i8 %v2.neg, 0
IC: ERASE   %1 = sub nsw i8 0, %v2
IC: ADD DEFERRED:   %v2 = xor i8 %v0, 1
IC: ERASE   %v2 = xor i8 %v0, 1
IC: ADD DEFERRED:   %v0 = zext i1 %arg to i8
IC: ADD:   %v0 = zext i1 %arg to i8
IC: ADD:   %v2.neg = add i8 %0, 1
IC: ADD:   %0 = xor i8 %v0, -2
IC: Visiting:   %0 = xor i8 %v0, -2
IC: ADD DEFERRED:   %0 = or i8 %v0, -2
IC: Replacing   %1 = xor i8 %v0, -2
    with   %0 = or i8 %v0, -2
IC: Mod =   %0 = xor i8 %v0, -2
    New =   %1 = xor i8 %v0, -2
IC: ERASE   %1 = xor i8 %v0, -2
IC: ADD DEFERRED:   %v0 = zext i1 %arg to i8
IC: ADD:   %0 = or i8 %v0, -2
IC: Visiting:   %0 = or i8 %v0, -2
IC: Visiting:   %v2.neg = add i8 %0, 1
IC: Mod =   %v2.neg = add i8 %0, 1
    New =   %v2.neg = add nsw i8 %0, 1
IC: ADD:   %v2.neg = add nsw i8 %0, 1
IC: Visiting:   %v2.neg = add nsw i8 %0, 1
IC: Visiting:   %v0 = zext i1 %arg to i8
IC: Visiting:   %v5 = add i8 %v2.neg, 0
IC: Replacing   %v5 = add i8 %v2.neg, 0
    with   %v2.neg = add nsw i8 %0, 1
IC: Mod =   %v5 = add i8 %v2.neg, 0
    New =   %v5 = add i8 %v2.neg, 0
IC: ERASE   %v5 = add i8 %v2.neg, 0
IC: ADD DEFERRED:   %v2.neg = add nsw i8 %0, 1
IC: ADD:   %v2.neg = add nsw i8 %0, 1
IC: Visiting:   %v2.neg = add nsw i8 %0, 1
IC: Visiting:   %v6 = and i8 %v2.neg, 91
IC: ADD DEFERRED:   %0 = or i8 %v0, 126
IC: ADD DEFERRED:   %v2.neg = add i8 %0, 1
IC: Mod =   %v6 = and i8 %v2.neg, 91
    New =   %v6 = and i8 %v2.neg, 91
IC: ADD:   %v6 = and i8 %v2.neg, 91
IC: ADD:   %v2.neg = add i8 %0, 1
IC: ADD:   %0 = or i8 %v0, 126
IC: Visiting:   %0 = or i8 %v0, 126
IC: Visiting:   %v2.neg = add i8 %0, 1
IC: Mod =   %v2.neg = add i8 %0, 1
    New =   %v2.neg = add nuw i8 %0, 1
IC: ADD:   %v2.neg = add nuw i8 %0, 1
IC: Visiting:   %v2.neg = add nuw i8 %0, 1
IC: Visiting:   %v6 = and i8 %v2.neg, 91
IC: ConstFold to: i8 0 from:   %v7 = and i8 0, 61
IC: Replacing   %v7 = and i8 0, 61
    with i8 0
IC: ERASE   %v7 = and i8 0, 61
IC: Visiting:   %v8 = add nuw nsw i8 0, %v6
IC: Replacing   %v8 = add nuw nsw i8 0, %v6
    with   %v6 = and i8 %v2.neg, 91
IC: Mod =   %v8 = add nuw nsw i8 0, %v6
    New =   %v8 = add nuw nsw i8 0, %v6
IC: ERASE   %v8 = add nuw nsw i8 0, %v6
IC: ADD DEFERRED:   %v6 = and i8 %v2.neg, 91
IC: ADD:   %v6 = and i8 %v2.neg, 91
IC: Visiting:   %v6 = and i8 %v2.neg, 91
IC: Visiting:   ret i8 %v6


INSTCOMBINE ITERATION #2 on fold_lshr
IC: ADD:   ret i8 %v6
IC: ADD:   %v6 = and i8 %v2.neg, 91
IC: ADD:   %v2.neg = add nuw i8 %0, 1
IC: ADD:   %0 = or i8 %v0, 126
IC: ADD:   %v0 = zext i1 %arg to i8
IC: Visiting:   %v0 = zext i1 %arg to i8
IC: Visiting:   %0 = or i8 %v0, 126
IC: Visiting:   %v2.neg = add nuw i8 %0, 1
IC: Visiting:   %v6 = and i8 %v2.neg, 91
IC: Visiting:   ret i8 %v6
*** IR Dump After Combine redundant instructions ***
define i8 @fold_lshr(i1 %arg) {
entry:
  %v0 = zext i1 %arg to i8
  %0 = or i8 %v0, 126
  %v2.neg = add nuw i8 %0, 1
  %v6 = and i8 %v2.neg, 91
  ret i8 %v6
}
*** IR Dump After Module Verifier ***
define i8 @fold_lshr(i1 %arg) {
entry:
  %v0 = zext i1 %arg to i8
  %0 = or i8 %v0, 126
  %v2.neg = add nuw i8 %0, 1
  %v6 = and i8 %v2.neg, 91
  ret i8 %v6
}
; ModuleID = 'lshr-select-const-i8.ll'
source_filename = "lshr-select-const-i8.ll"

define i8 @fold_lshr(i1 %arg) {
entry:
  %v0 = zext i1 %arg to i8
  %0 = or i8 %v0, 126
  %v2.neg = add nuw i8 %0, 1
  %v6 = and i8 %v2.neg, 91
  ret i8 %v6
}