diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index 66ca5faf82fb..af936e6fc96b 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -1,798 +1,798 @@
 //===----------------------- MipsBranchExpansion.cpp ----------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 /// \file
 ///
 /// This pass do two things:
 /// - it expands a branch or jump instruction into a long branch if its offset
 ///   is too large to fit into its immediate field,
 /// - it inserts nops to prevent forbidden slot hazards.
 ///
 /// The reason why this pass combines these two tasks is that one of these two
 /// tasks can break the result of the previous one.
 ///
 /// Example of that is a situation where at first, no branch should be expanded,
 /// but after adding at least one nop somewhere in the code to prevent a
 /// forbidden slot hazard, offset of some branches may go out of range. In that
 /// case it is necessary to check again if there is some branch that needs
 /// expansion. On the other hand, expanding some branch may cause a control
 /// transfer instruction to appear in the forbidden slot, which is a hazard that
 /// should be fixed. This pass alternates between this two tasks untill no
 /// changes are made. Only then we can be sure that all branches are expanded
 /// properly, and no hazard situations exist.
 ///
 /// Regarding branch expanding:
 ///
 /// When branch instruction like beqzc or bnezc has offset that is too large
 /// to fit into its immediate field, it has to be expanded to another
 /// instruction or series of instructions.
 ///
 /// FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
 /// TODO: Handle out of range bc, b (pseudo) instructions.
 ///
 /// Regarding compact branch hazard prevention:
 ///
 /// Hazards handled: forbidden slots for MIPSR6.
 ///
 /// A forbidden slot hazard occurs when a compact branch instruction is executed
 /// and the adjacent instruction in memory is a control transfer instruction
 /// such as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE.
 ///
 /// For example:
 ///
 /// 0x8004      bnec    a1,v0,<P+0x18>
 /// 0x8008      beqc    a1,a2,<P+0x54>
 ///
 /// In such cases, the processor is required to signal a Reserved Instruction
 /// exception.
 ///
 /// Here, if the instruction at 0x8004 is executed, the processor will raise an
 /// exception as there is a control transfer instruction at 0x8008.
 ///
 /// There are two sources of forbidden slot hazards:
 ///
 /// A) A previous pass has created a compact branch directly.
 /// B) Transforming a delay slot branch into compact branch. This case can be
 ///    difficult to process as lookahead for hazards is insufficient, as
 ///    backwards delay slot fillling can also produce hazards in previously
 ///    processed instuctions.
 ///
 /// In future this pass can be extended (or new pass can be created) to handle
 /// other pipeline hazards, such as various MIPS1 hazards, processor errata that
 /// require instruction reorganization, etc.
 ///
 /// This pass has to run after the delay slot filler as that pass can introduce
 /// pipeline hazards such as compact branch hazard, hence the existing hazard
 /// recognizer is not suitable.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "MCTargetDesc/MipsMCNaCl.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
 #include "Mips.h"
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
 #include "MipsTargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetMachine.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "mips-branch-expansion"
 
 STATISTIC(NumInsertedNops, "Number of nops inserted");
 STATISTIC(LongBranches, "Number of long branches.");
 
 static cl::opt<bool>
     SkipLongBranch("skip-mips-long-branch", cl::init(false),
                    cl::desc("MIPS: Skip branch expansion pass."), cl::Hidden);
 
 static cl::opt<bool>
     ForceLongBranch("force-mips-long-branch", cl::init(false),
                     cl::desc("MIPS: Expand all branches to long format."),
                     cl::Hidden);
 
 namespace {
 
 using Iter = MachineBasicBlock::iterator;
 using ReverseIter = MachineBasicBlock::reverse_iterator;
 
 struct MBBInfo {
   uint64_t Size = 0;
   bool HasLongBranch = false;
   MachineInstr *Br = nullptr;
   MBBInfo() = default;
 };
 
 class MipsBranchExpansion : public MachineFunctionPass {
 public:
   static char ID;
 
   MipsBranchExpansion() : MachineFunctionPass(ID), ABI(MipsABIInfo::Unknown()) {
     initializeMipsBranchExpansionPass(*PassRegistry::getPassRegistry());
   }
 
   StringRef getPassName() const override {
     return "Mips Branch Expansion Pass";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
   }
 
 private:
   void splitMBB(MachineBasicBlock *MBB);
   void initMBBInfo();
   int64_t computeOffset(const MachineInstr *Br);
   void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
                      MachineBasicBlock *MBBOpnd);
   void expandToLongBranch(MBBInfo &Info);
   bool handleForbiddenSlot();
   bool handlePossibleLongBranch();
 
   const MipsSubtarget *STI;
   const MipsInstrInfo *TII;
 
   MachineFunction *MFp;
   SmallVector<MBBInfo, 16> MBBInfos;
   bool IsPIC;
   MipsABIInfo ABI;
   unsigned LongBranchSeqSize;
   bool ForceLongBranchFirstPass = false;
 };
 
 } // end of anonymous namespace
 
 char MipsBranchExpansion::ID = 0;
 
 INITIALIZE_PASS(MipsBranchExpansion, DEBUG_TYPE,
                 "Expand out of range branch instructions and prevent forbidden"
                 " slot hazards",
                 false, false)
 
 /// Returns a pass that clears pipeline hazards.
 FunctionPass *llvm::createMipsBranchExpansion() {
   return new MipsBranchExpansion();
 }
 
 // Find the next real instruction from the current position in current basic
 // block.
 static Iter getNextMachineInstrInBB(Iter Position) {
   Iter I = Position, E = Position->getParent()->end();
   I = std::find_if_not(I, E,
                        [](const Iter &Insn) { return Insn->isTransient(); });
 
   return I;
 }
 
 // Find the next real instruction from the current position, looking through
 // basic block boundaries.
 static std::pair<Iter, bool> getNextMachineInstr(Iter Position,
                                                  MachineBasicBlock *Parent) {
   if (Position == Parent->end()) {
     do {
       MachineBasicBlock *Succ = Parent->getNextNode();
       if (Succ != nullptr && Parent->isSuccessor(Succ)) {
         Position = Succ->begin();
         Parent = Succ;
       } else {
         return std::make_pair(Position, true);
       }
     } while (Parent->empty());
   }
 
   Iter Instr = getNextMachineInstrInBB(Position);
   if (Instr == Parent->end()) {
     return getNextMachineInstr(Instr, Parent);
   }
   return std::make_pair(Instr, false);
 }
 
 /// Iterate over list of Br's operands and search for a MachineBasicBlock
 /// operand.
 static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
   for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
     const MachineOperand &MO = Br.getOperand(I);
 
     if (MO.isMBB())
       return MO.getMBB();
   }
 
   llvm_unreachable("This instruction does not have an MBB operand.");
 }
 
 // Traverse the list of instructions backwards until a non-debug instruction is
 // found or it reaches E.
 static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
   for (; B != E; ++B)
     if (!B->isDebugInstr())
       return B;
 
   return E;
 }
 
 // Split MBB if it has two direct jumps/branches.
 void MipsBranchExpansion::splitMBB(MachineBasicBlock *MBB) {
   ReverseIter End = MBB->rend();
   ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
 
   // Return if MBB has no branch instructions.
   if ((LastBr == End) ||
       (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
     return;
 
   ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
 
   // MBB has only one branch instruction if FirstBr is not a branch
   // instruction.
   if ((FirstBr == End) ||
       (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
     return;
 
   assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
 
   // Create a new MBB. Move instructions in MBB to the newly created MBB.
   MachineBasicBlock *NewMBB =
       MFp->CreateMachineBasicBlock(MBB->getBasicBlock());
 
   // Insert NewMBB and fix control flow.
   MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
   NewMBB->transferSuccessors(MBB);
   NewMBB->removeSuccessor(Tgt, true);
   MBB->addSuccessor(NewMBB);
   MBB->addSuccessor(Tgt);
   MFp->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
 
   NewMBB->splice(NewMBB->end(), MBB, LastBr.getReverse(), MBB->end());
 }
 
 // Fill MBBInfos.
 void MipsBranchExpansion::initMBBInfo() {
   // Split the MBBs if they have two branches. Each basic block should have at
   // most one branch after this loop is executed.
   for (auto &MBB : *MFp)
     splitMBB(&MBB);
 
   MFp->RenumberBlocks();
   MBBInfos.clear();
   MBBInfos.resize(MFp->size());
 
   for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
     MachineBasicBlock *MBB = MFp->getBlockNumbered(I);
 
     // Compute size of MBB.
     for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
          MI != MBB->instr_end(); ++MI)
       MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
 
     // Search for MBB's branch instruction.
     ReverseIter End = MBB->rend();
     ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
 
     if ((Br != End) && !Br->isIndirectBranch() &&
         (Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC)))
       MBBInfos[I].Br = &*Br;
   }
 }
 
 // Compute offset of branch in number of bytes.
 int64_t MipsBranchExpansion::computeOffset(const MachineInstr *Br) {
   int64_t Offset = 0;
   int ThisMBB = Br->getParent()->getNumber();
   int TargetMBB = getTargetMBB(*Br)->getNumber();
 
   // Compute offset of a forward branch.
   if (ThisMBB < TargetMBB) {
     for (int N = ThisMBB + 1; N < TargetMBB; ++N)
       Offset += MBBInfos[N].Size;
 
     return Offset + 4;
   }
 
   // Compute offset of a backward branch.
   for (int N = ThisMBB; N >= TargetMBB; --N)
     Offset += MBBInfos[N].Size;
 
   return -Offset + 4;
 }
 
 // Replace Br with a branch which has the opposite condition code and a
 // MachineBasicBlock operand MBBOpnd.
 void MipsBranchExpansion::replaceBranch(MachineBasicBlock &MBB, Iter Br,
                                         const DebugLoc &DL,
                                         MachineBasicBlock *MBBOpnd) {
   unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
   const MCInstrDesc &NewDesc = TII->get(NewOpc);
 
   MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
 
   for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
     MachineOperand &MO = Br->getOperand(I);
 
     if (!MO.isReg()) {
       assert(MO.isMBB() && "MBB operand expected.");
       break;
     }
 
     MIB.addReg(MO.getReg());
   }
 
   MIB.addMBB(MBBOpnd);
 
   if (Br->hasDelaySlot()) {
     // Bundle the instruction in the delay slot to the newly created branch
     // and erase the original branch.
     assert(Br->isBundledWithSucc());
     MachineBasicBlock::instr_iterator II = Br.getInstrIterator();
     MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
   }
   Br->eraseFromParent();
 }
 
 // Expand branch instructions to long branches.
 // TODO: This function has to be fixed for beqz16 and bnez16, because it
 // currently assumes that all branches have 16-bit offsets, and will produce
 // wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
 // are present.
 void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
   MachineBasicBlock::iterator Pos;
   MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
   DebugLoc DL = I.Br->getDebugLoc();
   const BasicBlock *BB = MBB->getBasicBlock();
   MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
   MachineBasicBlock *LongBrMBB = MFp->CreateMachineBasicBlock(BB);
 
   MFp->insert(FallThroughMBB, LongBrMBB);
   MBB->replaceSuccessor(TgtMBB, LongBrMBB);
 
   if (IsPIC) {
     MachineBasicBlock *BalTgtMBB = MFp->CreateMachineBasicBlock(BB);
     MFp->insert(FallThroughMBB, BalTgtMBB);
     LongBrMBB->addSuccessor(BalTgtMBB);
     BalTgtMBB->addSuccessor(TgtMBB);
 
     // We must select between the MIPS32r6/MIPS64r6 BALC (which is a normal
     // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
     // pseudo-instruction wrapping BGEZAL).
     const unsigned BalOp =
         STI->hasMips32r6()
             ? STI->inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC
             : STI->inMicroMipsMode() ? Mips::BAL_BR_MM : Mips::BAL_BR;
 
     if (!ABI.IsN64()) {
       // Pre R6:
       // $longbr:
       //  addiu $sp, $sp, -8
       //  sw $ra, 0($sp)
       //  lui $at, %hi($tgt - $baltgt)
       //  bal $baltgt
       //  addiu $at, $at, %lo($tgt - $baltgt)
       // $baltgt:
       //  addu $at, $ra, $at
       //  lw $ra, 0($sp)
       //  jr $at
       //  addiu $sp, $sp, 8
       // $fallthrough:
       //
 
       // R6:
       // $longbr:
       //  addiu $sp, $sp, -8
       //  sw $ra, 0($sp)
       //  lui $at, %hi($tgt - $baltgt)
       //  addiu $at, $at, %lo($tgt - $baltgt)
       //  balc $baltgt
       // $baltgt:
       //  addu $at, $ra, $at
       //  lw $ra, 0($sp)
       //  addiu $sp, $sp, 8
       //  jic $at, 0
       // $fallthrough:
 
       Pos = LongBrMBB->begin();
 
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
           .addReg(Mips::SP)
           .addImm(-8);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
           .addReg(Mips::RA)
           .addReg(Mips::SP)
           .addImm(0);
 
       // LUi and ADDiu instructions create 32-bit offset of the target basic
       // block from the target of BAL(C) instruction.  We cannot use immediate
       // value for this offset because it cannot be determined accurately when
       // the program has inline assembly statements.  We therefore use the
       // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
       // are resolved during the fixup, so the values will always be correct.
       //
       // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
       // expressions at this point (it is possible only at the MC layer),
       // we replace LUi and ADDiu with pseudo instructions
       // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
       // blocks as operands to these instructions.  When lowering these pseudo
       // instructions to LUi and ADDiu in the MC layer, we will create
       // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
       // operands to lowered instructions.
 
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
-          .addMBB(TgtMBB)
+          .addMBB(TgtMBB, MipsII::MO_ABS_HI)
           .addMBB(BalTgtMBB);
 
       MachineInstrBuilder BalInstr =
           BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
       MachineInstrBuilder ADDiuInstr =
           BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
               .addReg(Mips::AT)
-              .addMBB(TgtMBB)
+              .addMBB(TgtMBB, MipsII::MO_ABS_LO)
               .addMBB(BalTgtMBB);
       if (STI->hasMips32r6()) {
         LongBrMBB->insert(Pos, ADDiuInstr);
         LongBrMBB->insert(Pos, BalInstr);
       } else {
         LongBrMBB->insert(Pos, BalInstr);
         LongBrMBB->insert(Pos, ADDiuInstr);
         LongBrMBB->rbegin()->bundleWithPred();
       }
 
       Pos = BalTgtMBB->begin();
 
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
           .addReg(Mips::RA)
           .addReg(Mips::AT);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
           .addReg(Mips::SP)
           .addImm(0);
       if (STI->isTargetNaCl())
         // Bundle-align the target of indirect branch JR.
         TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
 
       // In NaCl, modifying the sp is not allowed in branch delay slot.
       // For MIPS32R6, we can skip using a delay slot branch.
       if (STI->isTargetNaCl() ||
           (STI->hasMips32r6() && !STI->useIndirectJumpsHazard()))
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
             .addReg(Mips::SP)
             .addImm(8);
 
       if (STI->hasMips32r6() && !STI->useIndirectJumpsHazard()) {
         const unsigned JICOp =
             STI->inMicroMipsMode() ? Mips::JIC_MMR6 : Mips::JIC;
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(JICOp))
             .addReg(Mips::AT)
             .addImm(0);
 
       } else {
         unsigned JROp =
             STI->useIndirectJumpsHazard()
                 ? (STI->hasMips32r6() ? Mips::JR_HB_R6 : Mips::JR_HB)
                 : Mips::JR;
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT);
 
         if (STI->isTargetNaCl()) {
           BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
         } else
           BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
               .addReg(Mips::SP)
               .addImm(8);
 
         BalTgtMBB->rbegin()->bundleWithPred();
       }
     } else {
       // Pre R6:
       // $longbr:
       //  daddiu $sp, $sp, -16
       //  sd $ra, 0($sp)
       //  daddiu $at, $zero, %hi($tgt - $baltgt)
       //  dsll $at, $at, 16
       //  bal $baltgt
       //  daddiu $at, $at, %lo($tgt - $baltgt)
       // $baltgt:
       //  daddu $at, $ra, $at
       //  ld $ra, 0($sp)
       //  jr64 $at
       //  daddiu $sp, $sp, 16
       // $fallthrough:
 
       // R6:
       // $longbr:
       //  daddiu $sp, $sp, -16
       //  sd $ra, 0($sp)
       //  daddiu $at, $zero, %hi($tgt - $baltgt)
       //  dsll $at, $at, 16
       //  daddiu $at, $at, %lo($tgt - $baltgt)
       //  balc $baltgt
       // $baltgt:
       //  daddu $at, $ra, $at
       //  ld $ra, 0($sp)
       //  daddiu $sp, $sp, 16
       //  jic $at, 0
       // $fallthrough:
 
       // We assume the branch is within-function, and that offset is within
       // +/- 2GB.  High 32 bits will therefore always be zero.
 
       // Note that this will work even if the offset is negative, because
       // of the +1 modification that's added in that case.  For example, if the
       // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
       //
       // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
       //
       // and the bits [47:32] are zero.  For %highest
       //
       // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
       //
       // and the bits [63:48] are zero.
 
       Pos = LongBrMBB->begin();
 
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
           .addReg(Mips::SP_64)
           .addImm(-16);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD))
           .addReg(Mips::RA_64)
           .addReg(Mips::SP_64)
           .addImm(0);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
               Mips::AT_64)
           .addReg(Mips::ZERO_64)
           .addMBB(TgtMBB, MipsII::MO_ABS_HI)
           .addMBB(BalTgtMBB);
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
           .addReg(Mips::AT_64)
           .addImm(16);
 
       MachineInstrBuilder BalInstr =
           BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
       MachineInstrBuilder DADDiuInstr =
           BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
               .addReg(Mips::AT_64)
               .addMBB(TgtMBB, MipsII::MO_ABS_LO)
               .addMBB(BalTgtMBB);
       if (STI->hasMips32r6()) {
         LongBrMBB->insert(Pos, DADDiuInstr);
         LongBrMBB->insert(Pos, BalInstr);
       } else {
         LongBrMBB->insert(Pos, BalInstr);
         LongBrMBB->insert(Pos, DADDiuInstr);
         LongBrMBB->rbegin()->bundleWithPred();
       }
 
       Pos = BalTgtMBB->begin();
 
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
           .addReg(Mips::RA_64)
           .addReg(Mips::AT_64);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
           .addReg(Mips::SP_64)
           .addImm(0);
 
       if (STI->hasMips64r6() && !STI->useIndirectJumpsHazard()) {
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
             .addReg(Mips::SP_64)
             .addImm(16);
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JIC64))
             .addReg(Mips::AT_64)
             .addImm(0);
       } else {
         unsigned JROp =
             STI->useIndirectJumpsHazard()
                 ? (STI->hasMips32r6() ? Mips::JR_HB64_R6 : Mips::JR_HB64)
                 : Mips::JR64;
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT_64);
         BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
             .addReg(Mips::SP_64)
             .addImm(16);
         BalTgtMBB->rbegin()->bundleWithPred();
       }
     }
 
     assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
   } else {
     // Pre R6:                  R6:
     // $longbr:                 $longbr:
     //  j $tgt                   bc $tgt
     //  nop                     $fallthrough
     // $fallthrough:
     //
     Pos = LongBrMBB->begin();
     LongBrMBB->addSuccessor(TgtMBB);
     if (STI->hasMips32r6())
       BuildMI(*LongBrMBB, Pos, DL,
               TII->get(STI->inMicroMipsMode() ? Mips::BC_MMR6 : Mips::BC))
           .addMBB(TgtMBB);
     else
       MIBundleBuilder(*LongBrMBB, Pos)
           .append(BuildMI(*MFp, DL, TII->get(Mips::J)).addMBB(TgtMBB))
           .append(BuildMI(*MFp, DL, TII->get(Mips::NOP)));
 
     assert(LongBrMBB->size() == LongBranchSeqSize);
   }
 
   if (I.Br->isUnconditionalBranch()) {
     // Change branch destination.
     assert(I.Br->getDesc().getNumOperands() == 1);
     I.Br->RemoveOperand(0);
     I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
   } else
     // Change branch destination and reverse condition.
     replaceBranch(*MBB, I.Br, DL, &*FallThroughMBB);
 }
 
 static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
   MachineBasicBlock &MBB = F.front();
   MachineBasicBlock::iterator I = MBB.begin();
   DebugLoc DL = MBB.findDebugLoc(MBB.begin());
   BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
       .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
   BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
       .addReg(Mips::V0)
       .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
   MBB.removeLiveIn(Mips::V0);
 }
 
 bool MipsBranchExpansion::handleForbiddenSlot() {
   // Forbidden slot hazards are only defined for MIPSR6 but not microMIPSR6.
   if (!STI->hasMips32r6() || STI->inMicroMipsMode())
     return false;
 
   const MipsInstrInfo *TII = STI->getInstrInfo();
 
   bool Changed = false;
 
   for (MachineFunction::iterator FI = MFp->begin(); FI != MFp->end(); ++FI) {
     for (Iter I = FI->begin(); I != FI->end(); ++I) {
 
       // Forbidden slot hazard handling. Use lookahead over state.
       if (!TII->HasForbiddenSlot(*I))
         continue;
 
       Iter Inst;
       bool LastInstInFunction =
           std::next(I) == FI->end() && std::next(FI) == MFp->end();
       if (!LastInstInFunction) {
         std::pair<Iter, bool> Res = getNextMachineInstr(std::next(I), &*FI);
         LastInstInFunction |= Res.second;
         Inst = Res.first;
       }
 
       if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) {
 
         MachineBasicBlock::instr_iterator Iit = I->getIterator();
         if (std::next(Iit) == FI->end() ||
             std::next(Iit)->getOpcode() != Mips::NOP) {
           Changed = true;
           MIBundleBuilder(&*I).append(
               BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));
           NumInsertedNops++;
         }
       }
     }
   }
 
   return Changed;
 }
 
 bool MipsBranchExpansion::handlePossibleLongBranch() {
 
   LongBranchSeqSize = IsPIC ? ((ABI.IsN64() || STI->isTargetNaCl()) ? 10 : 9)
                             : (STI->hasMips32r6() ? 1 : 2);
 
   if (STI->inMips16Mode() || !STI->enableLongBranchPass())
     return false;
 
   if (SkipLongBranch)
     return false;
 
   initMBBInfo();
 
   SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
   bool EverMadeChange = false, MadeChange = true;
 
   while (MadeChange) {
     MadeChange = false;
 
     for (I = MBBInfos.begin(); I != E; ++I) {
       // Skip if this MBB doesn't have a branch or the branch has already been
       // converted to a long branch.
       if (!I->Br || I->HasLongBranch)
         continue;
 
       int64_t Offset = computeOffset(I->Br);
 
       if (STI->isTargetNaCl()) {
         // The offset calculation does not include sandboxing instructions
         // that will be added later in the MC layer.  Since at this point we
         // don't know the exact amount of code that "sandboxing" will add, we
         // conservatively estimate that code will not grow more than 100%.
         Offset *= 2;
       }
 
       // Check if offset fits into the immediate field of the branch.
       if (!ForceLongBranchFirstPass &&
           TII->isBranchOffsetInRange(I->Br->getOpcode(), Offset))
         continue;
 
       I->HasLongBranch = true;
       I->Size += LongBranchSeqSize * 4;
       ++LongBranches;
       EverMadeChange = MadeChange = true;
     }
   }
 
   ForceLongBranchFirstPass = false;
 
   if (!EverMadeChange)
     return false;
 
   // Do the expansion.
   for (I = MBBInfos.begin(); I != E; ++I)
     if (I->HasLongBranch) {
       expandToLongBranch(*I);
     }
 
   MFp->RenumberBlocks();
 
   return true;
 }
 
 bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) {
   const TargetMachine &TM = MF.getTarget();
   IsPIC = TM.isPositionIndependent();
   ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
   STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
   TII = static_cast<const MipsInstrInfo *>(STI->getInstrInfo());
 
   if (IsPIC && ABI.IsO32() &&
       MF.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
     emitGPDisp(MF, TII);
 
   MFp = &MF;
 
   ForceLongBranchFirstPass = ForceLongBranch;
   // Run these two at least once
   bool longBranchChanged = handlePossibleLongBranch();
   bool forbiddenSlotChanged = handleForbiddenSlot();
 
   bool Changed = longBranchChanged || forbiddenSlotChanged;
 
   // Then run them alternatively while there are changes
   while (forbiddenSlotChanged) {
     longBranchChanged = handlePossibleLongBranch();
     if (!longBranchChanged)
       break;
     forbiddenSlotChanged = handleForbiddenSlot();
   }
 
   return Changed;
 }
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.cpp b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
index a4ab7d3a5780..2b7f64099923 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
@@ -1,280 +1,325 @@
 //===- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains code to lower Mips MachineInstrs to their corresponding
 // MCInst records.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsMCInstLower.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "MCTargetDesc/MipsMCExpr.h"
 #include "MipsAsmPrinter.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <cassert>
 
 using namespace llvm;
 
 MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
   : AsmPrinter(asmprinter) {}
 
 void MipsMCInstLower::Initialize(MCContext *C) {
   Ctx = C;
 }
 
 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
                                               MachineOperandType MOTy,
                                               unsigned Offset) const {
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
   MipsMCExpr::MipsExprKind TargetKind = MipsMCExpr::MEK_None;
   bool IsGpOff = false;
   const MCSymbol *Symbol;
 
   switch(MO.getTargetFlags()) {
   default:
     llvm_unreachable("Invalid target flag!");
   case MipsII::MO_NO_FLAG:
     break;
   case MipsII::MO_GPREL:
     TargetKind = MipsMCExpr::MEK_GPREL;
     break;
   case MipsII::MO_GOT_CALL:
     TargetKind = MipsMCExpr::MEK_GOT_CALL;
     break;
   case MipsII::MO_GOT:
     TargetKind = MipsMCExpr::MEK_GOT;
     break;
   case MipsII::MO_ABS_HI:
     TargetKind = MipsMCExpr::MEK_HI;
     break;
   case MipsII::MO_ABS_LO:
     TargetKind = MipsMCExpr::MEK_LO;
     break;
   case MipsII::MO_TLSGD:
     TargetKind = MipsMCExpr::MEK_TLSGD;
     break;
   case MipsII::MO_TLSLDM:
     TargetKind = MipsMCExpr::MEK_TLSLDM;
     break;
   case MipsII::MO_DTPREL_HI:
     TargetKind = MipsMCExpr::MEK_DTPREL_HI;
     break;
   case MipsII::MO_DTPREL_LO:
     TargetKind = MipsMCExpr::MEK_DTPREL_LO;
     break;
   case MipsII::MO_GOTTPREL:
     TargetKind = MipsMCExpr::MEK_GOTTPREL;
     break;
   case MipsII::MO_TPREL_HI:
     TargetKind = MipsMCExpr::MEK_TPREL_HI;
     break;
   case MipsII::MO_TPREL_LO:
     TargetKind = MipsMCExpr::MEK_TPREL_LO;
     break;
   case MipsII::MO_GPOFF_HI:
     TargetKind = MipsMCExpr::MEK_HI;
     IsGpOff = true;
     break;
   case MipsII::MO_GPOFF_LO:
     TargetKind = MipsMCExpr::MEK_LO;
     IsGpOff = true;
     break;
   case MipsII::MO_GOT_DISP:
     TargetKind = MipsMCExpr::MEK_GOT_DISP;
     break;
   case MipsII::MO_GOT_HI16:
     TargetKind = MipsMCExpr::MEK_GOT_HI16;
     break;
   case MipsII::MO_GOT_LO16:
     TargetKind = MipsMCExpr::MEK_GOT_LO16;
     break;
   case MipsII::MO_GOT_PAGE:
     TargetKind = MipsMCExpr::MEK_GOT_PAGE;
     break;
   case MipsII::MO_GOT_OFST:
     TargetKind = MipsMCExpr::MEK_GOT_OFST;
     break;
   case MipsII::MO_HIGHER:
     TargetKind = MipsMCExpr::MEK_HIGHER;
     break;
   case MipsII::MO_HIGHEST:
     TargetKind = MipsMCExpr::MEK_HIGHEST;
     break;
   case MipsII::MO_CALL_HI16:
     TargetKind = MipsMCExpr::MEK_CALL_HI16;
     break;
   case MipsII::MO_CALL_LO16:
     TargetKind = MipsMCExpr::MEK_CALL_LO16;
     break;
   }
 
   switch (MOTy) {
   case MachineOperand::MO_MachineBasicBlock:
     Symbol = MO.getMBB()->getSymbol();
     break;
 
   case MachineOperand::MO_GlobalAddress:
     Symbol = AsmPrinter.getSymbol(MO.getGlobal());
     Offset += MO.getOffset();
     break;
 
   case MachineOperand::MO_BlockAddress:
     Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
     Offset += MO.getOffset();
     break;
 
   case MachineOperand::MO_ExternalSymbol:
     Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
     Offset += MO.getOffset();
     break;
 
   case MachineOperand::MO_MCSymbol:
     Symbol = MO.getMCSymbol();
     Offset += MO.getOffset();
     break;
 
   case MachineOperand::MO_JumpTableIndex:
     Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
     break;
 
   case MachineOperand::MO_ConstantPoolIndex:
     Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
     Offset += MO.getOffset();
     break;
 
   default:
     llvm_unreachable("<unknown operand type>");
   }
 
   const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, *Ctx);
 
   if (Offset) {
     // Assume offset is never negative.
     assert(Offset > 0);
 
     Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(Offset, *Ctx),
                                    *Ctx);
   }
 
   if (IsGpOff)
     Expr = MipsMCExpr::createGpOff(TargetKind, Expr, *Ctx);
   else if (TargetKind != MipsMCExpr::MEK_None)
     Expr = MipsMCExpr::create(TargetKind, Expr, *Ctx);
 
   return MCOperand::createExpr(Expr);
 }
 
 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
                                         unsigned offset) const {
   MachineOperandType MOTy = MO.getType();
 
   switch (MOTy) {
   default: llvm_unreachable("unknown operand type");
   case MachineOperand::MO_Register:
     // Ignore all implicit register operands.
     if (MO.isImplicit()) break;
     return MCOperand::createReg(MO.getReg());
   case MachineOperand::MO_Immediate:
     return MCOperand::createImm(MO.getImm() + offset);
   case MachineOperand::MO_MachineBasicBlock:
   case MachineOperand::MO_GlobalAddress:
   case MachineOperand::MO_ExternalSymbol:
   case MachineOperand::MO_MCSymbol:
   case MachineOperand::MO_JumpTableIndex:
   case MachineOperand::MO_ConstantPoolIndex:
   case MachineOperand::MO_BlockAddress:
     return LowerSymbolOperand(MO, MOTy, offset);
   case MachineOperand::MO_RegisterMask:
     break;
  }
 
   return MCOperand();
 }
 
 MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
                                      MachineBasicBlock *BB2,
                                      MipsMCExpr::MipsExprKind Kind) const {
   const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::create(BB1->getSymbol(), *Ctx);
   const MCSymbolRefExpr *Sym2 = MCSymbolRefExpr::create(BB2->getSymbol(), *Ctx);
   const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Sym1, Sym2, *Ctx);
 
   return MCOperand::createExpr(MipsMCExpr::create(Kind, Sub, *Ctx));
 }
 
 void MipsMCInstLower::
 lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(Mips::LUi);
 
   // Lower register operand.
   OutMI.addOperand(LowerOperand(MI->getOperand(0)));
 
-  // Create %hi($tgt-$baltgt).
-  OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
-                             MI->getOperand(2).getMBB(),
-                             MipsMCExpr::MEK_HI));
+  MipsMCExpr::MipsExprKind Kind;
+  unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
+  switch (TargetFlags) {
+  case MipsII::MO_HIGHEST:
+    Kind = MipsMCExpr::MEK_HIGHEST;
+    break;
+  case MipsII::MO_HIGHER:
+    Kind = MipsMCExpr::MEK_HIGHER;
+    break;
+  case MipsII::MO_ABS_HI:
+    Kind = MipsMCExpr::MEK_HI;
+    break;
+  case MipsII::MO_ABS_LO:
+    Kind = MipsMCExpr::MEK_LO;
+    break;
+  default:
+    report_fatal_error("Unexpected flags for lowerLongBranchLUi");
+  }
+
+  if (MI->getNumOperands() == 2) {
+    const MCExpr *Expr =
+        MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
+    const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+    OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+  } else if (MI->getNumOperands() == 3) {
+    // Create %hi($tgt-$baltgt).
+    OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
+                               MI->getOperand(2).getMBB(), Kind));
+  }
 }
 
-void MipsMCInstLower::lowerLongBranchADDiu(
-    const MachineInstr *MI, MCInst &OutMI, int Opcode,
-    MipsMCExpr::MipsExprKind Kind) const {
+void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
+                                           MCInst &OutMI, int Opcode) const {
   OutMI.setOpcode(Opcode);
 
+  MipsMCExpr::MipsExprKind Kind;
+  unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
+  switch (TargetFlags) {
+  case MipsII::MO_HIGHEST:
+    Kind = MipsMCExpr::MEK_HIGHEST;
+    break;
+  case MipsII::MO_HIGHER:
+    Kind = MipsMCExpr::MEK_HIGHER;
+    break;
+  case MipsII::MO_ABS_HI:
+    Kind = MipsMCExpr::MEK_HI;
+    break;
+  case MipsII::MO_ABS_LO:
+    Kind = MipsMCExpr::MEK_LO;
+    break;
+  default:
+    report_fatal_error("Unexpected flags for lowerLongBranchADDiu");
+  }
+
   // Lower two register operands.
   for (unsigned I = 0, E = 2; I != E; ++I) {
     const MachineOperand &MO = MI->getOperand(I);
     OutMI.addOperand(LowerOperand(MO));
   }
 
-  // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
-  OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
-                             MI->getOperand(3).getMBB(), Kind));
+  if (MI->getNumOperands() == 3) {
+    // Lower register operand.
+    const MCExpr *Expr =
+        MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
+    const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+    OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+  } else if (MI->getNumOperands() == 4) {
+    // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
+    OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
+                               MI->getOperand(3).getMBB(), Kind));
+  }
 }
 
 bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
                                       MCInst &OutMI) const {
   switch (MI->getOpcode()) {
   default:
     return false;
   case Mips::LONG_BRANCH_LUi:
     lowerLongBranchLUi(MI, OutMI);
     return true;
   case Mips::LONG_BRANCH_ADDiu:
-    lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO);
+    lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
     return true;
   case Mips::LONG_BRANCH_DADDiu:
-    unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
-    if (TargetFlags == MipsII::MO_ABS_HI)
-      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_HI);
-    else if (TargetFlags == MipsII::MO_ABS_LO)
-      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_LO);
-    else
-      report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
+    lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu);
     return true;
   }
 }
 
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   if (lowerLongBranch(MI, OutMI))
     return;
 
   OutMI.setOpcode(MI->getOpcode());
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     MCOperand MCOp = LowerOperand(MO);
 
     if (MCOp.isValid())
       OutMI.addOperand(MCOp);
   }
 }
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.h b/llvm/lib/Target/Mips/MipsMCInstLower.h
index fb5079643827..e19f21c98839 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.h
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.h
@@ -1,54 +1,54 @@
 //===- MipsMCInstLower.h - Lower MachineInstr to MCInst --------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
 #define LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
 
 #include "MCTargetDesc/MipsMCExpr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/Support/Compiler.h"
 
 namespace llvm {
 
 class MachineBasicBlock;
 class MachineInstr;
 class MCContext;
 class MCInst;
 class MCOperand;
 class MipsAsmPrinter;
 
 /// MipsMCInstLower - This class is used to lower an MachineInstr into an
 ///                   MCInst.
 class LLVM_LIBRARY_VISIBILITY MipsMCInstLower {
   using MachineOperandType = MachineOperand::MachineOperandType;
 
   MCContext *Ctx;
   MipsAsmPrinter &AsmPrinter;
 
 public:
   MipsMCInstLower(MipsAsmPrinter &asmprinter);
 
   void Initialize(MCContext *C);
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
   MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
 
 private:
   MCOperand LowerSymbolOperand(const MachineOperand &MO,
                                MachineOperandType MOTy, unsigned Offset) const;
   MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
                       MipsMCExpr::MipsExprKind Kind) const;
   void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
-  void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
-                            MipsMCExpr::MipsExprKind Kind) const;
+  void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
+                            int Opcode) const;
   bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
index a9cd8689ef5a..1e336a810e93 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
@@ -1,215 +1,215 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MM
 # RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
 
   define i32 @a(double %a, double %b) {
   entry:
     %cmp = fcmp une double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
   define i32 @b(double %a, double %b) {
   entry:
     %cmp = fcmp ueq double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
 ...
 ---
 name:            a
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d6', virtual-reg: '' }
   - { reg: '$d7', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: a
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MM:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MM:   BC1F_MM $fcc0, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1F_MM $fcc0, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d6, $d7
 
     FCMP_D32_MM killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
     BC1T_MM killed $fcc0, %bb.2, implicit-def dead $at
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = LI16_MM 0
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.2.return:
     $v0 = LI16_MM 1
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
 ---
 name:            b
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d6', virtual-reg: '' }
   - { reg: '$d7', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: b
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; MM:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; MM:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; PIC:   FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
   ; PIC:   BC1F_MM killed $fcc0, %bb.1, implicit-def dead $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   ; PIC: bb.2.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit killed $v0
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $d6, $d7
 
     FCMP_D32_MM killed renamable $d6, killed renamable $d7, 19, implicit-def $fcc0
     BC1F_MM killed $fcc0, %bb.2, implicit-def dead $at
 
   bb.2.return:
     $v0 = LI16_MM 1
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = LI16_MM 0
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
index 4a9dd5da8465..2f05c6b7ab59 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
@@ -1,219 +1,219 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MM
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
 
   define i32 @a(double %a, double %b) {
   entry:
     %cmp = fcmp une double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 810680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
   define i32 @b(double %a, double %b) {
   entry:
     %cmp = fcmp ueq double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 810680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
 ...
 ---
 name:            a
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d12_64', virtual-reg: '' }
   - { reg: '$d14_64', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: a
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MM:   $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
   ; MM:   BC1EQZC_MMR6 $d0_64, %bb.2, implicit-def $at
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   BC_MMR6 %bb.3
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
   ; PIC:   BC1EQZC_MMR6 $d0_64, %bb.3, implicit-def $at
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d12_64, $d14_64
 
     $f0 = CMP_EQ_D_MMR6 killed $d12_64, killed $d14_64
     BC1NEZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
     $v0 = LI16_MM 0
     PseudoReturn undef $ra, implicit $v0
 
   bb.2.return:
     $v0 = LI16_MM 1
     PseudoReturn undef $ra, implicit $v0
 
 ...
 ---
 name:            b
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d12_64', virtual-reg: '' }
   - { reg: '$d14_64', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: b
   ; MM: bb.0.entry:
   ; MM:   successors: %bb.2(0x30000000), %bb.1(0x50000000)
   ; MM:   $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
   ; MM:   BC1NEZC_MMR6 $d0_64, %bb.2, implicit-def $at
   ; MM: bb.1.entry:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   BC_MMR6 %bb.3
   ; MM: bb.2.if.then:
   ; MM:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
   ; MM:   $v0 = LI16_MM 0
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; MM: bb.3.return:
   ; MM:   $v0 = LI16_MM 1
   ; MM:   JRC16_MM undef $ra, implicit $v0
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
   ; PIC:   $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
   ; PIC:   BC1NEZC_MMR6 $d0_64, %bb.3, implicit-def $at
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   $v0 = LI16_MM 0
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   ; PIC: bb.4.return:
   ; PIC:   $v0 = LI16_MM 1
   ; PIC:   JRC16_MM undef $ra, implicit $v0
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $d12_64, $d14_64
 
     $f0 = CMP_UEQ_D_MMR6 killed $d12_64, killed $d14_64
     BC1EQZC_MMR6 killed $d0_64, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
     $v0 = LI16_MM 0
     PseudoReturn undef $ra, implicit $v0
 
   bb.2.return:
     $v0 = LI16_MM 1
     PseudoReturn undef $ra, implicit $v0
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
index 26058fb916da..0e34890c5efa 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
@@ -1,242 +1,242 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS
 # RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 # Test the long branch expansion of various branches
 
 --- |
 
   define i32 @a(double %a, double %b) {
   entry:
     %cmp = fcmp une double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
   define i32 @b(double %a, double %b) {
   entry:
     %cmp = fcmp une double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:
     ret i32 1
   }
 
 ...
 ---
 name:            a
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d6', virtual-reg: '' }
   - { reg: '$d7', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: a
   ; MIPS: bb.0.entry:
   ; MIPS:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MIPS:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MIPS:   BC1F $fcc0, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
   ; MIPS:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1F $fcc0, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d6, $d7
 
     FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
     BC1T killed $fcc0, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = ADDiu $zero, 0
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.2.return:
     $v0 = ADDiu $zero, 1
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
 ---
 name:            b
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d6', virtual-reg: '' }
   - { reg: '$d7', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: b
   ; MIPS: bb.0.entry:
   ; MIPS:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; MIPS:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; MIPS:   BC1T $fcc0, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1.entry:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.if.then:
   ; MIPS:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 0
   ; MIPS:   }
   ; MIPS: bb.3.return:
   ; MIPS:   PseudoReturn undef $ra, implicit killed $v0 {
   ; MIPS:     $v0 = ADDiu $zero, 1
   ; MIPS:   }
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
   ; PIC:   BC1T $fcc0, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d6, $d7
 
     FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
     BC1F killed $fcc0, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = ADDiu $zero, 0
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.2.return:
     $v0 = ADDiu $zero, 1
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
index cffc2a735e15..9b2e9c53fb3a 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
@@ -1,236 +1,236 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=R6
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
 
   define i32 @a(double %a, double %b) {
   entry:
     %cmp = fcmp une double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:                                          ; preds = %entry
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:                                           ; preds = %entry
     ret i32 1
   }
 
   define i32 @b(double %a, double %b) {
   entry:
     %cmp = fcmp ueq double %a, %b
     br i1 %cmp, label %if.then, label %return
 
   if.then:                                          ; preds = %entry
     call void asm sideeffect ".space 310680", "~{$1}"()
     ret i32 0
 
   return:                                           ; preds = %entry
     ret i32 1
   }
 
 
 ...
 ---
 name:            a
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d12_64', virtual-reg: '' }
   - { reg: '$d14_64', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: a
   ; R6: bb.0.entry:
   ; R6:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1NEZ $d0_64, %bb.2 {
   ; R6:     NOP
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
   ; R6:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: a
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; PIC:   BC1NEZ $d0_64, %bb.3 {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d12_64, $d14_64
 
     $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
     BC1EQZ killed $d0_64, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = ADDiu $zero, 0
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.2.return:
     $v0 = ADDiu $zero, 1
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
 ---
 name:            b
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$d12_64', virtual-reg: '' }
   - { reg: '$d14_64', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: b
   ; R6: bb.0.entry:
   ; R6:   successors: %bb.2(0x50000000), %bb.1(0x30000000)
   ; R6:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; R6:   BC1EQZ $d0_64, %bb.2 {
   ; R6:     NOP
   ; R6:   }
   ; R6: bb.1.entry:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.if.then:
   ; R6:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 0
   ; R6:   }
   ; R6: bb.3.return:
   ; R6:   PseudoReturn undef $ra, implicit killed $v0 {
   ; R6:     $v0 = ADDiu $zero, 1
   ; R6:   }
   ; PIC-LABEL: name: b
   ; PIC: bb.0.entry:
   ; PIC:   successors: %bb.3(0x50000000), %bb.1(0x30000000)
   ; PIC:   $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
   ; PIC:   BC1EQZ $d0_64, %bb.3 {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1.entry:
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2.entry:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.if.then:
   ; PIC:   INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 0
   ; PIC:   }
   ; PIC: bb.4.return:
   ; PIC:   PseudoReturn undef $ra, implicit killed $v0 {
   ; PIC:     $v0 = ADDiu $zero, 1
   ; PIC:   }
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $d12_64, $d14_64
 
     $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
     BC1NEZ killed $d0_64, %bb.2, implicit-def $at
 
   bb.1.if.then:
     INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
     $v0 = ADDiu $zero, 0
     PseudoReturn undef $ra, implicit killed $v0
 
   bb.2.return:
     $v0 = ADDiu $zero, 1
     PseudoReturn undef $ra, implicit killed $v0
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
index e35411d6746b..53d729144a76 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
@@ -1,848 +1,848 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MM
 # RUN: llc -mtriple=mips-mti-linux-gnu -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
   define void @expand_BEQ_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEZ_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGTZ_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLEZ_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTZ_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNE_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BEQZ16_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNEZ16_MM(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
 ...
 ---
 
 name:            expand_BEQ_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BEQ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BNEZC_MM $at, %bb.2, implicit-def $at
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNEZC_MM $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQ_MM killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEZ_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BGEZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BLTZ_MM $at, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGEZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZ_MM $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEZ_MM killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGTZ_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BGTZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BLEZ_MM $at, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGTZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZ_MM $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGTZ_MM killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLEZ_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BLEZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BGTZ_MM $at, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLEZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZ_MM $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLEZ_MM killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTZ_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BLTZ_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BGEZ_MM $at, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLTZ_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZ_MM $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTZ_MM killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNE_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BNE_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $at = ANDi killed renamable $a0, 1
   ; MM:   BEQZC_MM $at, %bb.2, implicit-def $at
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNE_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQZC_MM $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNE_MM killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BEQZ16_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BEQZ16_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $v0 = ANDi killed renamable $a0, 1
   ; MM:   BNEZ16_MM $v0, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQZ16_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $v0 = ANDi killed renamable $a0, 1
   ; PIC:   BNEZ16_MM $v0, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $v0 = ANDi killed renamable $a0, 1
     BEQZ16_MM killed renamable $v0, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNEZ16_MM
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MM-LABEL: name: expand_BNEZ16_MM
   ; MM: bb.0 (%ir-block.0):
   ; MM:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MM:   renamable $v0 = ANDi killed renamable $a0, 1
   ; MM:   BEQZ16_MM $v0, %bb.2, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.1 (%ir-block.0):
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   J %bb.3, implicit-def $at {
   ; MM:     NOP
   ; MM:   }
   ; MM: bb.2.iftrue:
   ; MM:   successors: %bb.3(0x80000000)
   ; MM:   INLINEASM &".space 131068", 1
   ; MM: bb.3.tail:
   ; MM:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNEZ16_MM
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $v0 = ANDi killed renamable $a0, 1
   ; PIC:   BEQZ16_MM $v0, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR_MM %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $v0 = ANDi killed renamable $a0, 1
     BNEZ16_MM killed renamable $v0, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
index 3ff541d9d5df..0db8ddc14421 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
@@ -1,1184 +1,1184 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MMR6
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
   define void @expand_BEQC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNEC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEUC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGTZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLEZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTUC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BEQZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 8388608", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNEZC_MMR6(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 8388608", ""()
     br label %tail
 
   tail:
     ret void
   }
 
 ...
 ---
 
 name:            expand_BEQC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BEQC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BNEC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNEC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNEC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BNEC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BEQC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNEC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BGEC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BLTC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGEC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEUC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BGEUC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BLTUC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGEUC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTUC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BGEZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BLTZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGEZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGTZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BGTZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BLEZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BGTZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLEZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BLEZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BGTZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLEZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BLTC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BGEC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLTC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTUC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BLTUC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BGEUC_MMR6 $at, $zero, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLTUC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEUC_MMR6 $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTUC_MMR6 killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BLTZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BGEZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 131068", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BLTZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BEQZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BEQZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BNEZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 8388608", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BEQZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNEZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 8388608", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 8388608", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNEZC_MMR6
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MMR6-LABEL: name: expand_BNEZC_MMR6
   ; MMR6: bb.0 (%ir-block.0):
   ; MMR6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MMR6:   renamable $at = ANDi killed renamable $a0, 1
   ; MMR6:   BEQZC_MMR6 $at, %bb.2, implicit-def $at
   ; MMR6: bb.1 (%ir-block.0):
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   BC_MMR6 %bb.3
   ; MMR6: bb.2.iftrue:
   ; MMR6:   successors: %bb.3(0x80000000)
   ; MMR6:   INLINEASM &".space 8388608", 1
   ; MMR6: bb.3.tail:
   ; MMR6:   JRC16_MM undef $ra
   ; PIC-LABEL: name: expand_BNEZC_MMR6
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQZC_MMR6 $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC_MMR6 %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC_MMR6 $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 8388608", 1
   ; PIC: bb.4.tail:
   ; PIC:   JRC16_MM undef $ra
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNEZC_MMR6 killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 8388608", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
index a83a0c573021..f945014a53ba 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
@@ -1,1184 +1,1184 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=R6
 # RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
   define void @expand_BEQC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNEC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEUC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGTZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLEZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTUC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BEQZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 8388608", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNEZC(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 8388608", ""()
     br label %tail
 
   tail:
     ret void
   }
 
 ...
 ---
 
 name:            expand_BEQC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BEQC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BNEC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BEQC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNEC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNEC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BNEC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BEQC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BNEC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNEC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BGEC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BLTC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BGEC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEUC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BGEUC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BLTUC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BGEUC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTUC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEUC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BGEZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BLTZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BGEZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGTZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BGTZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BLEZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BGTZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGTZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLEZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BLEZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BGTZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BLEZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLEZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BLTC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BGEC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BLTC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTUC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BLTUC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BGEUC $at, $zero, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BLTUC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEUC $at, $zero, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTUC killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BLTZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BGEZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 131068", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BLTZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BEQZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BEQZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BNEZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 8388608", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BEQZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNEZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 8388608", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 8388608", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNEZC
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; R6-LABEL: name: expand_BNEZC
   ; R6: bb.0 (%ir-block.0):
   ; R6:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; R6:   renamable $at = ANDi killed renamable $a0, 1
   ; R6:   BEQZC $at, %bb.2, implicit-def $at
   ; R6: bb.1 (%ir-block.0):
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   BC %bb.3
   ; R6: bb.2.iftrue:
   ; R6:   successors: %bb.3(0x80000000)
   ; R6:   INLINEASM &".space 8388608", 1
   ; R6: bb.3.tail:
   ; R6:   JIC undef $ra, 0, implicit-def $at
   ; PIC-LABEL: name: expand_BNEZC
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQZC $at, %bb.3, implicit-def $at
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
-  ; PIC:   $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   BALC %bb.2, implicit-def $ra
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   $sp = ADDiu $sp, 8
   ; PIC:   JIC $at, 0, implicit-def $at
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 8388608", 1
   ; PIC: bb.4.tail:
   ; PIC:   JIC undef $ra, 0, implicit-def $at
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNEZC killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 8388608", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
index e656e28020f5..3d8a6dd898bb 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
@@ -1,668 +1,668 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS
 # RUN: llc -mtriple=mips-mti-linux-gnu -o - %s -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
 
 # Test the long branch expansion of various branches
 
 --- |
   define void @expand_BEQ(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGEZ(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BGTZ(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLEZ(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BLTZ(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
   define void @expand_BNE(i1 %a) {
     br i1 %a, label %iftrue, label %tail
 
   iftrue:
     call void asm sideeffect ".space 131068", ""()
     br label %tail
 
   tail:
     ret void
   }
 
 ...
 ---
 
 name:            expand_BEQ
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BEQ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BNE $at, $zero, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BEQ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BNE $at, $zero, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BEQ killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGEZ
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BGEZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BLTZ $at, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BGEZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLTZ $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGEZ killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BGTZ
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BGTZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BLEZ $at, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BGTZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BLEZ $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BGTZ killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLEZ
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BLEZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BGTZ $at, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BLEZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGTZ $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLEZ killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BLTZ
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BLTZ
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BGEZ $at, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BLTZ
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BGEZ $at, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BLTZ killed renamable $at, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...
 ---
 
 name:            expand_BNE
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 registers:
 liveins:
   - { reg: '$a0', virtual-reg: '' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
   adjustsStack:    false
   hasCalls:        false
   stackProtector:  ''
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:
 stack:
 constants:
 body:             |
   ; MIPS-LABEL: name: expand_BNE
   ; MIPS: bb.0 (%ir-block.0):
   ; MIPS:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; MIPS:   renamable $at = ANDi killed renamable $a0, 1
   ; MIPS:   BEQ $at, $zero, %bb.2, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.1 (%ir-block.0):
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   J %bb.3, implicit-def $at {
   ; MIPS:     NOP
   ; MIPS:   }
   ; MIPS: bb.2.iftrue:
   ; MIPS:   successors: %bb.3(0x80000000)
   ; MIPS:   INLINEASM &".space 131068", 1
   ; MIPS: bb.3.tail:
   ; MIPS:   PseudoReturn undef $ra {
   ; MIPS:     NOP
   ; MIPS:   }
   ; PIC-LABEL: name: expand_BNE
   ; PIC: bb.0 (%ir-block.0):
   ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; PIC:   renamable $at = ANDi killed renamable $a0, 1
   ; PIC:   BEQ $at, $zero, %bb.3, implicit-def $at {
   ; PIC:     NOP
   ; PIC:   }
   ; PIC: bb.1 (%ir-block.0):
   ; PIC:   successors: %bb.2(0x80000000)
   ; PIC:   $sp = ADDiu $sp, -8
   ; PIC:   SW $ra, $sp, 0
-  ; PIC:   $at = LONG_BRANCH_LUi %bb.4, %bb.2
+  ; PIC:   $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
   ; PIC:   BAL_BR %bb.2, implicit-def $ra {
-  ; PIC:     $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+  ; PIC:     $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
   ; PIC:   }
   ; PIC: bb.2 (%ir-block.0):
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   $at = ADDu $ra, $at
   ; PIC:   $ra = LW $sp, 0
   ; PIC:   JR $at {
   ; PIC:     $sp = ADDiu $sp, 8
   ; PIC:   }
   ; PIC: bb.3.iftrue:
   ; PIC:   successors: %bb.4(0x80000000)
   ; PIC:   INLINEASM &".space 131068", 1
   ; PIC: bb.4.tail:
   ; PIC:   PseudoReturn undef $ra {
   ; PIC:     NOP
   ; PIC:   }
   bb.0 (%ir-block.0):
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $a0
 
     renamable $at = ANDi killed renamable $a0, 1
     BNE killed renamable $at, $zero, %bb.2, implicit-def $at
 
   bb.1.iftrue:
     successors: %bb.2(0x80000000)
 
     INLINEASM &".space 131068", 1
 
   bb.2.tail:
     PseudoReturn undef $ra
 
 ...