diff --git a/clang/include/clang/Basic/X86Target.def b/clang/include/clang/Basic/X86Target.def index 94ccb9fd8b2f..7baacca6da8e 100644 --- a/clang/include/clang/Basic/X86Target.def +++ b/clang/include/clang/Basic/X86Target.def @@ -1,345 +1,350 @@ //===--- X86Target.def - X86 Feature/Processor Database ---------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines the X86-specific Features and Processors, as used by // the X86 Targets. // //===----------------------------------------------------------------------===// #ifndef PROC_WITH_FEAT #define PROC_WITH_FEAT(ENUM, STRING, IS64BIT, KEYFEATURE) \ PROC(ENUM, STRING, IS64BIT) #endif #ifndef PROC #define PROC(ENUM, STRING, IS64BIT) #endif #ifndef PROC_ALIAS #define PROC_ALIAS(ENUM, ALIAS) #endif #ifndef FEATURE #define FEATURE(ENUM) #endif #ifndef CPU_SPECIFIC #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) #endif #ifndef CPU_SPECIFIC_ALIAS #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) #endif #define PROC_64_BIT true #define PROC_32_BIT false /// \name i386 /// i386-generation processors. //@{ PROC(i386, "i386", PROC_32_BIT) //@} /// \name i486 /// i486-generation processors. //@{ PROC(i486, "i486", PROC_32_BIT) PROC(WinChipC6, "winchip-c6", PROC_32_BIT) PROC(WinChip2, "winchip2", PROC_32_BIT) PROC(C3, "c3", PROC_32_BIT) //@} /// \name i586 /// i586-generation processors, P5 microarchitecture based. //@{ PROC(i586, "i586", PROC_32_BIT) PROC(Pentium, "pentium", PROC_32_BIT) PROC(PentiumMMX, "pentium-mmx", PROC_32_BIT) //@} /// \name i686 /// i686-generation processors, P6 / Pentium M microarchitecture based. //@{ PROC(PentiumPro, "pentiumpro", PROC_32_BIT) PROC(i686, "i686", PROC_32_BIT) PROC(Pentium2, "pentium2", PROC_32_BIT) PROC(Pentium3, "pentium3", PROC_32_BIT) PROC_ALIAS(Pentium3, "pentium3m") PROC(PentiumM, "pentium-m", PROC_32_BIT) PROC(C3_2, "c3-2", PROC_32_BIT) /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. /// Clang however has some logic to support this. // FIXME: Warn, deprecate, and potentially remove this. PROC(Yonah, "yonah", PROC_32_BIT) //@} /// \name Netburst /// Netburst microarchitecture based processors. //@{ PROC(Pentium4, "pentium4", PROC_32_BIT) PROC_ALIAS(Pentium4, "pentium4m") PROC(Prescott, "prescott", PROC_32_BIT) PROC(Nocona, "nocona", PROC_64_BIT) //@} /// \name Core /// Core microarchitecture based processors. //@{ PROC_WITH_FEAT(Core2, "core2", PROC_64_BIT, FEATURE_SSSE3) /// This enumerator, like Yonah, is a bit odd. It is another /// codename which GCC no longer accepts as an option to -march, but Clang /// has some logic for recognizing it. // FIXME: Warn, deprecate, and potentially remove this. PROC(Penryn, "penryn", PROC_64_BIT) //@} /// \name Atom /// Atom processors //@{ PROC_WITH_FEAT(Bonnell, "bonnell", PROC_64_BIT, FEATURE_SSSE3) PROC_ALIAS(Bonnell, "atom") PROC_WITH_FEAT(Silvermont, "silvermont", PROC_64_BIT, FEATURE_SSE4_2) PROC_ALIAS(Silvermont, "slm") PROC(Goldmont, "goldmont", PROC_64_BIT) PROC(GoldmontPlus, "goldmont-plus", PROC_64_BIT) PROC(Tremont, "tremont", PROC_64_BIT) //@} /// \name Nehalem /// Nehalem microarchitecture based processors. PROC_WITH_FEAT(Nehalem, "nehalem", PROC_64_BIT, FEATURE_SSE4_2) PROC_ALIAS(Nehalem, "corei7") /// \name Westmere /// Westmere microarchitecture based processors. PROC_WITH_FEAT(Westmere, "westmere", PROC_64_BIT, FEATURE_PCLMUL) /// \name Sandy Bridge /// Sandy Bridge microarchitecture based processors. PROC_WITH_FEAT(SandyBridge, "sandybridge", PROC_64_BIT, FEATURE_AVX) PROC_ALIAS(SandyBridge, "corei7-avx") /// \name Ivy Bridge /// Ivy Bridge microarchitecture based processors. PROC_WITH_FEAT(IvyBridge, "ivybridge", PROC_64_BIT, FEATURE_AVX) PROC_ALIAS(IvyBridge, "core-avx-i") /// \name Haswell /// Haswell microarchitecture based processors. PROC_WITH_FEAT(Haswell, "haswell", PROC_64_BIT, FEATURE_AVX2) PROC_ALIAS(Haswell, "core-avx2") /// \name Broadwell /// Broadwell microarchitecture based processors. PROC_WITH_FEAT(Broadwell, "broadwell", PROC_64_BIT, FEATURE_AVX2) /// \name Skylake Client /// Skylake client microarchitecture based processors. PROC_WITH_FEAT(SkylakeClient, "skylake", PROC_64_BIT, FEATURE_AVX2) /// \name Skylake Server /// Skylake server microarchitecture based processors. PROC_WITH_FEAT(SkylakeServer, "skylake-avx512", PROC_64_BIT, FEATURE_AVX512F) PROC_ALIAS(SkylakeServer, "skx") /// \name Cascadelake Server /// Cascadelake Server microarchitecture based processors. PROC_WITH_FEAT(Cascadelake, "cascadelake", PROC_64_BIT, FEATURE_AVX512VNNI) /// \name Cooperlake Server /// Cooperlake Server microarchitecture based processors. PROC_WITH_FEAT(Cooperlake, "cooperlake", PROC_64_BIT, FEATURE_AVX512BF16) /// \name Cannonlake Client /// Cannonlake client microarchitecture based processors. PROC_WITH_FEAT(Cannonlake, "cannonlake", PROC_64_BIT, FEATURE_AVX512VBMI) /// \name Icelake Client /// Icelake client microarchitecture based processors. PROC(IcelakeClient, "icelake-client", PROC_64_BIT) /// \name Icelake Server /// Icelake server microarchitecture based processors. PROC(IcelakeServer, "icelake-server", PROC_64_BIT) +/// \name Tigerlake Server +/// Tigerlake Server microarchitecture based processors. +PROC(Tigerlake, "tigerlake", PROC_64_BIT) + /// \name Knights Landing /// Knights Landing processor. PROC_WITH_FEAT(KNL, "knl", PROC_64_BIT, FEATURE_AVX512F) /// \name Knights Mill /// Knights Mill processor. PROC_WITH_FEAT(KNM, "knm", PROC_64_BIT, FEATURE_AVX5124FMAPS) /// \name Lakemont /// Lakemont microarchitecture based processors. PROC(Lakemont, "lakemont", PROC_32_BIT) /// \name K6 /// K6 architecture processors. //@{ PROC(K6, "k6", PROC_32_BIT) PROC(K6_2, "k6-2", PROC_32_BIT) PROC(K6_3, "k6-3", PROC_32_BIT) //@} /// \name K7 /// K7 architecture processors. //@{ PROC(Athlon, "athlon", PROC_32_BIT) PROC_ALIAS(Athlon, "athlon-tbird") PROC(AthlonXP, "athlon-xp", PROC_32_BIT) PROC_ALIAS(AthlonXP, "athlon-mp") PROC_ALIAS(AthlonXP, "athlon-4") //@} /// \name K8 /// K8 architecture processors. //@{ PROC(K8, "k8", PROC_64_BIT) PROC_ALIAS(K8, "athlon64") PROC_ALIAS(K8, "athlon-fx") PROC_ALIAS(K8, "opteron") PROC(K8SSE3, "k8-sse3", PROC_64_BIT) PROC_ALIAS(K8SSE3, "athlon64-sse3") PROC_ALIAS(K8SSE3, "opteron-sse3") PROC_WITH_FEAT(AMDFAM10, "amdfam10", PROC_64_BIT, FEATURE_SSE4_A) PROC_ALIAS(AMDFAM10, "barcelona") //@} /// \name Bobcat /// Bobcat architecture processors. //@{ PROC_WITH_FEAT(BTVER1, "btver1", PROC_64_BIT, FEATURE_SSE4_A) PROC_WITH_FEAT(BTVER2, "btver2", PROC_64_BIT, FEATURE_BMI) //@} /// \name Bulldozer /// Bulldozer architecture processors. //@{ PROC_WITH_FEAT(BDVER1, "bdver1", PROC_64_BIT, FEATURE_XOP) PROC_WITH_FEAT(BDVER2, "bdver2", PROC_64_BIT, FEATURE_FMA) PROC_WITH_FEAT(BDVER3, "bdver3", PROC_64_BIT, FEATURE_FMA) PROC_WITH_FEAT(BDVER4, "bdver4", PROC_64_BIT, FEATURE_AVX2) //@} /// \name zen /// Zen architecture processors. //@{ PROC_WITH_FEAT(ZNVER1, "znver1", PROC_64_BIT, FEATURE_AVX2) PROC_WITH_FEAT(ZNVER2, "znver2", PROC_64_BIT, FEATURE_AVX2) //@} /// This specification is deprecated and will be removed in the future. /// Users should prefer K8. // FIXME: Warn on this when the CPU is set to it. //@{ PROC(x86_64, "x86-64", PROC_64_BIT) //@} /// \name Geode /// Geode processors. //@{ PROC(Geode, "geode", PROC_32_BIT) //@} // List of CPU Supports features in order. These need to remain in the order // required by attribute 'target' checking. Note that not all are supported/ // prioritized by GCC, so synchronization with GCC's implementation may require // changing some existing values. FEATURE(FEATURE_CMOV) FEATURE(FEATURE_MMX) FEATURE(FEATURE_SSE) FEATURE(FEATURE_SSE2) FEATURE(FEATURE_SSE3) FEATURE(FEATURE_SSSE3) FEATURE(FEATURE_SSE4_A) FEATURE(FEATURE_SSE4_1) FEATURE(FEATURE_SSE4_2) FEATURE(FEATURE_POPCNT) FEATURE(FEATURE_AES) FEATURE(FEATURE_PCLMUL) FEATURE(FEATURE_AVX) FEATURE(FEATURE_BMI) FEATURE(FEATURE_FMA4) FEATURE(FEATURE_XOP) FEATURE(FEATURE_FMA) FEATURE(FEATURE_BMI2) FEATURE(FEATURE_AVX2) FEATURE(FEATURE_AVX512F) FEATURE(FEATURE_AVX512VL) FEATURE(FEATURE_AVX512BW) FEATURE(FEATURE_AVX512DQ) FEATURE(FEATURE_AVX512CD) FEATURE(FEATURE_AVX512ER) FEATURE(FEATURE_AVX512PF) FEATURE(FEATURE_AVX512VBMI) FEATURE(FEATURE_AVX512IFMA) FEATURE(FEATURE_AVX5124VNNIW) FEATURE(FEATURE_AVX5124FMAPS) FEATURE(FEATURE_AVX512VPOPCNTDQ) FEATURE(FEATURE_AVX512VBMI2) FEATURE(FEATURE_GFNI) FEATURE(FEATURE_VPCLMULQDQ) FEATURE(FEATURE_AVX512VNNI) FEATURE(FEATURE_AVX512BITALG) FEATURE(FEATURE_AVX512BF16) +FEATURE(FEATURE_AVX512VP2INTERSECT) // FIXME: When commented out features are supported in LLVM, enable them here. CPU_SPECIFIC("generic", 'A', "") CPU_SPECIFIC("pentium", 'B', "") CPU_SPECIFIC("pentium_pro", 'C', "+cmov") CPU_SPECIFIC("pentium_mmx", 'D', "+mmx") CPU_SPECIFIC("pentium_ii", 'E', "+cmov,+mmx") CPU_SPECIFIC("pentium_iii", 'H', "+cmov,+mmx,+sse") CPU_SPECIFIC_ALIAS("pentium_iii_no_xmm_regs", "pentium_iii") CPU_SPECIFIC("pentium_4", 'J', "+cmov,+mmx,+sse,+sse2") CPU_SPECIFIC("pentium_m", 'K', "+cmov,+mmx,+sse,+sse2") CPU_SPECIFIC("pentium_4_sse3", 'L', "+cmov,+mmx,+sse,+sse2,+sse3") CPU_SPECIFIC("core_2_duo_ssse3", 'M', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3") CPU_SPECIFIC("core_2_duo_sse4_1", 'N', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1") CPU_SPECIFIC("atom", 'O', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+movbe") CPU_SPECIFIC("atom_sse4_2", 'c', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt") CPU_SPECIFIC("core_i7_sse4_2", 'P', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt") CPU_SPECIFIC("core_aes_pclmulqdq", 'Q', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt") CPU_SPECIFIC("atom_sse4_2_movbe", 'd', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt") CPU_SPECIFIC("goldmont", 'i', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt") CPU_SPECIFIC("sandybridge", 'R', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx") CPU_SPECIFIC_ALIAS("core_2nd_gen_avx", "sandybridge") CPU_SPECIFIC("ivybridge", 'S', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx") CPU_SPECIFIC_ALIAS("core_3rd_gen_avx", "ivybridge") CPU_SPECIFIC("haswell", 'V', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2") CPU_SPECIFIC_ALIAS("core_4th_gen_avx", "haswell") CPU_SPECIFIC("core_4th_gen_avx_tsx", 'W', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2") CPU_SPECIFIC("broadwell", 'X', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx") CPU_SPECIFIC_ALIAS("core_5th_gen_avx", "broadwell") CPU_SPECIFIC("core_5th_gen_avx_tsx", 'Y', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx") CPU_SPECIFIC("knl", 'Z', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd") CPU_SPECIFIC_ALIAS("mic_avx512", "knl") CPU_SPECIFIC("skylake", 'b', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx") CPU_SPECIFIC( "skylake_avx512", 'a', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512cd,+avx512bw,+avx512vl,+clwb") CPU_SPECIFIC("cannonlake", 'e', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512ifma,+avx512cd,+avx512bw,+avx512vl,+avx512vbmi") CPU_SPECIFIC("knm", 'j', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd,+avx5124fmaps,+avx5124vnniw,+avx512vpopcntdq") #undef CPU_SPECIFIC_ALIAS #undef CPU_SPECIFIC #undef PROC_64_BIT #undef PROC_32_BIT #undef FEATURE #undef PROC #undef PROC_ALIAS #undef PROC_WITH_FEAT diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 786cd8e5a72c..a010b5a36fa1 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -1,1895 +1,1905 @@ //===--- X86.cpp - Implement X86 target feature support -------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements X86 TargetInfo objects. // //===----------------------------------------------------------------------===// #include "X86.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/TargetBuiltins.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/Support/TargetParser.h" namespace clang { namespace targets { const Builtin::Info BuiltinInfoX86[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, #include "clang/Basic/BuiltinsX86.def" #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE}, #include "clang/Basic/BuiltinsX86_64.def" }; static const char *const GCCRegNames[] = { "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", "cr0", "cr2", "cr3", "cr4", "cr8", "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", "bnd0", "bnd1", "bnd2", "bnd3", }; const TargetInfo::AddlRegName AddlRegNames[] = { {{"al", "ah", "eax", "rax"}, 0}, {{"bl", "bh", "ebx", "rbx"}, 3}, {{"cl", "ch", "ecx", "rcx"}, 2}, {{"dl", "dh", "edx", "rdx"}, 1}, {{"esi", "rsi"}, 4}, {{"edi", "rdi"}, 5}, {{"esp", "rsp"}, 7}, {{"ebp", "rbp"}, 6}, {{"r8d", "r8w", "r8b"}, 38}, {{"r9d", "r9w", "r9b"}, 39}, {{"r10d", "r10w", "r10b"}, 40}, {{"r11d", "r11w", "r11b"}, 41}, {{"r12d", "r12w", "r12b"}, 42}, {{"r13d", "r13w", "r13b"}, 43}, {{"r14d", "r14w", "r14b"}, 44}, {{"r15d", "r15w", "r15b"}, 45}, }; } // namespace targets } // namespace clang using namespace clang; using namespace clang::targets; bool X86TargetInfo::setFPMath(StringRef Name) { if (Name == "387") { FPMath = FP_387; return true; } if (Name == "sse") { FPMath = FP_SSE; return true; } return false; } bool X86TargetInfo::initFeatureMap( llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector &FeaturesVec) const { // FIXME: This *really* should not be here. // X86_64 always has SSE2. if (getTriple().getArch() == llvm::Triple::x86_64) setFeatureEnabledImpl(Features, "sse2", true); const CPUKind Kind = getCPUKind(CPU); // Enable X87 for all X86 processors but Lakemont. if (Kind != CK_Lakemont) setFeatureEnabledImpl(Features, "x87", true); // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards // compatibility. if (Kind >= CK_i586 || Kind == CK_Generic) setFeatureEnabledImpl(Features, "cx8", true); switch (Kind) { case CK_Generic: case CK_i386: case CK_i486: case CK_i586: case CK_Pentium: case CK_PentiumPro: case CK_i686: case CK_Lakemont: break; case CK_PentiumMMX: case CK_Pentium2: case CK_K6: case CK_WinChipC6: setFeatureEnabledImpl(Features, "mmx", true); break; case CK_Cooperlake: // CPX inherits all CLX features plus AVX512BF16 setFeatureEnabledImpl(Features, "avx512bf16", true); LLVM_FALLTHROUGH; case CK_Cascadelake: // CLX inherits all SKX features plus AVX512VNNI setFeatureEnabledImpl(Features, "avx512vnni", true); LLVM_FALLTHROUGH; case CK_SkylakeServer: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512dq", true); setFeatureEnabledImpl(Features, "avx512bw", true); setFeatureEnabledImpl(Features, "avx512vl", true); setFeatureEnabledImpl(Features, "clwb", true); setFeatureEnabledImpl(Features, "pku", true); // SkylakeServer cores inherits all SKL features, except SGX goto SkylakeCommon; + case CK_Tigerlake: + setFeatureEnabledImpl(Features, "avx512vp2intersect", true); + setFeatureEnabledImpl(Features, "movdiri", true); + setFeatureEnabledImpl(Features, "movdir64b", true); + setFeatureEnabledImpl(Features, "shstk", true); + // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd + goto IcelakeCommon; + case CK_IcelakeServer: setFeatureEnabledImpl(Features, "pconfig", true); setFeatureEnabledImpl(Features, "wbnoinvd", true); LLVM_FALLTHROUGH; case CK_IcelakeClient: +IcelakeCommon: setFeatureEnabledImpl(Features, "vaes", true); setFeatureEnabledImpl(Features, "gfni", true); setFeatureEnabledImpl(Features, "vpclmulqdq", true); setFeatureEnabledImpl(Features, "avx512bitalg", true); setFeatureEnabledImpl(Features, "avx512vbmi2", true); setFeatureEnabledImpl(Features, "avx512vnni", true); setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); setFeatureEnabledImpl(Features, "rdpid", true); setFeatureEnabledImpl(Features, "clwb", true); LLVM_FALLTHROUGH; case CK_Cannonlake: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512dq", true); setFeatureEnabledImpl(Features, "avx512bw", true); setFeatureEnabledImpl(Features, "avx512vl", true); setFeatureEnabledImpl(Features, "avx512ifma", true); setFeatureEnabledImpl(Features, "avx512vbmi", true); setFeatureEnabledImpl(Features, "pku", true); setFeatureEnabledImpl(Features, "sha", true); LLVM_FALLTHROUGH; case CK_SkylakeClient: setFeatureEnabledImpl(Features, "sgx", true); // SkylakeServer cores inherits all SKL features, except SGX SkylakeCommon: setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaves", true); setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; case CK_Broadwell: setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "prfchw", true); LLVM_FALLTHROUGH; case CK_Haswell: setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "invpcid", true); setFeatureEnabledImpl(Features, "movbe", true); LLVM_FALLTHROUGH; case CK_IvyBridge: setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "fsgsbase", true); LLVM_FALLTHROUGH; case CK_SandyBridge: setFeatureEnabledImpl(Features, "avx", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "xsaveopt", true); LLVM_FALLTHROUGH; case CK_Westmere: setFeatureEnabledImpl(Features, "pclmul", true); LLVM_FALLTHROUGH; case CK_Nehalem: setFeatureEnabledImpl(Features, "sse4.2", true); LLVM_FALLTHROUGH; case CK_Penryn: setFeatureEnabledImpl(Features, "sse4.1", true); LLVM_FALLTHROUGH; case CK_Core2: setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_Nocona: setFeatureEnabledImpl(Features, "cx16", true); LLVM_FALLTHROUGH; case CK_Yonah: case CK_Prescott: setFeatureEnabledImpl(Features, "sse3", true); LLVM_FALLTHROUGH; case CK_PentiumM: case CK_Pentium4: case CK_x86_64: setFeatureEnabledImpl(Features, "sse2", true); LLVM_FALLTHROUGH; case CK_Pentium3: case CK_C3_2: setFeatureEnabledImpl(Features, "sse", true); setFeatureEnabledImpl(Features, "fxsr", true); break; case CK_Tremont: setFeatureEnabledImpl(Features, "cldemote", true); setFeatureEnabledImpl(Features, "movdiri", true); setFeatureEnabledImpl(Features, "movdir64b", true); setFeatureEnabledImpl(Features, "gfni", true); setFeatureEnabledImpl(Features, "waitpkg", true); LLVM_FALLTHROUGH; case CK_GoldmontPlus: setFeatureEnabledImpl(Features, "ptwrite", true); setFeatureEnabledImpl(Features, "rdpid", true); setFeatureEnabledImpl(Features, "sgx", true); LLVM_FALLTHROUGH; case CK_Goldmont: setFeatureEnabledImpl(Features, "sha", true); setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaves", true); setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; case CK_Silvermont: setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "sse4.2", true); setFeatureEnabledImpl(Features, "prfchw", true); LLVM_FALLTHROUGH; case CK_Bonnell: setFeatureEnabledImpl(Features, "movbe", true); setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "sahf", true); break; case CK_KNM: // TODO: Add avx5124fmaps/avx5124vnniw. setFeatureEnabledImpl(Features, "avx512vpopcntdq", true); LLVM_FALLTHROUGH; case CK_KNL: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); setFeatureEnabledImpl(Features, "avx512er", true); setFeatureEnabledImpl(Features, "avx512pf", true); setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "prefetchwt1", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "movbe", true); setFeatureEnabledImpl(Features, "sahf", true); break; case CK_K6_2: case CK_K6_3: case CK_WinChip2: case CK_C3: setFeatureEnabledImpl(Features, "3dnow", true); break; case CK_AMDFAM10: setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "popcnt", true); setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; case CK_K8SSE3: setFeatureEnabledImpl(Features, "sse3", true); LLVM_FALLTHROUGH; case CK_K8: setFeatureEnabledImpl(Features, "sse2", true); LLVM_FALLTHROUGH; case CK_AthlonXP: setFeatureEnabledImpl(Features, "sse", true); setFeatureEnabledImpl(Features, "fxsr", true); LLVM_FALLTHROUGH; case CK_Athlon: case CK_Geode: setFeatureEnabledImpl(Features, "3dnowa", true); break; case CK_BTVER2: setFeatureEnabledImpl(Features, "avx", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "movbe", true); LLVM_FALLTHROUGH; case CK_BTVER1: setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "popcnt", true); setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "sahf", true); break; case CK_ZNVER2: setFeatureEnabledImpl(Features, "clwb", true); setFeatureEnabledImpl(Features, "rdpid", true); setFeatureEnabledImpl(Features, "wbnoinvd", true); LLVM_FALLTHROUGH; case CK_ZNVER1: setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "clzero", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "mwaitx", true); setFeatureEnabledImpl(Features, "movbe", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "popcnt", true); setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "sahf", true); setFeatureEnabledImpl(Features, "sha", true); setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaveopt", true); setFeatureEnabledImpl(Features, "xsaves", true); break; case CK_BDVER4: setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "mwaitx", true); LLVM_FALLTHROUGH; case CK_BDVER3: setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "xsaveopt", true); LLVM_FALLTHROUGH; case CK_BDVER2: setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "tbm", true); LLVM_FALLTHROUGH; case CK_BDVER1: // xop implies avx, sse4a and fma4. setFeatureEnabledImpl(Features, "xop", true); setFeatureEnabledImpl(Features, "lwp", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); setFeatureEnabledImpl(Features, "prfchw", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "sahf", true); break; } if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) return false; // Can't do this earlier because we need to be able to explicitly enable // or disable these features and the things that they depend upon. // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. auto I = Features.find("sse4.2"); if (I != Features.end() && I->getValue() && llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) Features["popcnt"] = true; // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. I = Features.find("3dnow"); if (I != Features.end() && I->getValue() && llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) Features["prfchw"] = true; // Additionally, if SSE is enabled and mmx is not explicitly disabled, // then enable MMX. I = Features.find("sse"); if (I != Features.end() && I->getValue() && llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) Features["mmx"] = true; return true; } void X86TargetInfo::setSSELevel(llvm::StringMap &Features, X86SSEEnum Level, bool Enabled) { if (Enabled) { switch (Level) { case AVX512F: Features["avx512f"] = true; Features["fma"] = true; Features["f16c"] = true; LLVM_FALLTHROUGH; case AVX2: Features["avx2"] = true; LLVM_FALLTHROUGH; case AVX: Features["avx"] = true; Features["xsave"] = true; LLVM_FALLTHROUGH; case SSE42: Features["sse4.2"] = true; LLVM_FALLTHROUGH; case SSE41: Features["sse4.1"] = true; LLVM_FALLTHROUGH; case SSSE3: Features["ssse3"] = true; LLVM_FALLTHROUGH; case SSE3: Features["sse3"] = true; LLVM_FALLTHROUGH; case SSE2: Features["sse2"] = true; LLVM_FALLTHROUGH; case SSE1: Features["sse"] = true; LLVM_FALLTHROUGH; case NoSSE: break; } return; } switch (Level) { case NoSSE: case SSE1: Features["sse"] = false; LLVM_FALLTHROUGH; case SSE2: Features["sse2"] = Features["pclmul"] = Features["aes"] = false; Features["sha"] = Features["gfni"] = false; LLVM_FALLTHROUGH; case SSE3: Features["sse3"] = false; setXOPLevel(Features, NoXOP, false); LLVM_FALLTHROUGH; case SSSE3: Features["ssse3"] = false; LLVM_FALLTHROUGH; case SSE41: Features["sse4.1"] = false; LLVM_FALLTHROUGH; case SSE42: Features["sse4.2"] = false; LLVM_FALLTHROUGH; case AVX: Features["fma"] = Features["avx"] = Features["f16c"] = false; Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false; Features["vpclmulqdq"] = false; setXOPLevel(Features, FMA4, false); LLVM_FALLTHROUGH; case AVX2: Features["avx2"] = false; LLVM_FALLTHROUGH; case AVX512F: Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false; Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false; Features["avx512vl"] = Features["avx512vbmi"] = false; Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; Features["avx512bitalg"] = Features["avx512vnni"] = false; Features["avx512vbmi2"] = Features["avx512bf16"] = false; Features["avx512vp2intersect"] = false; break; } } void X86TargetInfo::setMMXLevel(llvm::StringMap &Features, MMX3DNowEnum Level, bool Enabled) { if (Enabled) { switch (Level) { case AMD3DNowAthlon: Features["3dnowa"] = true; LLVM_FALLTHROUGH; case AMD3DNow: Features["3dnow"] = true; LLVM_FALLTHROUGH; case MMX: Features["mmx"] = true; LLVM_FALLTHROUGH; case NoMMX3DNow: break; } return; } switch (Level) { case NoMMX3DNow: case MMX: Features["mmx"] = false; LLVM_FALLTHROUGH; case AMD3DNow: Features["3dnow"] = false; LLVM_FALLTHROUGH; case AMD3DNowAthlon: Features["3dnowa"] = false; break; } } void X86TargetInfo::setXOPLevel(llvm::StringMap &Features, XOPEnum Level, bool Enabled) { if (Enabled) { switch (Level) { case XOP: Features["xop"] = true; LLVM_FALLTHROUGH; case FMA4: Features["fma4"] = true; setSSELevel(Features, AVX, true); LLVM_FALLTHROUGH; case SSE4A: Features["sse4a"] = true; setSSELevel(Features, SSE3, true); LLVM_FALLTHROUGH; case NoXOP: break; } return; } switch (Level) { case NoXOP: case SSE4A: Features["sse4a"] = false; LLVM_FALLTHROUGH; case FMA4: Features["fma4"] = false; LLVM_FALLTHROUGH; case XOP: Features["xop"] = false; break; } } void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap &Features, StringRef Name, bool Enabled) { // This is a bit of a hack to deal with the sse4 target feature when used // as part of the target attribute. We handle sse4 correctly everywhere // else. See below for more information on how we handle the sse4 options. if (Name != "sse4") Features[Name] = Enabled; if (Name == "mmx") { setMMXLevel(Features, MMX, Enabled); } else if (Name == "sse") { setSSELevel(Features, SSE1, Enabled); } else if (Name == "sse2") { setSSELevel(Features, SSE2, Enabled); } else if (Name == "sse3") { setSSELevel(Features, SSE3, Enabled); } else if (Name == "ssse3") { setSSELevel(Features, SSSE3, Enabled); } else if (Name == "sse4.2") { setSSELevel(Features, SSE42, Enabled); } else if (Name == "sse4.1") { setSSELevel(Features, SSE41, Enabled); } else if (Name == "3dnow") { setMMXLevel(Features, AMD3DNow, Enabled); } else if (Name == "3dnowa") { setMMXLevel(Features, AMD3DNowAthlon, Enabled); } else if (Name == "aes") { if (Enabled) setSSELevel(Features, SSE2, Enabled); else Features["vaes"] = false; } else if (Name == "vaes") { if (Enabled) { setSSELevel(Features, AVX, Enabled); Features["aes"] = true; } } else if (Name == "pclmul") { if (Enabled) setSSELevel(Features, SSE2, Enabled); else Features["vpclmulqdq"] = false; } else if (Name == "vpclmulqdq") { if (Enabled) { setSSELevel(Features, AVX, Enabled); Features["pclmul"] = true; } } else if (Name == "gfni") { if (Enabled) setSSELevel(Features, SSE2, Enabled); } else if (Name == "avx") { setSSELevel(Features, AVX, Enabled); } else if (Name == "avx2") { setSSELevel(Features, AVX2, Enabled); } else if (Name == "avx512f") { setSSELevel(Features, AVX512F, Enabled); } else if (Name.startswith("avx512")) { if (Enabled) setSSELevel(Features, AVX512F, Enabled); // Enable BWI instruction if certain features are being enabled. if ((Name == "avx512vbmi" || Name == "avx512vbmi2" || Name == "avx512bitalg" || Name == "avx512bf16") && Enabled) Features["avx512bw"] = true; // Also disable some features if BWI is being disabled. if (Name == "avx512bw" && !Enabled) { Features["avx512vbmi"] = false; Features["avx512vbmi2"] = false; Features["avx512bitalg"] = false; Features["avx512bf16"] = false; } } else if (Name == "fma") { if (Enabled) setSSELevel(Features, AVX, Enabled); else setSSELevel(Features, AVX512F, Enabled); } else if (Name == "fma4") { setXOPLevel(Features, FMA4, Enabled); } else if (Name == "xop") { setXOPLevel(Features, XOP, Enabled); } else if (Name == "sse4a") { setXOPLevel(Features, SSE4A, Enabled); } else if (Name == "f16c") { if (Enabled) setSSELevel(Features, AVX, Enabled); else setSSELevel(Features, AVX512F, Enabled); } else if (Name == "sha") { if (Enabled) setSSELevel(Features, SSE2, Enabled); } else if (Name == "sse4") { // We can get here via the __target__ attribute since that's not controlled // via the -msse4/-mno-sse4 command line alias. Handle this the same way // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if // disabled. if (Enabled) setSSELevel(Features, SSE42, Enabled); else setSSELevel(Features, SSE41, Enabled); } else if (Name == "xsave") { if (!Enabled) Features["xsaveopt"] = false; } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { if (Enabled) Features["xsave"] = true; } } /// handleTargetFeatures - Perform initialization based on the user /// configured set of features. bool X86TargetInfo::handleTargetFeatures(std::vector &Features, DiagnosticsEngine &Diags) { for (const auto &Feature : Features) { if (Feature[0] != '+') continue; if (Feature == "+aes") { HasAES = true; } else if (Feature == "+vaes") { HasVAES = true; } else if (Feature == "+pclmul") { HasPCLMUL = true; } else if (Feature == "+vpclmulqdq") { HasVPCLMULQDQ = true; } else if (Feature == "+lzcnt") { HasLZCNT = true; } else if (Feature == "+rdrnd") { HasRDRND = true; } else if (Feature == "+fsgsbase") { HasFSGSBASE = true; } else if (Feature == "+bmi") { HasBMI = true; } else if (Feature == "+bmi2") { HasBMI2 = true; } else if (Feature == "+popcnt") { HasPOPCNT = true; } else if (Feature == "+rtm") { HasRTM = true; } else if (Feature == "+prfchw") { HasPRFCHW = true; } else if (Feature == "+rdseed") { HasRDSEED = true; } else if (Feature == "+adx") { HasADX = true; } else if (Feature == "+tbm") { HasTBM = true; } else if (Feature == "+lwp") { HasLWP = true; } else if (Feature == "+fma") { HasFMA = true; } else if (Feature == "+f16c") { HasF16C = true; } else if (Feature == "+gfni") { HasGFNI = true; } else if (Feature == "+avx512cd") { HasAVX512CD = true; } else if (Feature == "+avx512vpopcntdq") { HasAVX512VPOPCNTDQ = true; } else if (Feature == "+avx512vnni") { HasAVX512VNNI = true; } else if (Feature == "+avx512bf16") { HasAVX512BF16 = true; } else if (Feature == "+avx512er") { HasAVX512ER = true; } else if (Feature == "+avx512pf") { HasAVX512PF = true; } else if (Feature == "+avx512dq") { HasAVX512DQ = true; } else if (Feature == "+avx512bitalg") { HasAVX512BITALG = true; } else if (Feature == "+avx512bw") { HasAVX512BW = true; } else if (Feature == "+avx512vl") { HasAVX512VL = true; } else if (Feature == "+avx512vbmi") { HasAVX512VBMI = true; } else if (Feature == "+avx512vbmi2") { HasAVX512VBMI2 = true; } else if (Feature == "+avx512ifma") { HasAVX512IFMA = true; } else if (Feature == "+avx512vp2intersect") { HasAVX512VP2INTERSECT = true; } else if (Feature == "+sha") { HasSHA = true; } else if (Feature == "+mpx") { HasMPX = true; } else if (Feature == "+shstk") { HasSHSTK = true; } else if (Feature == "+movbe") { HasMOVBE = true; } else if (Feature == "+sgx") { HasSGX = true; } else if (Feature == "+cx8") { HasCX8 = true; } else if (Feature == "+cx16") { HasCX16 = true; } else if (Feature == "+fxsr") { HasFXSR = true; } else if (Feature == "+xsave") { HasXSAVE = true; } else if (Feature == "+xsaveopt") { HasXSAVEOPT = true; } else if (Feature == "+xsavec") { HasXSAVEC = true; } else if (Feature == "+xsaves") { HasXSAVES = true; } else if (Feature == "+mwaitx") { HasMWAITX = true; } else if (Feature == "+pku") { HasPKU = true; } else if (Feature == "+clflushopt") { HasCLFLUSHOPT = true; } else if (Feature == "+clwb") { HasCLWB = true; } else if (Feature == "+wbnoinvd") { HasWBNOINVD = true; } else if (Feature == "+prefetchwt1") { HasPREFETCHWT1 = true; } else if (Feature == "+clzero") { HasCLZERO = true; } else if (Feature == "+cldemote") { HasCLDEMOTE = true; } else if (Feature == "+rdpid") { HasRDPID = true; } else if (Feature == "+retpoline-external-thunk") { HasRetpolineExternalThunk = true; } else if (Feature == "+sahf") { HasLAHFSAHF = true; } else if (Feature == "+waitpkg") { HasWAITPKG = true; } else if (Feature == "+movdiri") { HasMOVDIRI = true; } else if (Feature == "+movdir64b") { HasMOVDIR64B = true; } else if (Feature == "+pconfig") { HasPCONFIG = true; } else if (Feature == "+ptwrite") { HasPTWRITE = true; } else if (Feature == "+invpcid") { HasINVPCID = true; } else if (Feature == "+enqcmd") { HasENQCMD = true; } X86SSEEnum Level = llvm::StringSwitch(Feature) .Case("+avx512f", AVX512F) .Case("+avx2", AVX2) .Case("+avx", AVX) .Case("+sse4.2", SSE42) .Case("+sse4.1", SSE41) .Case("+ssse3", SSSE3) .Case("+sse3", SSE3) .Case("+sse2", SSE2) .Case("+sse", SSE1) .Default(NoSSE); SSELevel = std::max(SSELevel, Level); MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch(Feature) .Case("+3dnowa", AMD3DNowAthlon) .Case("+3dnow", AMD3DNow) .Case("+mmx", MMX) .Default(NoMMX3DNow); MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); XOPEnum XLevel = llvm::StringSwitch(Feature) .Case("+xop", XOP) .Case("+fma4", FMA4) .Case("+sse4a", SSE4A) .Default(NoXOP); XOPLevel = std::max(XOPLevel, XLevel); } // LLVM doesn't have a separate switch for fpmath, so only accept it if it // matches the selected sse level. if ((FPMath == FP_SSE && SSELevel < SSE1) || (FPMath == FP_387 && SSELevel >= SSE1)) { Diags.Report(diag::err_target_unsupported_fpmath) << (FPMath == FP_SSE ? "sse" : "387"); return false; } SimdDefaultAlign = hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; return true; } /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro /// definitions for this particular subtarget. void X86TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { // Inline assembly supports X86 flag outputs. Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); std::string CodeModel = getTargetOpts().CodeModel; if (CodeModel == "default") CodeModel = "small"; Builder.defineMacro("__code_model_" + CodeModel + "_"); // Target identification. if (getTriple().getArch() == llvm::Triple::x86_64) { Builder.defineMacro("__amd64__"); Builder.defineMacro("__amd64"); Builder.defineMacro("__x86_64"); Builder.defineMacro("__x86_64__"); if (getTriple().getArchName() == "x86_64h") { Builder.defineMacro("__x86_64h"); Builder.defineMacro("__x86_64h__"); } } else { DefineStd(Builder, "i386", Opts); } Builder.defineMacro("__SEG_GS"); Builder.defineMacro("__SEG_FS"); Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))"); Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))"); // Subtarget options. // FIXME: We are hard-coding the tune parameters based on the CPU, but they // truly should be based on -mtune options. switch (CPU) { case CK_Generic: break; case CK_i386: // The rest are coming from the i386 define above. Builder.defineMacro("__tune_i386__"); break; case CK_i486: case CK_WinChipC6: case CK_WinChip2: case CK_C3: defineCPUMacros(Builder, "i486"); break; case CK_PentiumMMX: Builder.defineMacro("__pentium_mmx__"); Builder.defineMacro("__tune_pentium_mmx__"); LLVM_FALLTHROUGH; case CK_i586: case CK_Pentium: defineCPUMacros(Builder, "i586"); defineCPUMacros(Builder, "pentium"); break; case CK_Pentium3: case CK_PentiumM: Builder.defineMacro("__tune_pentium3__"); LLVM_FALLTHROUGH; case CK_Pentium2: case CK_C3_2: Builder.defineMacro("__tune_pentium2__"); LLVM_FALLTHROUGH; case CK_PentiumPro: case CK_i686: defineCPUMacros(Builder, "i686"); defineCPUMacros(Builder, "pentiumpro"); break; case CK_Pentium4: defineCPUMacros(Builder, "pentium4"); break; case CK_Yonah: case CK_Prescott: case CK_Nocona: defineCPUMacros(Builder, "nocona"); break; case CK_Core2: case CK_Penryn: defineCPUMacros(Builder, "core2"); break; case CK_Bonnell: defineCPUMacros(Builder, "atom"); break; case CK_Silvermont: defineCPUMacros(Builder, "slm"); break; case CK_Goldmont: defineCPUMacros(Builder, "goldmont"); break; case CK_GoldmontPlus: defineCPUMacros(Builder, "goldmont_plus"); break; case CK_Tremont: defineCPUMacros(Builder, "tremont"); break; case CK_Nehalem: case CK_Westmere: case CK_SandyBridge: case CK_IvyBridge: case CK_Haswell: case CK_Broadwell: case CK_SkylakeClient: case CK_SkylakeServer: case CK_Cascadelake: case CK_Cooperlake: case CK_Cannonlake: case CK_IcelakeClient: case CK_IcelakeServer: + case CK_Tigerlake: // FIXME: Historically, we defined this legacy name, it would be nice to // remove it at some point. We've never exposed fine-grained names for // recent primary x86 CPUs, and we should keep it that way. defineCPUMacros(Builder, "corei7"); break; case CK_KNL: defineCPUMacros(Builder, "knl"); break; case CK_KNM: break; case CK_Lakemont: defineCPUMacros(Builder, "i586", /*Tuning*/false); defineCPUMacros(Builder, "pentium", /*Tuning*/false); Builder.defineMacro("__tune_lakemont__"); break; case CK_K6_2: Builder.defineMacro("__k6_2__"); Builder.defineMacro("__tune_k6_2__"); LLVM_FALLTHROUGH; case CK_K6_3: if (CPU != CK_K6_2) { // In case of fallthrough // FIXME: GCC may be enabling these in cases where some other k6 // architecture is specified but -m3dnow is explicitly provided. The // exact semantics need to be determined and emulated here. Builder.defineMacro("__k6_3__"); Builder.defineMacro("__tune_k6_3__"); } LLVM_FALLTHROUGH; case CK_K6: defineCPUMacros(Builder, "k6"); break; case CK_Athlon: case CK_AthlonXP: defineCPUMacros(Builder, "athlon"); if (SSELevel != NoSSE) { Builder.defineMacro("__athlon_sse__"); Builder.defineMacro("__tune_athlon_sse__"); } break; case CK_K8: case CK_K8SSE3: case CK_x86_64: defineCPUMacros(Builder, "k8"); break; case CK_AMDFAM10: defineCPUMacros(Builder, "amdfam10"); break; case CK_BTVER1: defineCPUMacros(Builder, "btver1"); break; case CK_BTVER2: defineCPUMacros(Builder, "btver2"); break; case CK_BDVER1: defineCPUMacros(Builder, "bdver1"); break; case CK_BDVER2: defineCPUMacros(Builder, "bdver2"); break; case CK_BDVER3: defineCPUMacros(Builder, "bdver3"); break; case CK_BDVER4: defineCPUMacros(Builder, "bdver4"); break; case CK_ZNVER1: defineCPUMacros(Builder, "znver1"); break; case CK_ZNVER2: defineCPUMacros(Builder, "znver2"); break; case CK_Geode: defineCPUMacros(Builder, "geode"); break; } // Target properties. Builder.defineMacro("__REGISTER_PREFIX__", ""); // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline // functions in glibc header files that use FP Stack inline asm which the // backend can't deal with (PR879). Builder.defineMacro("__NO_MATH_INLINES"); if (HasAES) Builder.defineMacro("__AES__"); if (HasVAES) Builder.defineMacro("__VAES__"); if (HasPCLMUL) Builder.defineMacro("__PCLMUL__"); if (HasVPCLMULQDQ) Builder.defineMacro("__VPCLMULQDQ__"); if (HasLZCNT) Builder.defineMacro("__LZCNT__"); if (HasRDRND) Builder.defineMacro("__RDRND__"); if (HasFSGSBASE) Builder.defineMacro("__FSGSBASE__"); if (HasBMI) Builder.defineMacro("__BMI__"); if (HasBMI2) Builder.defineMacro("__BMI2__"); if (HasPOPCNT) Builder.defineMacro("__POPCNT__"); if (HasRTM) Builder.defineMacro("__RTM__"); if (HasPRFCHW) Builder.defineMacro("__PRFCHW__"); if (HasRDSEED) Builder.defineMacro("__RDSEED__"); if (HasADX) Builder.defineMacro("__ADX__"); if (HasTBM) Builder.defineMacro("__TBM__"); if (HasLWP) Builder.defineMacro("__LWP__"); if (HasMWAITX) Builder.defineMacro("__MWAITX__"); if (HasMOVBE) Builder.defineMacro("__MOVBE__"); switch (XOPLevel) { case XOP: Builder.defineMacro("__XOP__"); LLVM_FALLTHROUGH; case FMA4: Builder.defineMacro("__FMA4__"); LLVM_FALLTHROUGH; case SSE4A: Builder.defineMacro("__SSE4A__"); LLVM_FALLTHROUGH; case NoXOP: break; } if (HasFMA) Builder.defineMacro("__FMA__"); if (HasF16C) Builder.defineMacro("__F16C__"); if (HasGFNI) Builder.defineMacro("__GFNI__"); if (HasAVX512CD) Builder.defineMacro("__AVX512CD__"); if (HasAVX512VPOPCNTDQ) Builder.defineMacro("__AVX512VPOPCNTDQ__"); if (HasAVX512VNNI) Builder.defineMacro("__AVX512VNNI__"); if (HasAVX512BF16) Builder.defineMacro("__AVX512BF16__"); if (HasAVX512ER) Builder.defineMacro("__AVX512ER__"); if (HasAVX512PF) Builder.defineMacro("__AVX512PF__"); if (HasAVX512DQ) Builder.defineMacro("__AVX512DQ__"); if (HasAVX512BITALG) Builder.defineMacro("__AVX512BITALG__"); if (HasAVX512BW) Builder.defineMacro("__AVX512BW__"); if (HasAVX512VL) Builder.defineMacro("__AVX512VL__"); if (HasAVX512VBMI) Builder.defineMacro("__AVX512VBMI__"); if (HasAVX512VBMI2) Builder.defineMacro("__AVX512VBMI2__"); if (HasAVX512IFMA) Builder.defineMacro("__AVX512IFMA__"); if (HasAVX512VP2INTERSECT) Builder.defineMacro("__AVX512VP2INTERSECT__"); if (HasSHA) Builder.defineMacro("__SHA__"); if (HasFXSR) Builder.defineMacro("__FXSR__"); if (HasXSAVE) Builder.defineMacro("__XSAVE__"); if (HasXSAVEOPT) Builder.defineMacro("__XSAVEOPT__"); if (HasXSAVEC) Builder.defineMacro("__XSAVEC__"); if (HasXSAVES) Builder.defineMacro("__XSAVES__"); if (HasPKU) Builder.defineMacro("__PKU__"); if (HasCLFLUSHOPT) Builder.defineMacro("__CLFLUSHOPT__"); if (HasCLWB) Builder.defineMacro("__CLWB__"); if (HasWBNOINVD) Builder.defineMacro("__WBNOINVD__"); if (HasMPX) Builder.defineMacro("__MPX__"); if (HasSHSTK) Builder.defineMacro("__SHSTK__"); if (HasSGX) Builder.defineMacro("__SGX__"); if (HasPREFETCHWT1) Builder.defineMacro("__PREFETCHWT1__"); if (HasCLZERO) Builder.defineMacro("__CLZERO__"); if (HasRDPID) Builder.defineMacro("__RDPID__"); if (HasCLDEMOTE) Builder.defineMacro("__CLDEMOTE__"); if (HasWAITPKG) Builder.defineMacro("__WAITPKG__"); if (HasMOVDIRI) Builder.defineMacro("__MOVDIRI__"); if (HasMOVDIR64B) Builder.defineMacro("__MOVDIR64B__"); if (HasPCONFIG) Builder.defineMacro("__PCONFIG__"); if (HasPTWRITE) Builder.defineMacro("__PTWRITE__"); if (HasINVPCID) Builder.defineMacro("__INVPCID__"); if (HasENQCMD) Builder.defineMacro("__ENQCMD__"); // Each case falls through to the previous one here. switch (SSELevel) { case AVX512F: Builder.defineMacro("__AVX512F__"); LLVM_FALLTHROUGH; case AVX2: Builder.defineMacro("__AVX2__"); LLVM_FALLTHROUGH; case AVX: Builder.defineMacro("__AVX__"); LLVM_FALLTHROUGH; case SSE42: Builder.defineMacro("__SSE4_2__"); LLVM_FALLTHROUGH; case SSE41: Builder.defineMacro("__SSE4_1__"); LLVM_FALLTHROUGH; case SSSE3: Builder.defineMacro("__SSSE3__"); LLVM_FALLTHROUGH; case SSE3: Builder.defineMacro("__SSE3__"); LLVM_FALLTHROUGH; case SSE2: Builder.defineMacro("__SSE2__"); Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. LLVM_FALLTHROUGH; case SSE1: Builder.defineMacro("__SSE__"); Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. LLVM_FALLTHROUGH; case NoSSE: break; } if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { switch (SSELevel) { case AVX512F: case AVX2: case AVX: case SSE42: case SSE41: case SSSE3: case SSE3: case SSE2: Builder.defineMacro("_M_IX86_FP", Twine(2)); break; case SSE1: Builder.defineMacro("_M_IX86_FP", Twine(1)); break; default: Builder.defineMacro("_M_IX86_FP", Twine(0)); break; } } // Each case falls through to the previous one here. switch (MMX3DNowLevel) { case AMD3DNowAthlon: Builder.defineMacro("__3dNOW_A__"); LLVM_FALLTHROUGH; case AMD3DNow: Builder.defineMacro("__3dNOW__"); LLVM_FALLTHROUGH; case MMX: Builder.defineMacro("__MMX__"); LLVM_FALLTHROUGH; case NoMMX3DNow: break; } if (CPU >= CK_i486 || CPU == CK_Generic) { Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); } if (HasCX8) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); if (HasFloat128) Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); } bool X86TargetInfo::isValidFeatureName(StringRef Name) const { return llvm::StringSwitch(Name) .Case("3dnow", true) .Case("3dnowa", true) .Case("adx", true) .Case("aes", true) .Case("avx", true) .Case("avx2", true) .Case("avx512f", true) .Case("avx512cd", true) .Case("avx512vpopcntdq", true) .Case("avx512vnni", true) .Case("avx512bf16", true) .Case("avx512er", true) .Case("avx512pf", true) .Case("avx512dq", true) .Case("avx512bitalg", true) .Case("avx512bw", true) .Case("avx512vl", true) .Case("avx512vbmi", true) .Case("avx512vbmi2", true) .Case("avx512ifma", true) .Case("avx512vp2intersect", true) .Case("bmi", true) .Case("bmi2", true) .Case("cldemote", true) .Case("clflushopt", true) .Case("clwb", true) .Case("clzero", true) .Case("cx16", true) .Case("enqcmd", true) .Case("f16c", true) .Case("fma", true) .Case("fma4", true) .Case("fsgsbase", true) .Case("fxsr", true) .Case("gfni", true) .Case("invpcid", true) .Case("lwp", true) .Case("lzcnt", true) .Case("mmx", true) .Case("movbe", true) .Case("movdiri", true) .Case("movdir64b", true) .Case("mpx", true) .Case("mwaitx", true) .Case("pclmul", true) .Case("pconfig", true) .Case("pku", true) .Case("popcnt", true) .Case("prefetchwt1", true) .Case("prfchw", true) .Case("ptwrite", true) .Case("rdpid", true) .Case("rdrnd", true) .Case("rdseed", true) .Case("rtm", true) .Case("sahf", true) .Case("sgx", true) .Case("sha", true) .Case("shstk", true) .Case("sse", true) .Case("sse2", true) .Case("sse3", true) .Case("ssse3", true) .Case("sse4", true) .Case("sse4.1", true) .Case("sse4.2", true) .Case("sse4a", true) .Case("tbm", true) .Case("vaes", true) .Case("vpclmulqdq", true) .Case("wbnoinvd", true) .Case("waitpkg", true) .Case("x87", true) .Case("xop", true) .Case("xsave", true) .Case("xsavec", true) .Case("xsaves", true) .Case("xsaveopt", true) .Default(false); } bool X86TargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch(Feature) .Case("adx", HasADX) .Case("aes", HasAES) .Case("avx", SSELevel >= AVX) .Case("avx2", SSELevel >= AVX2) .Case("avx512f", SSELevel >= AVX512F) .Case("avx512cd", HasAVX512CD) .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512vnni", HasAVX512VNNI) .Case("avx512bf16", HasAVX512BF16) .Case("avx512er", HasAVX512ER) .Case("avx512pf", HasAVX512PF) .Case("avx512dq", HasAVX512DQ) .Case("avx512bitalg", HasAVX512BITALG) .Case("avx512bw", HasAVX512BW) .Case("avx512vl", HasAVX512VL) .Case("avx512vbmi", HasAVX512VBMI) .Case("avx512vbmi2", HasAVX512VBMI2) .Case("avx512ifma", HasAVX512IFMA) .Case("avx512vp2intersect", HasAVX512VP2INTERSECT) .Case("bmi", HasBMI) .Case("bmi2", HasBMI2) .Case("cldemote", HasCLDEMOTE) .Case("clflushopt", HasCLFLUSHOPT) .Case("clwb", HasCLWB) .Case("clzero", HasCLZERO) .Case("cx8", HasCX8) .Case("cx16", HasCX16) .Case("enqcmd", HasENQCMD) .Case("f16c", HasF16C) .Case("fma", HasFMA) .Case("fma4", XOPLevel >= FMA4) .Case("fsgsbase", HasFSGSBASE) .Case("fxsr", HasFXSR) .Case("gfni", HasGFNI) .Case("invpcid", HasINVPCID) .Case("lwp", HasLWP) .Case("lzcnt", HasLZCNT) .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) .Case("mmx", MMX3DNowLevel >= MMX) .Case("movbe", HasMOVBE) .Case("movdiri", HasMOVDIRI) .Case("movdir64b", HasMOVDIR64B) .Case("mpx", HasMPX) .Case("mwaitx", HasMWAITX) .Case("pclmul", HasPCLMUL) .Case("pconfig", HasPCONFIG) .Case("pku", HasPKU) .Case("popcnt", HasPOPCNT) .Case("prefetchwt1", HasPREFETCHWT1) .Case("prfchw", HasPRFCHW) .Case("ptwrite", HasPTWRITE) .Case("rdpid", HasRDPID) .Case("rdrnd", HasRDRND) .Case("rdseed", HasRDSEED) .Case("retpoline-external-thunk", HasRetpolineExternalThunk) .Case("rtm", HasRTM) .Case("sahf", HasLAHFSAHF) .Case("sgx", HasSGX) .Case("sha", HasSHA) .Case("shstk", HasSHSTK) .Case("sse", SSELevel >= SSE1) .Case("sse2", SSELevel >= SSE2) .Case("sse3", SSELevel >= SSE3) .Case("ssse3", SSELevel >= SSSE3) .Case("sse4.1", SSELevel >= SSE41) .Case("sse4.2", SSELevel >= SSE42) .Case("sse4a", XOPLevel >= SSE4A) .Case("tbm", HasTBM) .Case("vaes", HasVAES) .Case("vpclmulqdq", HasVPCLMULQDQ) .Case("wbnoinvd", HasWBNOINVD) .Case("waitpkg", HasWAITPKG) .Case("x86", true) .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) .Case("xop", XOPLevel >= XOP) .Case("xsave", HasXSAVE) .Case("xsavec", HasXSAVEC) .Case("xsaves", HasXSAVES) .Case("xsaveopt", HasXSAVEOPT) .Default(false); } // We can't use a generic validation scheme for the features accepted here // versus subtarget features accepted in the target attribute because the // bitfield structure that's initialized in the runtime only supports the // below currently rather than the full range of subtarget features. (See // X86TargetInfo::hasFeature for a somewhat comprehensive list). bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { return llvm::StringSwitch(FeatureStr) #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true) #include "llvm/Support/X86TargetParser.def" .Default(false); } static llvm::X86::ProcessorFeatures getFeature(StringRef Name) { return llvm::StringSwitch(Name) #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM) #include "llvm/Support/X86TargetParser.def" ; // Note, this function should only be used after ensuring the value is // correct, so it asserts if the value is out of range. } static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) { enum class FeatPriority { #define FEATURE(FEAT) FEAT, #include "clang/Basic/X86Target.def" }; switch (Feat) { #define FEATURE(FEAT) \ case llvm::X86::FEAT: \ return static_cast(FeatPriority::FEAT); #include "clang/Basic/X86Target.def" default: llvm_unreachable("No Feature Priority for non-CPUSupports Features"); } } unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { // Valid CPUs have a 'key feature' that compares just better than its key // feature. CPUKind Kind = getCPUKind(Name); if (Kind != CK_Generic) { switch (Kind) { default: llvm_unreachable( "CPU Type without a key feature used in 'target' attribute"); #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \ case CK_##ENUM: \ return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1; #include "clang/Basic/X86Target.def" } } // Now we know we have a feature, so get its priority and shift it a few so // that we have sufficient room for the CPUs (above). return getFeaturePriority(getFeature(Name)) << 1; } bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { return llvm::StringSwitch(Name) #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) #include "clang/Basic/X86Target.def" .Default(false); } static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { return llvm::StringSwitch(Name) #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) #include "clang/Basic/X86Target.def" .Default(Name); } char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { return llvm::StringSwitch(CPUSpecificCPUDispatchNameDealias(Name)) #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) #include "clang/Basic/X86Target.def" .Default(0); } void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( StringRef Name, llvm::SmallVectorImpl &Features) const { StringRef WholeList = llvm::StringSwitch(CPUSpecificCPUDispatchNameDealias(Name)) #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) #include "clang/Basic/X86Target.def" .Default(""); WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); } // We can't use a generic validation scheme for the cpus accepted here // versus subtarget cpus accepted in the target attribute because the // variables intitialized by the runtime only support the below currently // rather than the full range of cpus. bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { return llvm::StringSwitch(FeatureStr) #define X86_VENDOR(ENUM, STRING) .Case(STRING, true) #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \ .Cases(STR, ALIAS, true) #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true) #include "llvm/Support/X86TargetParser.def" .Default(false); } static unsigned matchAsmCCConstraint(const char *&Name) { auto RV = llvm::StringSwitch(Name) .Case("@cca", 4) .Case("@ccae", 5) .Case("@ccb", 4) .Case("@ccbe", 5) .Case("@ccc", 4) .Case("@cce", 4) .Case("@ccz", 4) .Case("@ccg", 4) .Case("@ccge", 5) .Case("@ccl", 4) .Case("@ccle", 5) .Case("@ccna", 5) .Case("@ccnae", 6) .Case("@ccnb", 5) .Case("@ccnbe", 6) .Case("@ccnc", 5) .Case("@ccne", 5) .Case("@ccnz", 5) .Case("@ccng", 5) .Case("@ccnge", 6) .Case("@ccnl", 5) .Case("@ccnle", 6) .Case("@ccno", 5) .Case("@ccnp", 5) .Case("@ccns", 5) .Case("@cco", 4) .Case("@ccp", 4) .Case("@ccs", 4) .Default(0); return RV; } bool X86TargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { default: return false; // Constant constraints. case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 // instructions. case 'Z': // 32-bit unsigned integer constant for use with zero-extending // x86_64 instructions. case 's': Info.setRequiresImmediate(); return true; case 'I': Info.setRequiresImmediate(0, 31); return true; case 'J': Info.setRequiresImmediate(0, 63); return true; case 'K': Info.setRequiresImmediate(-128, 127); return true; case 'L': Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)}); return true; case 'M': Info.setRequiresImmediate(0, 3); return true; case 'N': Info.setRequiresImmediate(0, 255); return true; case 'O': Info.setRequiresImmediate(0, 127); return true; // Register constraints. case 'Y': // 'Y' is the first character for several 2-character constraints. // Shift the pointer to the second character of the constraint. Name++; switch (*Name) { default: return false; case 'z': case '0': // First SSE register. case '2': case 't': // Any SSE register, when SSE2 is enabled. case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. case 'm': // Any MMX register, when inter-unit moves enabled. case 'k': // AVX512 arch mask registers: k1-k7. Info.setAllowsRegister(); return true; } case 'f': // Any x87 floating point stack register. // Constraint 'f' cannot be used for output operands. if (Info.ConstraintStr[0] == '=') return false; Info.setAllowsRegister(); return true; case 'a': // eax. case 'b': // ebx. case 'c': // ecx. case 'd': // edx. case 'S': // esi. case 'D': // edi. case 'A': // edx:eax. case 't': // Top of floating point stack. case 'u': // Second from top of floating point stack. case 'q': // Any register accessible as [r]l: a, b, c, and d. case 'y': // Any MMX register. case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) case 'x': // Any SSE register. case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0 // for intermideate k reg operations). case 'Q': // Any register accessible as [r]h: a, b, c, and d. case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. case 'l': // "Index" registers: any general register that can be used as an // index in a base+index memory access. Info.setAllowsRegister(); return true; // Floating point constant constraints. case 'C': // SSE floating point constant. case 'G': // x87 floating point constant. return true; case '@': // CC condition changes. if (auto Len = matchAsmCCConstraint(Name)) { Name += Len - 1; Info.setAllowsRegister(); return true; } return false; } } bool X86TargetInfo::validateOutputSize(StringRef Constraint, unsigned Size) const { // Strip off constraint modifiers. while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') Constraint = Constraint.substr(1); return validateOperandSize(Constraint, Size); } bool X86TargetInfo::validateInputSize(StringRef Constraint, unsigned Size) const { return validateOperandSize(Constraint, Size); } bool X86TargetInfo::validateOperandSize(StringRef Constraint, unsigned Size) const { switch (Constraint[0]) { default: break; case 'k': // Registers k0-k7 (AVX512) size limit is 64 bit. case 'y': return Size <= 64; case 'f': case 't': case 'u': return Size <= 128; case 'Y': // 'Y' is the first character for several 2-character constraints. switch (Constraint[1]) { default: return false; case 'm': // 'Ym' is synonymous with 'y'. case 'k': return Size <= 64; case 'z': case '0': // XMM0 if (SSELevel >= SSE1) return Size <= 128U; return false; case 'i': case 't': case '2': // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled. if (SSELevel < SSE2) return false; break; } LLVM_FALLTHROUGH; case 'v': case 'x': if (SSELevel >= AVX512F) // 512-bit zmm registers can be used if target supports AVX512F. return Size <= 512U; else if (SSELevel >= AVX) // 256-bit ymm registers can be used if target supports AVX. return Size <= 256U; return Size <= 128U; } return true; } std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { switch (*Constraint) { case '@': if (auto Len = matchAsmCCConstraint(Constraint)) { std::string Converted = "{" + std::string(Constraint, Len) + "}"; Constraint += Len - 1; return Converted; } return std::string(1, *Constraint); case 'a': return std::string("{ax}"); case 'b': return std::string("{bx}"); case 'c': return std::string("{cx}"); case 'd': return std::string("{dx}"); case 'S': return std::string("{si}"); case 'D': return std::string("{di}"); case 'p': // address return std::string("im"); case 't': // top of floating point stack. return std::string("{st}"); case 'u': // second from top of floating point stack. return std::string("{st(1)}"); // second from top of floating point stack. case 'Y': switch (Constraint[1]) { default: // Break from inner switch and fall through (copy single char), // continue parsing after copying the current constraint into // the return string. break; case 'k': case 'm': case 'i': case 't': case 'z': case '0': case '2': // "^" hints llvm that this is a 2 letter constraint. // "Constraint++" is used to promote the string iterator // to the next constraint. return std::string("^") + std::string(Constraint++, 2); } LLVM_FALLTHROUGH; default: return std::string(1, *Constraint); } } bool X86TargetInfo::checkCPUKind(CPUKind Kind) const { // Perform any per-CPU checks necessary to determine if this CPU is // acceptable. switch (Kind) { case CK_Generic: // No processor selected! return false; #define PROC(ENUM, STRING, IS64BIT) \ case CK_##ENUM: \ return IS64BIT || getTriple().getArch() == llvm::Triple::x86; #include "clang/Basic/X86Target.def" } llvm_unreachable("Unhandled CPU kind"); } void X86TargetInfo::fillValidCPUList(SmallVectorImpl &Values) const { #define PROC(ENUM, STRING, IS64BIT) \ if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ Values.emplace_back(STRING); // For aliases we need to lookup the CPUKind to check get the 64-bit ness. #define PROC_ALIAS(ENUM, ALIAS) \ if (checkCPUKind(CK_##ENUM)) \ Values.emplace_back(ALIAS); #include "clang/Basic/X86Target.def" } X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const { return llvm::StringSwitch(CPU) #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM) #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM) #include "clang/Basic/X86Target.def" .Default(CK_Generic); } ArrayRef X86TargetInfo::getGCCRegNames() const { return llvm::makeArrayRef(GCCRegNames); } ArrayRef X86TargetInfo::getGCCAddlRegNames() const { return llvm::makeArrayRef(AddlRegNames); } ArrayRef X86_32TargetInfo::getTargetBuiltins() const { return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1); } ArrayRef X86_64TargetInfo::getTargetBuiltins() const { return llvm::makeArrayRef(BuiltinInfoX86, X86::LastTSBuiltin - Builtin::FirstTSBuiltin); } diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c index ba900bb4920a..87fdf624a969 100644 --- a/clang/test/Driver/x86-march.c +++ b/clang/test/Driver/x86-march.c @@ -1,169 +1,173 @@ // Ensure we support the various CPU architecture names. // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=nocona 2>&1 \ // RUN: | FileCheck %s -check-prefix=nocona // nocona: "-target-cpu" "nocona" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=core2 2>&1 \ // RUN: | FileCheck %s -check-prefix=core2 // core2: "-target-cpu" "core2" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=penryn 2>&1 \ // RUN: | FileCheck %s -check-prefix=penryn // penryn: "-target-cpu" "penryn" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=nehalem 2>&1 \ // RUN: | FileCheck %s -check-prefix=nehalem // nehalem: "-target-cpu" "nehalem" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=westmere 2>&1 \ // RUN: | FileCheck %s -check-prefix=westmere // westmere: "-target-cpu" "westmere" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=sandybridge 2>&1 \ // RUN: | FileCheck %s -check-prefix=sandybridge // sandybridge: "-target-cpu" "sandybridge" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=ivybridge 2>&1 \ // RUN: | FileCheck %s -check-prefix=ivybridge // ivybridge: "-target-cpu" "ivybridge" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=haswell 2>&1 \ // RUN: | FileCheck %s -check-prefix=haswell // haswell: "-target-cpu" "haswell" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=broadwell 2>&1 \ // RUN: | FileCheck %s -check-prefix=broadwell // broadwell: "-target-cpu" "broadwell" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=skylake 2>&1 \ // RUN: | FileCheck %s -check-prefix=skylake // skylake: "-target-cpu" "skylake" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=skylake-avx512 2>&1 \ // RUN: | FileCheck %s -check-prefix=skylake-avx512 // skylake-avx512: "-target-cpu" "skylake-avx512" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=skx 2>&1 \ // RUN: | FileCheck %s -check-prefix=skx // skx: "-target-cpu" "skx" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=cascadelake 2>&1 \ // RUN: | FileCheck %s -check-prefix=cascadelake // cascadelake: "-target-cpu" "cascadelake" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=cooperlake 2>&1 \ // RUN: | FileCheck %s -check-prefix=cooperlake // cooperlake: "-target-cpu" "cooperlake" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=knl 2>&1 \ // RUN: | FileCheck %s -check-prefix=knl // knl: "-target-cpu" "knl" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=knm 2>&1 \ // RUN: | FileCheck %s -check-prefix=knm // knm: "-target-cpu" "knm" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=cannonlake 2>&1 \ // RUN: | FileCheck %s -check-prefix=cannonlake // cannonlake: "-target-cpu" "cannonlake" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-client 2>&1 \ // RUN: | FileCheck %s -check-prefix=icelake-client // icelake-client: "-target-cpu" "icelake-client" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=icelake-server 2>&1 \ // RUN: | FileCheck %s -check-prefix=icelake-server // icelake-server: "-target-cpu" "icelake-server" // +// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=tigerlake 2>&1 \ +// RUN: | FileCheck %s -check-prefix=tigerlake +// tigerlake: "-target-cpu" "tigerlake" +// // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \ // RUN: | FileCheck %s -check-prefix=lakemont // lakemont: "-target-cpu" "lakemont" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bonnell 2>&1 \ // RUN: | FileCheck %s -check-prefix=bonnell // bonnell: "-target-cpu" "bonnell" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=silvermont 2>&1 \ // RUN: | FileCheck %s -check-prefix=silvermont // silvermont: "-target-cpu" "silvermont" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=goldmont 2>&1 \ // RUN: | FileCheck %s -check-prefix=goldmont // goldmont: "-target-cpu" "goldmont" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=goldmont-plus 2>&1 \ // RUN: | FileCheck %s -check-prefix=goldmont-plus // goldmont-plus: "-target-cpu" "goldmont-plus" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=tremont 2>&1 \ // RUN: | FileCheck %s -check-prefix=tremont // tremont: "-target-cpu" "tremont" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=k8 2>&1 \ // RUN: | FileCheck %s -check-prefix=k8 // k8: "-target-cpu" "k8" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=opteron 2>&1 \ // RUN: | FileCheck %s -check-prefix=opteron // opteron: "-target-cpu" "opteron" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=athlon64 2>&1 \ // RUN: | FileCheck %s -check-prefix=athlon64 // athlon64: "-target-cpu" "athlon64" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=athlon-fx 2>&1 \ // RUN: | FileCheck %s -check-prefix=athlon-fx // athlon-fx: "-target-cpu" "athlon-fx" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=k8-sse3 2>&1 \ // RUN: | FileCheck %s -check-prefix=k8-sse3 // k8-sse3: "-target-cpu" "k8-sse3" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=opteron-sse3 2>&1 \ // RUN: | FileCheck %s -check-prefix=opteron-sse3 // opteron-sse3: "-target-cpu" "opteron-sse3" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=athlon64-sse3 2>&1 \ // RUN: | FileCheck %s -check-prefix=athlon64-sse3 // athlon64-sse3: "-target-cpu" "athlon64-sse3" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=amdfam10 2>&1 \ // RUN: | FileCheck %s -check-prefix=amdfam10 // amdfam10: "-target-cpu" "amdfam10" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=barcelona 2>&1 \ // RUN: | FileCheck %s -check-prefix=barcelona // barcelona: "-target-cpu" "barcelona" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bdver1 2>&1 \ // RUN: | FileCheck %s -check-prefix=bdver1 // bdver1: "-target-cpu" "bdver1" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bdver2 2>&1 \ // RUN: | FileCheck %s -check-prefix=bdver2 // bdver2: "-target-cpu" "bdver2" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bdver3 2>&1 \ // RUN: | FileCheck %s -check-prefix=bdver3 // bdver3: "-target-cpu" "bdver3" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=bdver4 2>&1 \ // RUN: | FileCheck %s -check-prefix=bdver4 // bdver4: "-target-cpu" "bdver4" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=btver1 2>&1 \ // RUN: | FileCheck %s -check-prefix=btver1 // btver1: "-target-cpu" "btver1" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=btver2 2>&1 \ // RUN: | FileCheck %s -check-prefix=btver2 // btver2: "-target-cpu" "btver2" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver1 2>&1 \ // RUN: | FileCheck %s -check-prefix=znver1 // znver1: "-target-cpu" "znver1" // // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver2 2>&1 \ // RUN: | FileCheck %s -check-prefix=znver2 // znver2: "-target-cpu" "znver2" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 2831aaefa0d3..e7dc6ed478b6 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -1,158 +1,158 @@ // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix ARM // ARM: error: unknown target CPU 'not-a-cpu' // ARM: note: valid target CPU values are: // ARM-SAME: arm2 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' // AARCH64: note: valid target CPU values are: // AARCH64-SAME: cortex-a35, // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' // X86: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, // X86-SAME: i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, // X86-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, -// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, knl, knm, lakemont, k6, k6-2, k6-3, +// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3, // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, // X86-SAME: x86-64, geode // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64 // X86_64: error: unknown target CPU 'not-a-cpu' // X86_64: note: valid target CPU values are: nocona, core2, penryn, bonnell, // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, -// X86_64-SAME: icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, +// X86_64-SAME: icelake-client, icelake-server, tigerlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX // NVPTX: error: unknown target CPU 'not-a-cpu' // NVPTX: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, // NVPTX-SAME: sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix R600 // R600: error: unknown target CPU 'not-a-cpu' // R600: note: valid target CPU values are: r600, rv630, rv635, r630, rs780, // R600-SAME: rs880, rv610, rv620, rv670, rv710, rv730, rv740, rv770, cedar, // R600-SAME: palm, cypress, hemlock, juniper, redwood, sumo, sumo2, barts, // R600-SAME: caicos, aruba, cayman, turks // RUN: not %clang_cc1 -triple amdgcn--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AMDGCN // AMDGCN: error: unknown target CPU 'not-a-cpu' // AMDGCN: note: valid target CPU values are: gfx600, tahiti, gfx601, hainan, // AMDGCN-SAME: oland, pitcairn, verde, gfx700, kaveri, gfx701, hawaii, gfx702, // AMDGCN-SAME: gfx703, kabini, mullins, gfx704, bonaire, gfx801, carrizo, // AMDGCN-SAME: gfx802, iceland, tonga, gfx803, fiji, polaris10, polaris11, // AMDGCN-SAME: gfx810, stoney, gfx900, gfx902 // RUN: not %clang_cc1 -triple wasm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix WEBASM // WEBASM: error: unknown target CPU 'not-a-cpu' // WEBASM: note: valid target CPU values are: mvp, bleeding-edge, generic // RUN: not %clang_cc1 -triple systemz--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix SYSTEMZ // SYSTEMZ: error: unknown target CPU 'not-a-cpu' // SYSTEMZ: note: valid target CPU values are: arch8, z10, arch9, z196, arch10, // SYSTEMZ-SAME: zEC12, arch11, z13, arch12, z14, arch13 // RUN: not %clang_cc1 -triple sparc--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix SPARC // SPARC: error: unknown target CPU 'not-a-cpu' // SPARC: note: valid target CPU values are: v8, supersparc, sparclite, f934, // SPARC-SAME: hypersparc, sparclite86x, sparclet, tsc701, v9, ultrasparc, // SPARC-SAME: ultrasparc3, niagara, niagara2, niagara3, niagara4, ma2100, // SPARC-SAME: ma2150, ma2155, ma2450, ma2455, ma2x5x, ma2080, ma2085, ma2480, // SPARC-SAME: ma2485, ma2x8x, myriad2, myriad2.1, myriad2.2, myriad2.3, leon2, // SPARC-SAME: at697e, at697f, leon3, ut699, gr712rc, leon4, gr740 // RUN: not %clang_cc1 -triple sparcv9--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix SPARCV9 // SPARCV9: error: unknown target CPU 'not-a-cpu' // SPARCV9: note: valid target CPU values are: v9, ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 // RUN: not %clang_cc1 -triple powerpc--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix PPC // PPC: error: unknown target CPU 'not-a-cpu' // PPC: note: valid target CPU values are: generic, 440, 450, 601, 602, 603, // PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750, // PPC-SAME: 970, g5, a2, a2q, e500mc, e5500, power3, pwr3, power4, pwr4, // PPC-SAME: power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7, // PPC-SAME: pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64, ppc64, // PPC-SAME: powerpc64le, ppc64le // RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS // MIPS: error: unknown target CPU 'not-a-cpu' // MIPS: note: valid target CPU values are: mips1, mips2, mips3, mips4, mips5, // MIPS-SAME: mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2, // MIPS-SAME: mips64r3, mips64r5, mips64r6, octeon, p5600 // RUN: not %clang_cc1 -triple lanai--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix LANAI // LANAI: error: unknown target CPU 'not-a-cpu' // LANAI: note: valid target CPU values are: v11 // RUN: not %clang_cc1 -triple hexagon--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix HEXAGON // HEXAGON: error: unknown target CPU 'not-a-cpu' // HEXAGON: note: valid target CPU values are: hexagonv5, hexagonv55, // HEXAGON-SAME: hexagonv60, hexagonv62, hexagonv65 // RUN: not %clang_cc1 -triple bpf--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix BPF // BPF: error: unknown target CPU 'not-a-cpu' // BPF: note: valid target CPU values are: generic, v1, v2, v3, probe // RUN: not %clang_cc1 -triple avr--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AVR // AVR: error: unknown target CPU 'not-a-cpu' // AVR: note: valid target CPU values are: avr1, avr2, avr25, avr3, avr31, // AVR-SAME: avr35, avr4, avr5, avr51, avr6, avrxmega1, avrxmega2, avrxmega3, // AVR-SAME: avrxmega4, avrxmega5, avrxmega6, avrxmega7, avrtiny, at90s1200, // AVR-SAME: attiny11, attiny12, attiny15, attiny28, at90s2313, at90s2323, // AVR-SAME: at90s2333, at90s2343, attiny22, attiny26, at86rf401, at90s4414, // AVR-SAME: t90s4433, at90s4434, at90s8515, at90c8534, at90s8535, ata5272, // AVR-SAME: ttiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, // AVR-SAME: ttiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, // AVR-SAME: ttiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, // AVR-SAME: ttiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, // AVR-SAME: ttiny828, at43usb355, at76c711, atmega103, at43usb320, attiny167, // AVR-SAME: t90usb82, at90usb162, ata5505, atmega8u2, atmega16u2, // AVR-SAME: atmega32u2, attiny1634, atmega8, ata6289, atmega8a, ata6285, // AVR-SAME: ata6286, atmega48, atmega48a, atmega48pa, atmega48p, atmega88, // AVR-SAME: atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, // AVR-SAME: atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, // AVR-SAME: at90pwm81, ata5790, ata5795, atmega16, atmega16a, atmega161, // AVR-SAME: atmega162, atmega163, atmega164a, atmega164p, atmega164pa, // AVR-SAME: atmega165, atmega165a, atmega165p, atmega165pa, atmega168, // AVR-SAME: atmega168a, atmega168p, atmega168pa, atmega169, atmega169a, // AVR-SAME: atmega169p, atmega169pa, atmega32, atmega32a, atmega323, // AVR-SAME: atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, // AVR-SAME: atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, // AVR-SAME: atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, // AVR-SAME: atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, // AVR-SAME: atmega3290pa, atmega406, atmega64, atmega64a, atmega640, atmega644, // AVR-SAME: atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, // AVR-SAME: tmega645p, atmega649, atmega649a, atmega649p, atmega6450, // AVR-SAME: tmega6450a, atmega6450p, atmega6490, atmega6490a, atmega6490p, // AVR-SAME: tmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, // AVR-SAME: tmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, // AVR-SAME: tmega64hve, at90can32, at90can64, at90pwm161, at90pwm216, // AVR-SAME: t90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, // AVR-SAME: tmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, // AVR-SAME: t90usb647, at90scr100, at94k, m3000, atmega128, atmega128a, // AVR-SAME: tmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, // AVR-SAME: tmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, // AVR-SAME: t90usb1287, atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2, // AVR-SAME: txmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega32a4, // AVR-SAME: txmega32a4u, atxmega32c4, atxmega32d4, atxmega32e5, atxmega16e5, // AVR-SAME: txmega8e5, atxmega32x1, atxmega64a3, atxmega64a3u, atxmega64a4u, // AVR-SAME: txmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4, // AVR-SAME: txmega64a1, atxmega64a1u, atxmega128a3, atxmega128a3u, // AVR-SAME: txmega128b1, atxmega128b3, atxmega128c3, atxmega128d3, // AVR-SAME: txmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, // AVR-SAME: txmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, // AVR-SAME: txmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, // AVR-SAME: txmega384d3, atxmega128a1, atxmega128a1u, atxmega128a4u, // AVR-SAME: ttiny4, attiny5, attiny9, attiny10, attiny20, attiny40, attiny102, // AVR-SAME: attiny104 diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index 4b3f2339d498..b21d6f5ead88 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1,3192 +1,3319 @@ // Begin X86/GCC/Linux tests ---------------- // RUN: %clang -march=i386 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I386_M32 // CHECK_I386_M32: #define __i386 1 // CHECK_I386_M32: #define __i386__ 1 // CHECK_I386_M32: #define __tune_i386__ 1 // CHECK_I386_M32: #define i386 1 // RUN: not %clang -march=i386 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I386_M64 // CHECK_I386_M64: error: {{.*}} // RUN: %clang -march=i486 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I486_M32 // CHECK_I486_M32: #define __i386 1 // CHECK_I486_M32: #define __i386__ 1 // CHECK_I486_M32: #define __i486 1 // CHECK_I486_M32: #define __i486__ 1 // CHECK_I486_M32: #define __tune_i486__ 1 // CHECK_I486_M32: #define i386 1 // RUN: not %clang -march=i486 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I486_M64 // CHECK_I486_M64: error: {{.*}} // RUN: %clang -march=i586 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I586_M32 // CHECK_I586_M32: #define __i386 1 // CHECK_I586_M32: #define __i386__ 1 // CHECK_I586_M32: #define __i586 1 // CHECK_I586_M32: #define __i586__ 1 // CHECK_I586_M32: #define __pentium 1 // CHECK_I586_M32: #define __pentium__ 1 // CHECK_I586_M32: #define __tune_i586__ 1 // CHECK_I586_M32: #define __tune_pentium__ 1 // CHECK_I586_M32: #define i386 1 // RUN: not %clang -march=i586 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I586_M64 // CHECK_I586_M64: error: {{.*}} // RUN: %clang -march=pentium -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M32 // CHECK_PENTIUM_M32: #define __i386 1 // CHECK_PENTIUM_M32: #define __i386__ 1 // CHECK_PENTIUM_M32: #define __i586 1 // CHECK_PENTIUM_M32: #define __i586__ 1 // CHECK_PENTIUM_M32: #define __pentium 1 // CHECK_PENTIUM_M32: #define __pentium__ 1 // CHECK_PENTIUM_M32: #define __tune_i586__ 1 // CHECK_PENTIUM_M32: #define __tune_pentium__ 1 // CHECK_PENTIUM_M32: #define i386 1 // RUN: not %clang -march=pentium -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M64 // CHECK_PENTIUM_M64: error: {{.*}} // RUN: %clang -march=pentium-mmx -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_MMX_M32 // CHECK_PENTIUM_MMX_M32: #define __MMX__ 1 // CHECK_PENTIUM_MMX_M32: #define __i386 1 // CHECK_PENTIUM_MMX_M32: #define __i386__ 1 // CHECK_PENTIUM_MMX_M32: #define __i586 1 // CHECK_PENTIUM_MMX_M32: #define __i586__ 1 // CHECK_PENTIUM_MMX_M32: #define __pentium 1 // CHECK_PENTIUM_MMX_M32: #define __pentium__ 1 // CHECK_PENTIUM_MMX_M32: #define __pentium_mmx__ 1 // CHECK_PENTIUM_MMX_M32: #define __tune_i586__ 1 // CHECK_PENTIUM_MMX_M32: #define __tune_pentium__ 1 // CHECK_PENTIUM_MMX_M32: #define __tune_pentium_mmx__ 1 // CHECK_PENTIUM_MMX_M32: #define i386 1 // RUN: not %clang -march=pentium-mmx -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_MMX_M64 // CHECK_PENTIUM_MMX_M64: error: {{.*}} // RUN: %clang -march=winchip-c6 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP_C6_M32 // CHECK_WINCHIP_C6_M32: #define __MMX__ 1 // CHECK_WINCHIP_C6_M32: #define __i386 1 // CHECK_WINCHIP_C6_M32: #define __i386__ 1 // CHECK_WINCHIP_C6_M32: #define __i486 1 // CHECK_WINCHIP_C6_M32: #define __i486__ 1 // CHECK_WINCHIP_C6_M32: #define __tune_i486__ 1 // CHECK_WINCHIP_C6_M32: #define i386 1 // RUN: not %clang -march=winchip-c6 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP_C6_M64 // CHECK_WINCHIP_C6_M64: error: {{.*}} // RUN: %clang -march=winchip2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP2_M32 // CHECK_WINCHIP2_M32: #define __3dNOW__ 1 // CHECK_WINCHIP2_M32: #define __MMX__ 1 // CHECK_WINCHIP2_M32: #define __i386 1 // CHECK_WINCHIP2_M32: #define __i386__ 1 // CHECK_WINCHIP2_M32: #define __i486 1 // CHECK_WINCHIP2_M32: #define __i486__ 1 // CHECK_WINCHIP2_M32: #define __tune_i486__ 1 // CHECK_WINCHIP2_M32: #define i386 1 // RUN: not %clang -march=winchip2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_WINCHIP2_M64 // CHECK_WINCHIP2_M64: error: {{.*}} // RUN: %clang -march=c3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_M32 // CHECK_C3_M32: #define __3dNOW__ 1 // CHECK_C3_M32: #define __MMX__ 1 // CHECK_C3_M32: #define __i386 1 // CHECK_C3_M32: #define __i386__ 1 // CHECK_C3_M32: #define __i486 1 // CHECK_C3_M32: #define __i486__ 1 // CHECK_C3_M32: #define __tune_i486__ 1 // CHECK_C3_M32: #define i386 1 // RUN: not %clang -march=c3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_M64 // CHECK_C3_M64: error: {{.*}} // RUN: %clang -march=c3-2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_2_M32 // CHECK_C3_2_M32: #define __MMX__ 1 // CHECK_C3_2_M32: #define __SSE__ 1 // CHECK_C3_2_M32: #define __i386 1 // CHECK_C3_2_M32: #define __i386__ 1 // CHECK_C3_2_M32: #define __i686 1 // CHECK_C3_2_M32: #define __i686__ 1 // CHECK_C3_2_M32: #define __pentiumpro 1 // CHECK_C3_2_M32: #define __pentiumpro__ 1 // CHECK_C3_2_M32: #define __tune_i686__ 1 // CHECK_C3_2_M32: #define __tune_pentium2__ 1 // CHECK_C3_2_M32: #define __tune_pentiumpro__ 1 // CHECK_C3_2_M32: #define i386 1 // RUN: not %clang -march=c3-2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_C3_2_M64 // CHECK_C3_2_M64: error: {{.*}} // RUN: %clang -march=i686 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I686_M32 // CHECK_I686_M32: #define __i386 1 // CHECK_I686_M32: #define __i386__ 1 // CHECK_I686_M32: #define __i686 1 // CHECK_I686_M32: #define __i686__ 1 // CHECK_I686_M32: #define __pentiumpro 1 // CHECK_I686_M32: #define __pentiumpro__ 1 // CHECK_I686_M32: #define __tune_i686__ 1 // CHECK_I686_M32: #define __tune_pentiumpro__ 1 // CHECK_I686_M32: #define i386 1 // RUN: not %clang -march=i686 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_I686_M64 // CHECK_I686_M64: error: {{.*}} // RUN: %clang -march=pentiumpro -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUMPRO_M32 // CHECK_PENTIUMPRO_M32: #define __i386 1 // CHECK_PENTIUMPRO_M32: #define __i386__ 1 // CHECK_PENTIUMPRO_M32: #define __i686 1 // CHECK_PENTIUMPRO_M32: #define __i686__ 1 // CHECK_PENTIUMPRO_M32: #define __pentiumpro 1 // CHECK_PENTIUMPRO_M32: #define __pentiumpro__ 1 // CHECK_PENTIUMPRO_M32: #define __tune_i686__ 1 // CHECK_PENTIUMPRO_M32: #define __tune_pentiumpro__ 1 // CHECK_PENTIUMPRO_M32: #define i386 1 // RUN: not %clang -march=pentiumpro -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUMPRO_M64 // CHECK_PENTIUMPRO_M64: error: {{.*}} // RUN: %clang -march=pentium2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM2_M32 // CHECK_PENTIUM2_M32: #define __MMX__ 1 // CHECK_PENTIUM2_M32: #define __i386 1 // CHECK_PENTIUM2_M32: #define __i386__ 1 // CHECK_PENTIUM2_M32: #define __i686 1 // CHECK_PENTIUM2_M32: #define __i686__ 1 // CHECK_PENTIUM2_M32: #define __pentiumpro 1 // CHECK_PENTIUM2_M32: #define __pentiumpro__ 1 // CHECK_PENTIUM2_M32: #define __tune_i686__ 1 // CHECK_PENTIUM2_M32: #define __tune_pentium2__ 1 // CHECK_PENTIUM2_M32: #define __tune_pentiumpro__ 1 // CHECK_PENTIUM2_M32: #define i386 1 // RUN: not %clang -march=pentium2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM2_M64 // CHECK_PENTIUM2_M64: error: {{.*}} // RUN: %clang -march=pentium3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3_M32 // CHECK_PENTIUM3_M32: #define __MMX__ 1 // CHECK_PENTIUM3_M32: #define __SSE__ 1 // CHECK_PENTIUM3_M32: #define __i386 1 // CHECK_PENTIUM3_M32: #define __i386__ 1 // CHECK_PENTIUM3_M32: #define __i686 1 // CHECK_PENTIUM3_M32: #define __i686__ 1 // CHECK_PENTIUM3_M32: #define __pentiumpro 1 // CHECK_PENTIUM3_M32: #define __pentiumpro__ 1 // CHECK_PENTIUM3_M32: #define __tune_i686__ 1 // CHECK_PENTIUM3_M32: #define __tune_pentium2__ 1 // CHECK_PENTIUM3_M32: #define __tune_pentium3__ 1 // CHECK_PENTIUM3_M32: #define __tune_pentiumpro__ 1 // CHECK_PENTIUM3_M32: #define i386 1 // RUN: not %clang -march=pentium3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3_M64 // CHECK_PENTIUM3_M64: error: {{.*}} // RUN: %clang -march=pentium3m -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3M_M32 // CHECK_PENTIUM3M_M32: #define __MMX__ 1 // CHECK_PENTIUM3M_M32: #define __SSE__ 1 // CHECK_PENTIUM3M_M32: #define __i386 1 // CHECK_PENTIUM3M_M32: #define __i386__ 1 // CHECK_PENTIUM3M_M32: #define __i686 1 // CHECK_PENTIUM3M_M32: #define __i686__ 1 // CHECK_PENTIUM3M_M32: #define __pentiumpro 1 // CHECK_PENTIUM3M_M32: #define __pentiumpro__ 1 // CHECK_PENTIUM3M_M32: #define __tune_i686__ 1 // CHECK_PENTIUM3M_M32: #define __tune_pentiumpro__ 1 // CHECK_PENTIUM3M_M32: #define i386 1 // RUN: not %clang -march=pentium3m -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM3M_M64 // CHECK_PENTIUM3M_M64: error: {{.*}} // RUN: %clang -march=pentium-m -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M_M32 // CHECK_PENTIUM_M_M32: #define __MMX__ 1 // CHECK_PENTIUM_M_M32: #define __SSE2__ 1 // CHECK_PENTIUM_M_M32: #define __SSE__ 1 // CHECK_PENTIUM_M_M32: #define __i386 1 // CHECK_PENTIUM_M_M32: #define __i386__ 1 // CHECK_PENTIUM_M_M32: #define __i686 1 // CHECK_PENTIUM_M_M32: #define __i686__ 1 // CHECK_PENTIUM_M_M32: #define __pentiumpro 1 // CHECK_PENTIUM_M_M32: #define __pentiumpro__ 1 // CHECK_PENTIUM_M_M32: #define __tune_i686__ 1 // CHECK_PENTIUM_M_M32: #define __tune_pentiumpro__ 1 // CHECK_PENTIUM_M_M32: #define i386 1 // RUN: not %clang -march=pentium-m -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM_M_M64 // CHECK_PENTIUM_M_M64: error: {{.*}} // RUN: %clang -march=pentium4 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4_M32 // CHECK_PENTIUM4_M32: #define __MMX__ 1 // CHECK_PENTIUM4_M32: #define __SSE2__ 1 // CHECK_PENTIUM4_M32: #define __SSE__ 1 // CHECK_PENTIUM4_M32: #define __i386 1 // CHECK_PENTIUM4_M32: #define __i386__ 1 // CHECK_PENTIUM4_M32: #define __pentium4 1 // CHECK_PENTIUM4_M32: #define __pentium4__ 1 // CHECK_PENTIUM4_M32: #define __tune_pentium4__ 1 // CHECK_PENTIUM4_M32: #define i386 1 // RUN: not %clang -march=pentium4 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4_M64 // CHECK_PENTIUM4_M64: error: {{.*}} // RUN: %clang -march=pentium4m -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4M_M32 // CHECK_PENTIUM4M_M32: #define __MMX__ 1 // CHECK_PENTIUM4M_M32: #define __SSE2__ 1 // CHECK_PENTIUM4M_M32: #define __SSE__ 1 // CHECK_PENTIUM4M_M32: #define __i386 1 // CHECK_PENTIUM4M_M32: #define __i386__ 1 // CHECK_PENTIUM4M_M32: #define __pentium4 1 // CHECK_PENTIUM4M_M32: #define __pentium4__ 1 // CHECK_PENTIUM4M_M32: #define __tune_pentium4__ 1 // CHECK_PENTIUM4M_M32: #define i386 1 // RUN: not %clang -march=pentium4m -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PENTIUM4M_M64 // CHECK_PENTIUM4M_M64: error: {{.*}} // RUN: %clang -march=yonah -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_YONAH_M32 // CHECK_YONAH_M32: #define __MMX__ 1 // CHECK_YONAH_M32: #define __SSE2__ 1 // CHECK_YONAH_M32: #define __SSE3__ 1 // CHECK_YONAH_M32: #define __SSE__ 1 // CHECK_YONAH_M32: #define __i386 1 // CHECK_YONAH_M32: #define __i386__ 1 // CHECK_YONAH_M32: #define __nocona 1 // CHECK_YONAH_M32: #define __nocona__ 1 // CHECK_YONAH_M32: #define __tune_nocona__ 1 // CHECK_YONAH_M32: #define i386 1 // RUN: not %clang -march=yonah -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_YONAH_M64 // CHECK_YONAH_M64: error: {{.*}} // RUN: %clang -march=prescott -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PRESCOTT_M32 // CHECK_PRESCOTT_M32: #define __MMX__ 1 // CHECK_PRESCOTT_M32: #define __SSE2__ 1 // CHECK_PRESCOTT_M32: #define __SSE3__ 1 // CHECK_PRESCOTT_M32: #define __SSE__ 1 // CHECK_PRESCOTT_M32: #define __i386 1 // CHECK_PRESCOTT_M32: #define __i386__ 1 // CHECK_PRESCOTT_M32: #define __nocona 1 // CHECK_PRESCOTT_M32: #define __nocona__ 1 // CHECK_PRESCOTT_M32: #define __tune_nocona__ 1 // CHECK_PRESCOTT_M32: #define i386 1 // RUN: not %clang -march=prescott -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PRESCOTT_M64 // CHECK_PRESCOTT_M64: error: {{.*}} // RUN: %clang -march=nocona -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_NOCONA_M32 // CHECK_NOCONA_M32: #define __MMX__ 1 // CHECK_NOCONA_M32: #define __SSE2__ 1 // CHECK_NOCONA_M32: #define __SSE3__ 1 // CHECK_NOCONA_M32: #define __SSE__ 1 // CHECK_NOCONA_M32: #define __i386 1 // CHECK_NOCONA_M32: #define __i386__ 1 // CHECK_NOCONA_M32: #define __nocona 1 // CHECK_NOCONA_M32: #define __nocona__ 1 // CHECK_NOCONA_M32: #define __tune_nocona__ 1 // CHECK_NOCONA_M32: #define i386 1 // RUN: %clang -march=nocona -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_NOCONA_M64 // CHECK_NOCONA_M64: #define __MMX__ 1 // CHECK_NOCONA_M64: #define __SSE2_MATH__ 1 // CHECK_NOCONA_M64: #define __SSE2__ 1 // CHECK_NOCONA_M64: #define __SSE3__ 1 // CHECK_NOCONA_M64: #define __SSE_MATH__ 1 // CHECK_NOCONA_M64: #define __SSE__ 1 // CHECK_NOCONA_M64: #define __amd64 1 // CHECK_NOCONA_M64: #define __amd64__ 1 // CHECK_NOCONA_M64: #define __nocona 1 // CHECK_NOCONA_M64: #define __nocona__ 1 // CHECK_NOCONA_M64: #define __tune_nocona__ 1 // CHECK_NOCONA_M64: #define __x86_64 1 // CHECK_NOCONA_M64: #define __x86_64__ 1 // RUN: %clang -march=core2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE2_M32 // CHECK_CORE2_M32: #define __MMX__ 1 // CHECK_CORE2_M32: #define __SSE2__ 1 // CHECK_CORE2_M32: #define __SSE3__ 1 // CHECK_CORE2_M32: #define __SSE__ 1 // CHECK_CORE2_M32: #define __SSSE3__ 1 // CHECK_CORE2_M32: #define __core2 1 // CHECK_CORE2_M32: #define __core2__ 1 // CHECK_CORE2_M32: #define __i386 1 // CHECK_CORE2_M32: #define __i386__ 1 // CHECK_CORE2_M32: #define __tune_core2__ 1 // CHECK_CORE2_M32: #define i386 1 // RUN: %clang -march=core2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE2_M64 // CHECK_CORE2_M64: #define __MMX__ 1 // CHECK_CORE2_M64: #define __SSE2_MATH__ 1 // CHECK_CORE2_M64: #define __SSE2__ 1 // CHECK_CORE2_M64: #define __SSE3__ 1 // CHECK_CORE2_M64: #define __SSE_MATH__ 1 // CHECK_CORE2_M64: #define __SSE__ 1 // CHECK_CORE2_M64: #define __SSSE3__ 1 // CHECK_CORE2_M64: #define __amd64 1 // CHECK_CORE2_M64: #define __amd64__ 1 // CHECK_CORE2_M64: #define __core2 1 // CHECK_CORE2_M64: #define __core2__ 1 // CHECK_CORE2_M64: #define __tune_core2__ 1 // CHECK_CORE2_M64: #define __x86_64 1 // CHECK_CORE2_M64: #define __x86_64__ 1 // RUN: %clang -march=corei7 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_M32 // CHECK_COREI7_M32: #define __MMX__ 1 // CHECK_COREI7_M32: #define __POPCNT__ 1 // CHECK_COREI7_M32: #define __SSE2__ 1 // CHECK_COREI7_M32: #define __SSE3__ 1 // CHECK_COREI7_M32: #define __SSE4_1__ 1 // CHECK_COREI7_M32: #define __SSE4_2__ 1 // CHECK_COREI7_M32: #define __SSE__ 1 // CHECK_COREI7_M32: #define __SSSE3__ 1 // CHECK_COREI7_M32: #define __corei7 1 // CHECK_COREI7_M32: #define __corei7__ 1 // CHECK_COREI7_M32: #define __i386 1 // CHECK_COREI7_M32: #define __i386__ 1 // CHECK_COREI7_M32: #define __tune_corei7__ 1 // CHECK_COREI7_M32: #define i386 1 // RUN: %clang -march=corei7 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_M64 // CHECK_COREI7_M64: #define __MMX__ 1 // CHECK_COREI7_M64: #define __POPCNT__ 1 // CHECK_COREI7_M64: #define __SSE2_MATH__ 1 // CHECK_COREI7_M64: #define __SSE2__ 1 // CHECK_COREI7_M64: #define __SSE3__ 1 // CHECK_COREI7_M64: #define __SSE4_1__ 1 // CHECK_COREI7_M64: #define __SSE4_2__ 1 // CHECK_COREI7_M64: #define __SSE_MATH__ 1 // CHECK_COREI7_M64: #define __SSE__ 1 // CHECK_COREI7_M64: #define __SSSE3__ 1 // CHECK_COREI7_M64: #define __amd64 1 // CHECK_COREI7_M64: #define __amd64__ 1 // CHECK_COREI7_M64: #define __corei7 1 // CHECK_COREI7_M64: #define __corei7__ 1 // CHECK_COREI7_M64: #define __tune_corei7__ 1 // CHECK_COREI7_M64: #define __x86_64 1 // CHECK_COREI7_M64: #define __x86_64__ 1 // RUN: %clang -march=corei7-avx -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_AVX_M32 // CHECK_COREI7_AVX_M32: #define __AVX__ 1 // CHECK_COREI7_AVX_M32: #define __MMX__ 1 // CHECK_COREI7_AVX_M32: #define __PCLMUL__ 1 // CHECK_COREI7_AVX_M32-NOT: __RDRND__ // CHECK_COREI7_AVX_M32: #define __POPCNT__ 1 // CHECK_COREI7_AVX_M32: #define __SSE2__ 1 // CHECK_COREI7_AVX_M32: #define __SSE3__ 1 // CHECK_COREI7_AVX_M32: #define __SSE4_1__ 1 // CHECK_COREI7_AVX_M32: #define __SSE4_2__ 1 // CHECK_COREI7_AVX_M32: #define __SSE__ 1 // CHECK_COREI7_AVX_M32: #define __SSSE3__ 1 // CHECK_COREI7_AVX_M32: #define __XSAVEOPT__ 1 // CHECK_COREI7_AVX_M32: #define __XSAVE__ 1 // CHECK_COREI7_AVX_M32: #define __corei7 1 // CHECK_COREI7_AVX_M32: #define __corei7__ 1 // CHECK_COREI7_AVX_M32: #define __i386 1 // CHECK_COREI7_AVX_M32: #define __i386__ 1 // CHECK_COREI7_AVX_M32: #define __tune_corei7__ 1 // CHECK_COREI7_AVX_M32: #define i386 1 // RUN: %clang -march=corei7-avx -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_COREI7_AVX_M64 // CHECK_COREI7_AVX_M64: #define __AVX__ 1 // CHECK_COREI7_AVX_M64: #define __MMX__ 1 // CHECK_COREI7_AVX_M64: #define __PCLMUL__ 1 // CHECK_COREI7_AVX_M64-NOT: __RDRND__ // CHECK_COREI7_AVX_M64: #define __POPCNT__ 1 // CHECK_COREI7_AVX_M64: #define __SSE2_MATH__ 1 // CHECK_COREI7_AVX_M64: #define __SSE2__ 1 // CHECK_COREI7_AVX_M64: #define __SSE3__ 1 // CHECK_COREI7_AVX_M64: #define __SSE4_1__ 1 // CHECK_COREI7_AVX_M64: #define __SSE4_2__ 1 // CHECK_COREI7_AVX_M64: #define __SSE_MATH__ 1 // CHECK_COREI7_AVX_M64: #define __SSE__ 1 // CHECK_COREI7_AVX_M64: #define __SSSE3__ 1 // CHECK_COREI7_AVX_M64: #define __XSAVEOPT__ 1 // CHECK_COREI7_AVX_M64: #define __XSAVE__ 1 // CHECK_COREI7_AVX_M64: #define __amd64 1 // CHECK_COREI7_AVX_M64: #define __amd64__ 1 // CHECK_COREI7_AVX_M64: #define __corei7 1 // CHECK_COREI7_AVX_M64: #define __corei7__ 1 // CHECK_COREI7_AVX_M64: #define __tune_corei7__ 1 // CHECK_COREI7_AVX_M64: #define __x86_64 1 // CHECK_COREI7_AVX_M64: #define __x86_64__ 1 // RUN: %clang -march=core-avx-i -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX_I_M32 // CHECK_CORE_AVX_I_M32: #define __AVX__ 1 // CHECK_CORE_AVX_I_M32: #define __F16C__ 1 // CHECK_CORE_AVX_I_M32: #define __MMX__ 1 // CHECK_CORE_AVX_I_M32: #define __PCLMUL__ 1 // CHECK_CORE_AVX_I_M32: #define __RDRND__ 1 // CHECK_CORE_AVX_I_M32: #define __SSE2__ 1 // CHECK_CORE_AVX_I_M32: #define __SSE3__ 1 // CHECK_CORE_AVX_I_M32: #define __SSE4_1__ 1 // CHECK_CORE_AVX_I_M32: #define __SSE4_2__ 1 // CHECK_CORE_AVX_I_M32: #define __SSE__ 1 // CHECK_CORE_AVX_I_M32: #define __SSSE3__ 1 // CHECK_CORE_AVX_I_M32: #define __XSAVEOPT__ 1 // CHECK_CORE_AVX_I_M32: #define __XSAVE__ 1 // CHECK_CORE_AVX_I_M32: #define __corei7 1 // CHECK_CORE_AVX_I_M32: #define __corei7__ 1 // CHECK_CORE_AVX_I_M32: #define __i386 1 // CHECK_CORE_AVX_I_M32: #define __i386__ 1 // CHECK_CORE_AVX_I_M32: #define __tune_corei7__ 1 // CHECK_CORE_AVX_I_M32: #define i386 1 // RUN: %clang -march=core-avx-i -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX_I_M64 // CHECK_CORE_AVX_I_M64: #define __AVX__ 1 // CHECK_CORE_AVX_I_M64: #define __F16C__ 1 // CHECK_CORE_AVX_I_M64: #define __MMX__ 1 // CHECK_CORE_AVX_I_M64: #define __PCLMUL__ 1 // CHECK_CORE_AVX_I_M64: #define __RDRND__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE2_MATH__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE2__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE3__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE4_1__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE4_2__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE_MATH__ 1 // CHECK_CORE_AVX_I_M64: #define __SSE__ 1 // CHECK_CORE_AVX_I_M64: #define __SSSE3__ 1 // CHECK_CORE_AVX_I_M64: #define __XSAVEOPT__ 1 // CHECK_CORE_AVX_I_M64: #define __XSAVE__ 1 // CHECK_CORE_AVX_I_M64: #define __amd64 1 // CHECK_CORE_AVX_I_M64: #define __amd64__ 1 // CHECK_CORE_AVX_I_M64: #define __corei7 1 // CHECK_CORE_AVX_I_M64: #define __corei7__ 1 // CHECK_CORE_AVX_I_M64: #define __tune_corei7__ 1 // CHECK_CORE_AVX_I_M64: #define __x86_64 1 // CHECK_CORE_AVX_I_M64: #define __x86_64__ 1 // RUN: %clang -march=core-avx2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX2_M32 // CHECK_CORE_AVX2_M32: #define __AVX2__ 1 // CHECK_CORE_AVX2_M32: #define __AVX__ 1 // CHECK_CORE_AVX2_M32: #define __BMI2__ 1 // CHECK_CORE_AVX2_M32: #define __BMI__ 1 // CHECK_CORE_AVX2_M32: #define __F16C__ 1 // CHECK_CORE_AVX2_M32: #define __FMA__ 1 // CHECK_CORE_AVX2_M32: #define __INVPCID__ 1 // CHECK_CORE_AVX2_M32: #define __LZCNT__ 1 // CHECK_CORE_AVX2_M32: #define __MMX__ 1 // CHECK_CORE_AVX2_M32: #define __MOVBE__ 1 // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1 // CHECK_CORE_AVX2_M32: #define __POPCNT__ 1 // CHECK_CORE_AVX2_M32: #define __RDRND__ 1 // CHECK_CORE_AVX2_M32: #define __SSE2__ 1 // CHECK_CORE_AVX2_M32: #define __SSE3__ 1 // CHECK_CORE_AVX2_M32: #define __SSE4_1__ 1 // CHECK_CORE_AVX2_M32: #define __SSE4_2__ 1 // CHECK_CORE_AVX2_M32: #define __SSE__ 1 // CHECK_CORE_AVX2_M32: #define __SSSE3__ 1 // CHECK_CORE_AVX2_M32: #define __XSAVEOPT__ 1 // CHECK_CORE_AVX2_M32: #define __XSAVE__ 1 // CHECK_CORE_AVX2_M32: #define __corei7 1 // CHECK_CORE_AVX2_M32: #define __corei7__ 1 // CHECK_CORE_AVX2_M32: #define __i386 1 // CHECK_CORE_AVX2_M32: #define __i386__ 1 // CHECK_CORE_AVX2_M32: #define __tune_corei7__ 1 // CHECK_CORE_AVX2_M32: #define i386 1 // RUN: %clang -march=core-avx2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CORE_AVX2_M64 // CHECK_CORE_AVX2_M64: #define __AVX2__ 1 // CHECK_CORE_AVX2_M64: #define __AVX__ 1 // CHECK_CORE_AVX2_M64: #define __BMI2__ 1 // CHECK_CORE_AVX2_M64: #define __BMI__ 1 // CHECK_CORE_AVX2_M64: #define __F16C__ 1 // CHECK_CORE_AVX2_M64: #define __FMA__ 1 // CHECK_CORE_AVX2_M64: #define __INVPCID__ 1 // CHECK_CORE_AVX2_M64: #define __LZCNT__ 1 // CHECK_CORE_AVX2_M64: #define __MMX__ 1 // CHECK_CORE_AVX2_M64: #define __MOVBE__ 1 // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1 // CHECK_CORE_AVX2_M64: #define __POPCNT__ 1 // CHECK_CORE_AVX2_M64: #define __RDRND__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1 // CHECK_CORE_AVX2_M64: #define __SSE2__ 1 // CHECK_CORE_AVX2_M64: #define __SSE3__ 1 // CHECK_CORE_AVX2_M64: #define __SSE4_1__ 1 // CHECK_CORE_AVX2_M64: #define __SSE4_2__ 1 // CHECK_CORE_AVX2_M64: #define __SSE_MATH__ 1 // CHECK_CORE_AVX2_M64: #define __SSE__ 1 // CHECK_CORE_AVX2_M64: #define __SSSE3__ 1 // CHECK_CORE_AVX2_M64: #define __XSAVEOPT__ 1 // CHECK_CORE_AVX2_M64: #define __XSAVE__ 1 // CHECK_CORE_AVX2_M64: #define __amd64 1 // CHECK_CORE_AVX2_M64: #define __amd64__ 1 // CHECK_CORE_AVX2_M64: #define __corei7 1 // CHECK_CORE_AVX2_M64: #define __corei7__ 1 // CHECK_CORE_AVX2_M64: #define __tune_corei7__ 1 // CHECK_CORE_AVX2_M64: #define __x86_64 1 // CHECK_CORE_AVX2_M64: #define __x86_64__ 1 // RUN: %clang -march=broadwell -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BROADWELL_M32 // CHECK_BROADWELL_M32: #define __ADX__ 1 // CHECK_BROADWELL_M32: #define __AVX2__ 1 // CHECK_BROADWELL_M32: #define __AVX__ 1 // CHECK_BROADWELL_M32: #define __BMI2__ 1 // CHECK_BROADWELL_M32: #define __BMI__ 1 // CHECK_BROADWELL_M32: #define __F16C__ 1 // CHECK_BROADWELL_M32: #define __FMA__ 1 // CHECK_BROADWELL_M32: #define __INVPCID__ 1 // CHECK_BROADWELL_M32: #define __LZCNT__ 1 // CHECK_BROADWELL_M32: #define __MMX__ 1 // CHECK_BROADWELL_M32: #define __MOVBE__ 1 // CHECK_BROADWELL_M32: #define __PCLMUL__ 1 // CHECK_BROADWELL_M32: #define __POPCNT__ 1 // CHECK_BROADWELL_M32: #define __PRFCHW__ 1 // CHECK_BROADWELL_M32: #define __RDRND__ 1 // CHECK_BROADWELL_M32: #define __RDSEED__ 1 // CHECK_BROADWELL_M32: #define __SSE2__ 1 // CHECK_BROADWELL_M32: #define __SSE3__ 1 // CHECK_BROADWELL_M32: #define __SSE4_1__ 1 // CHECK_BROADWELL_M32: #define __SSE4_2__ 1 // CHECK_BROADWELL_M32: #define __SSE__ 1 // CHECK_BROADWELL_M32: #define __SSSE3__ 1 // CHECK_BROADWELL_M32: #define __XSAVEOPT__ 1 // CHECK_BROADWELL_M32: #define __XSAVE__ 1 // CHECK_BROADWELL_M32: #define __corei7 1 // CHECK_BROADWELL_M32: #define __corei7__ 1 // CHECK_BROADWELL_M32: #define __i386 1 // CHECK_BROADWELL_M32: #define __i386__ 1 // CHECK_BROADWELL_M32: #define __tune_corei7__ 1 // CHECK_BROADWELL_M32: #define i386 1 // RUN: %clang -march=broadwell -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BROADWELL_M64 // CHECK_BROADWELL_M64: #define __ADX__ 1 // CHECK_BROADWELL_M64: #define __AVX2__ 1 // CHECK_BROADWELL_M64: #define __AVX__ 1 // CHECK_BROADWELL_M64: #define __BMI2__ 1 // CHECK_BROADWELL_M64: #define __BMI__ 1 // CHECK_BROADWELL_M64: #define __F16C__ 1 // CHECK_BROADWELL_M64: #define __FMA__ 1 // CHECK_BROADWELL_M64: #define __INVPCID__ 1 // CHECK_BROADWELL_M64: #define __LZCNT__ 1 // CHECK_BROADWELL_M64: #define __MMX__ 1 // CHECK_BROADWELL_M64: #define __MOVBE__ 1 // CHECK_BROADWELL_M64: #define __PCLMUL__ 1 // CHECK_BROADWELL_M64: #define __POPCNT__ 1 // CHECK_BROADWELL_M64: #define __PRFCHW__ 1 // CHECK_BROADWELL_M64: #define __RDRND__ 1 // CHECK_BROADWELL_M64: #define __RDSEED__ 1 // CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1 // CHECK_BROADWELL_M64: #define __SSE2__ 1 // CHECK_BROADWELL_M64: #define __SSE3__ 1 // CHECK_BROADWELL_M64: #define __SSE4_1__ 1 // CHECK_BROADWELL_M64: #define __SSE4_2__ 1 // CHECK_BROADWELL_M64: #define __SSE_MATH__ 1 // CHECK_BROADWELL_M64: #define __SSE__ 1 // CHECK_BROADWELL_M64: #define __SSSE3__ 1 // CHECK_BROADWELL_M64: #define __XSAVEOPT__ 1 // CHECK_BROADWELL_M64: #define __XSAVE__ 1 // CHECK_BROADWELL_M64: #define __amd64 1 // CHECK_BROADWELL_M64: #define __amd64__ 1 // CHECK_BROADWELL_M64: #define __corei7 1 // CHECK_BROADWELL_M64: #define __corei7__ 1 // CHECK_BROADWELL_M64: #define __tune_corei7__ 1 // CHECK_BROADWELL_M64: #define __x86_64 1 // CHECK_BROADWELL_M64: #define __x86_64__ 1 // RUN: %clang -march=skylake -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKL_M32 // CHECK_SKL_M32: #define __ADX__ 1 // CHECK_SKL_M32: #define __AES__ 1 // CHECK_SKL_M32: #define __AVX2__ 1 // CHECK_SKL_M32: #define __AVX__ 1 // CHECK_SKL_M32: #define __BMI2__ 1 // CHECK_SKL_M32: #define __BMI__ 1 // CHECK_SKL_M32: #define __CLFLUSHOPT__ 1 // CHECK_SKL_M32: #define __F16C__ 1 // CHECK_SKL_M32: #define __FMA__ 1 // CHECK_SKL_M32: #define __INVPCID__ 1 // CHECK_SKL_M32: #define __LZCNT__ 1 // CHECK_SKL_M32: #define __MMX__ 1 // CHECK_SKL_M32: #define __MOVBE__ 1 // CHECK_SKL_M32: #define __MPX__ 1 // CHECK_SKL_M32: #define __PCLMUL__ 1 // CHECK_SKL_M32: #define __POPCNT__ 1 // CHECK_SKL_M32: #define __PRFCHW__ 1 // CHECK_SKL_M32: #define __RDRND__ 1 // CHECK_SKL_M32: #define __RDSEED__ 1 // CHECK_SKL_M32: #define __SGX__ 1 // CHECK_SKL_M32: #define __SSE2__ 1 // CHECK_SKL_M32: #define __SSE3__ 1 // CHECK_SKL_M32: #define __SSE4_1__ 1 // CHECK_SKL_M32: #define __SSE4_2__ 1 // CHECK_SKL_M32: #define __SSE__ 1 // CHECK_SKL_M32: #define __SSSE3__ 1 // CHECK_SKL_M32: #define __XSAVEC__ 1 // CHECK_SKL_M32: #define __XSAVEOPT__ 1 // CHECK_SKL_M32: #define __XSAVES__ 1 // CHECK_SKL_M32: #define __XSAVE__ 1 // CHECK_SKL_M32: #define i386 1 // RUN: %clang -march=skylake -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKL_M64 // CHECK_SKL_M64: #define __ADX__ 1 // CHECK_SKL_M64: #define __AES__ 1 // CHECK_SKL_M64: #define __AVX2__ 1 // CHECK_SKL_M64: #define __AVX__ 1 // CHECK_SKL_M64: #define __BMI2__ 1 // CHECK_SKL_M64: #define __BMI__ 1 // CHECK_SKL_M64: #define __CLFLUSHOPT__ 1 // CHECK_SKL_M64: #define __F16C__ 1 // CHECK_SKL_M64: #define __FMA__ 1 // CHECK_SKL_M64: #define __INVPCID__ 1 // CHECK_SKL_M64: #define __LZCNT__ 1 // CHECK_SKL_M64: #define __MMX__ 1 // CHECK_SKL_M64: #define __MOVBE__ 1 // CHECK_SKL_M64: #define __MPX__ 1 // CHECK_SKL_M64: #define __PCLMUL__ 1 // CHECK_SKL_M64: #define __POPCNT__ 1 // CHECK_SKL_M64: #define __PRFCHW__ 1 // CHECK_SKL_M64: #define __RDRND__ 1 // CHECK_SKL_M64: #define __RDSEED__ 1 // CHECK_SKL_M64: #define __SGX__ 1 // CHECK_SKL_M64: #define __SSE2_MATH__ 1 // CHECK_SKL_M64: #define __SSE2__ 1 // CHECK_SKL_M64: #define __SSE3__ 1 // CHECK_SKL_M64: #define __SSE4_1__ 1 // CHECK_SKL_M64: #define __SSE4_2__ 1 // CHECK_SKL_M64: #define __SSE_MATH__ 1 // CHECK_SKL_M64: #define __SSE__ 1 // CHECK_SKL_M64: #define __SSSE3__ 1 // CHECK_SKL_M64: #define __XSAVEC__ 1 // CHECK_SKL_M64: #define __XSAVEOPT__ 1 // CHECK_SKL_M64: #define __XSAVES__ 1 // CHECK_SKL_M64: #define __XSAVE__ 1 // CHECK_SKL_M64: #define __amd64 1 // CHECK_SKL_M64: #define __amd64__ 1 // CHECK_SKL_M64: #define __x86_64 1 // CHECK_SKL_M64: #define __x86_64__ 1 // RUN: %clang -march=knl -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNL_M32 // CHECK_KNL_M32: #define __AES__ 1 // CHECK_KNL_M32: #define __AVX2__ 1 // CHECK_KNL_M32: #define __AVX512CD__ 1 // CHECK_KNL_M32: #define __AVX512ER__ 1 // CHECK_KNL_M32: #define __AVX512F__ 1 // CHECK_KNL_M32: #define __AVX512PF__ 1 // CHECK_KNL_M32: #define __AVX__ 1 // CHECK_KNL_M32: #define __BMI2__ 1 // CHECK_KNL_M32: #define __BMI__ 1 // CHECK_KNL_M32: #define __F16C__ 1 // CHECK_KNL_M32: #define __FMA__ 1 // CHECK_KNL_M32: #define __LZCNT__ 1 // CHECK_KNL_M32: #define __MMX__ 1 // CHECK_KNL_M32: #define __MOVBE__ 1 // CHECK_KNL_M32: #define __PCLMUL__ 1 // CHECK_KNL_M32: #define __POPCNT__ 1 // CHECK_KNL_M32: #define __PREFETCHWT1__ 1 // CHECK_KNL_M32: #define __PRFCHW__ 1 // CHECK_KNL_M32: #define __RDRND__ 1 // CHECK_KNL_M32: #define __SSE2__ 1 // CHECK_KNL_M32: #define __SSE3__ 1 // CHECK_KNL_M32: #define __SSE4_1__ 1 // CHECK_KNL_M32: #define __SSE4_2__ 1 // CHECK_KNL_M32: #define __SSE__ 1 // CHECK_KNL_M32: #define __SSSE3__ 1 // CHECK_KNL_M32: #define __XSAVEOPT__ 1 // CHECK_KNL_M32: #define __XSAVE__ 1 // CHECK_KNL_M32: #define __i386 1 // CHECK_KNL_M32: #define __i386__ 1 // CHECK_KNL_M32: #define __knl 1 // CHECK_KNL_M32: #define __knl__ 1 // CHECK_KNL_M32: #define __tune_knl__ 1 // CHECK_KNL_M32: #define i386 1 // RUN: %clang -march=knl -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNL_M64 // CHECK_KNL_M64: #define __AES__ 1 // CHECK_KNL_M64: #define __AVX2__ 1 // CHECK_KNL_M64: #define __AVX512CD__ 1 // CHECK_KNL_M64: #define __AVX512ER__ 1 // CHECK_KNL_M64: #define __AVX512F__ 1 // CHECK_KNL_M64: #define __AVX512PF__ 1 // CHECK_KNL_M64: #define __AVX__ 1 // CHECK_KNL_M64: #define __BMI2__ 1 // CHECK_KNL_M64: #define __BMI__ 1 // CHECK_KNL_M64: #define __F16C__ 1 // CHECK_KNL_M64: #define __FMA__ 1 // CHECK_KNL_M64: #define __LZCNT__ 1 // CHECK_KNL_M64: #define __MMX__ 1 // CHECK_KNL_M64: #define __MOVBE__ 1 // CHECK_KNL_M64: #define __PCLMUL__ 1 // CHECK_KNL_M64: #define __POPCNT__ 1 // CHECK_KNL_M64: #define __PREFETCHWT1__ 1 // CHECK_KNL_M64: #define __PRFCHW__ 1 // CHECK_KNL_M64: #define __RDRND__ 1 // CHECK_KNL_M64: #define __SSE2_MATH__ 1 // CHECK_KNL_M64: #define __SSE2__ 1 // CHECK_KNL_M64: #define __SSE3__ 1 // CHECK_KNL_M64: #define __SSE4_1__ 1 // CHECK_KNL_M64: #define __SSE4_2__ 1 // CHECK_KNL_M64: #define __SSE_MATH__ 1 // CHECK_KNL_M64: #define __SSE__ 1 // CHECK_KNL_M64: #define __SSSE3__ 1 // CHECK_KNL_M64: #define __XSAVEOPT__ 1 // CHECK_KNL_M64: #define __XSAVE__ 1 // CHECK_KNL_M64: #define __amd64 1 // CHECK_KNL_M64: #define __amd64__ 1 // CHECK_KNL_M64: #define __knl 1 // CHECK_KNL_M64: #define __knl__ 1 // CHECK_KNL_M64: #define __tune_knl__ 1 // CHECK_KNL_M64: #define __x86_64 1 // CHECK_KNL_M64: #define __x86_64__ 1 // RUN: %clang -march=knm -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNM_M32 // CHECK_KNM_M32: #define __AES__ 1 // CHECK_KNM_M32: #define __AVX2__ 1 // CHECK_KNM_M32: #define __AVX512CD__ 1 // CHECK_KNM_M32: #define __AVX512ER__ 1 // CHECK_KNM_M32: #define __AVX512F__ 1 // CHECK_KNM_M32: #define __AVX512PF__ 1 // CHECK_KNM_M32: #define __AVX512VPOPCNTDQ__ 1 // CHECK_KNM_M32: #define __AVX__ 1 // CHECK_KNM_M32: #define __BMI2__ 1 // CHECK_KNM_M32: #define __BMI__ 1 // CHECK_KNM_M32: #define __F16C__ 1 // CHECK_KNM_M32: #define __FMA__ 1 // CHECK_KNM_M32: #define __LZCNT__ 1 // CHECK_KNM_M32: #define __MMX__ 1 // CHECK_KNM_M32: #define __MOVBE__ 1 // CHECK_KNM_M32: #define __PCLMUL__ 1 // CHECK_KNM_M32: #define __POPCNT__ 1 // CHECK_KNM_M32: #define __PREFETCHWT1__ 1 // CHECK_KNM_M32: #define __PRFCHW__ 1 // CHECK_KNM_M32: #define __RDRND__ 1 // CHECK_KNM_M32: #define __SSE2__ 1 // CHECK_KNM_M32: #define __SSE3__ 1 // CHECK_KNM_M32: #define __SSE4_1__ 1 // CHECK_KNM_M32: #define __SSE4_2__ 1 // CHECK_KNM_M32: #define __SSE__ 1 // CHECK_KNM_M32: #define __SSSE3__ 1 // CHECK_KNM_M32: #define __XSAVEOPT__ 1 // CHECK_KNM_M32: #define __XSAVE__ 1 // CHECK_KNM_M32: #define __i386 1 // CHECK_KNM_M32: #define __i386__ 1 // CHECK_KNM_M32: #define i386 1 // RUN: %clang -march=knm -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_KNM_M64 // CHECK_KNM_M64: #define __AES__ 1 // CHECK_KNM_M64: #define __AVX2__ 1 // CHECK_KNM_M64: #define __AVX512CD__ 1 // CHECK_KNM_M64: #define __AVX512ER__ 1 // CHECK_KNM_M64: #define __AVX512F__ 1 // CHECK_KNM_M64: #define __AVX512PF__ 1 // CHECK_KNM_M64: #define __AVX512VPOPCNTDQ__ 1 // CHECK_KNM_M64: #define __AVX__ 1 // CHECK_KNM_M64: #define __BMI2__ 1 // CHECK_KNM_M64: #define __BMI__ 1 // CHECK_KNM_M64: #define __F16C__ 1 // CHECK_KNM_M64: #define __FMA__ 1 // CHECK_KNM_M64: #define __LZCNT__ 1 // CHECK_KNM_M64: #define __MMX__ 1 // CHECK_KNM_M64: #define __MOVBE__ 1 // CHECK_KNM_M64: #define __PCLMUL__ 1 // CHECK_KNM_M64: #define __POPCNT__ 1 // CHECK_KNM_M64: #define __PREFETCHWT1__ 1 // CHECK_KNM_M64: #define __PRFCHW__ 1 // CHECK_KNM_M64: #define __RDRND__ 1 // CHECK_KNM_M64: #define __SSE2_MATH__ 1 // CHECK_KNM_M64: #define __SSE2__ 1 // CHECK_KNM_M64: #define __SSE3__ 1 // CHECK_KNM_M64: #define __SSE4_1__ 1 // CHECK_KNM_M64: #define __SSE4_2__ 1 // CHECK_KNM_M64: #define __SSE_MATH__ 1 // CHECK_KNM_M64: #define __SSE__ 1 // CHECK_KNM_M64: #define __SSSE3__ 1 // CHECK_KNM_M64: #define __XSAVEOPT__ 1 // CHECK_KNM_M64: #define __XSAVE__ 1 // CHECK_KNM_M64: #define __amd64 1 // CHECK_KNM_M64: #define __amd64__ 1 // CHECK_KNM_M64: #define __x86_64 1 // CHECK_KNM_M64: #define __x86_64__ 1 // RUN: %clang -march=skylake-avx512 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKX_M32 // CHECK_SKX_M32: #define __AES__ 1 // CHECK_SKX_M32: #define __AVX2__ 1 // CHECK_SKX_M32: #define __AVX512BW__ 1 // CHECK_SKX_M32: #define __AVX512CD__ 1 // CHECK_SKX_M32: #define __AVX512DQ__ 1 // CHECK_SKX_M32: #define __AVX512F__ 1 // CHECK_SKX_M32: #define __AVX512VL__ 1 // CHECK_SKX_M32: #define __AVX__ 1 // CHECK_SKX_M32: #define __BMI2__ 1 // CHECK_SKX_M32: #define __BMI__ 1 // CHECK_SKX_M32: #define __CLFLUSHOPT__ 1 // CHECK_SKX_M32: #define __CLWB__ 1 // CHECK_SKX_M32: #define __F16C__ 1 // CHECK_SKX_M32: #define __FMA__ 1 // CHECK_SKX_M32: #define __INVPCID__ 1 // CHECK_SKX_M32: #define __LZCNT__ 1 // CHECK_SKX_M32: #define __MMX__ 1 // CHECK_SKX_M32: #define __MOVBE__ 1 // CHECK_SKX_M32: #define __MPX__ 1 // CHECK_SKX_M32: #define __PCLMUL__ 1 // CHECK_SKX_M32: #define __PKU__ 1 // CHECK_SKX_M32: #define __POPCNT__ 1 // CHECK_SKX_M32: #define __PRFCHW__ 1 // CHECK_SKX_M32: #define __RDRND__ 1 // CHECK_SKX_M32: #define __RDSEED__ 1 // CHECK_SKX_M32-NOT: #define __SGX__ 1 // CHECK_SKX_M32: #define __SSE2__ 1 // CHECK_SKX_M32: #define __SSE3__ 1 // CHECK_SKX_M32: #define __SSE4_1__ 1 // CHECK_SKX_M32: #define __SSE4_2__ 1 // CHECK_SKX_M32: #define __SSE__ 1 // CHECK_SKX_M32: #define __SSSE3__ 1 // CHECK_SKX_M32: #define __XSAVEC__ 1 // CHECK_SKX_M32: #define __XSAVEOPT__ 1 // CHECK_SKX_M32: #define __XSAVES__ 1 // CHECK_SKX_M32: #define __XSAVE__ 1 // CHECK_SKX_M32: #define __corei7 1 // CHECK_SKX_M32: #define __corei7__ 1 // CHECK_SKX_M32: #define __i386 1 // CHECK_SKX_M32: #define __i386__ 1 // CHECK_SKX_M32: #define __tune_corei7__ 1 // CHECK_SKX_M32: #define i386 1 // RUN: %clang -march=skylake-avx512 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SKX_M64 // CHECK_SKX_M64: #define __AES__ 1 // CHECK_SKX_M64: #define __AVX2__ 1 // CHECK_SKX_M64: #define __AVX512BW__ 1 // CHECK_SKX_M64: #define __AVX512CD__ 1 // CHECK_SKX_M64: #define __AVX512DQ__ 1 // CHECK_SKX_M64: #define __AVX512F__ 1 // CHECK_SKX_M64: #define __AVX512VL__ 1 // CHECK_SKX_M64: #define __AVX__ 1 // CHECK_SKX_M64: #define __BMI2__ 1 // CHECK_SKX_M64: #define __BMI__ 1 // CHECK_SKX_M64: #define __CLFLUSHOPT__ 1 // CHECK_SKX_M64: #define __CLWB__ 1 // CHECK_SKX_M64: #define __F16C__ 1 // CHECK_SKX_M64: #define __FMA__ 1 // CHECK_SKX_M64: #define __INVPCID__ 1 // CHECK_SKX_M64: #define __LZCNT__ 1 // CHECK_SKX_M64: #define __MMX__ 1 // CHECK_SKX_M64: #define __MOVBE__ 1 // CHECK_SKX_M64: #define __MPX__ 1 // CHECK_SKX_M64: #define __PCLMUL__ 1 // CHECK_SKX_M64: #define __PKU__ 1 // CHECK_SKX_M64: #define __POPCNT__ 1 // CHECK_SKX_M64: #define __PRFCHW__ 1 // CHECK_SKX_M64: #define __RDRND__ 1 // CHECK_SKX_M64: #define __RDSEED__ 1 // CHECK_SKX_M64-NOT: #define __SGX__ 1 // CHECK_SKX_M64: #define __SSE2_MATH__ 1 // CHECK_SKX_M64: #define __SSE2__ 1 // CHECK_SKX_M64: #define __SSE3__ 1 // CHECK_SKX_M64: #define __SSE4_1__ 1 // CHECK_SKX_M64: #define __SSE4_2__ 1 // CHECK_SKX_M64: #define __SSE_MATH__ 1 // CHECK_SKX_M64: #define __SSE__ 1 // CHECK_SKX_M64: #define __SSSE3__ 1 // CHECK_SKX_M64: #define __XSAVEC__ 1 // CHECK_SKX_M64: #define __XSAVEOPT__ 1 // CHECK_SKX_M64: #define __XSAVES__ 1 // CHECK_SKX_M64: #define __XSAVE__ 1 // CHECK_SKX_M64: #define __amd64 1 // CHECK_SKX_M64: #define __amd64__ 1 // CHECK_SKX_M64: #define __corei7 1 // CHECK_SKX_M64: #define __corei7__ 1 // CHECK_SKX_M64: #define __tune_corei7__ 1 // CHECK_SKX_M64: #define __x86_64 1 // CHECK_SKX_M64: #define __x86_64__ 1 // RUN: %clang -march=cascadelake -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M32 // CHECK_CLX_M32: #define __AES__ 1 // CHECK_CLX_M32: #define __AVX2__ 1 // CHECK_CLX_M32: #define __AVX512BW__ 1 // CHECK_CLX_M32: #define __AVX512CD__ 1 // CHECK_CLX_M32: #define __AVX512DQ__ 1 // CHECK_CLX_M32: #define __AVX512F__ 1 // CHECK_CLX_M32: #define __AVX512VL__ 1 // CHECK_CLX_M32: #define __AVX512VNNI__ 1 // CHECK_CLX_M32: #define __AVX__ 1 // CHECK_CLX_M32: #define __BMI2__ 1 // CHECK_CLX_M32: #define __BMI__ 1 // CHECK_CLX_M32: #define __CLFLUSHOPT__ 1 // CHECK_CLX_M32: #define __CLWB__ 1 // CHECK_CLX_M32: #define __F16C__ 1 // CHECK_CLX_M32: #define __FMA__ 1 // CHECK_CLX_M32: #define __INVPCID__ 1 // CHECK_CLX_M32: #define __LZCNT__ 1 // CHECK_CLX_M32: #define __MMX__ 1 // CHECK_CLX_M32: #define __MOVBE__ 1 // CHECK_CLX_M32: #define __MPX__ 1 // CHECK_CLX_M32: #define __PCLMUL__ 1 // CHECK_CLX_M32: #define __PKU__ 1 // CHECK_CLX_M32: #define __POPCNT__ 1 // CHECK_CLX_M32: #define __PRFCHW__ 1 // CHECK_CLX_M32: #define __RDRND__ 1 // CHECK_CLX_M32: #define __RDSEED__ 1 // CHECK_CLX_M32-NOT: #define __SGX__ 1 // CHECK_CLX_M32: #define __SSE2__ 1 // CHECK_CLX_M32: #define __SSE3__ 1 // CHECK_CLX_M32: #define __SSE4_1__ 1 // CHECK_CLX_M32: #define __SSE4_2__ 1 // CHECK_CLX_M32: #define __SSE__ 1 // CHECK_CLX_M32: #define __SSSE3__ 1 // CHECK_CLX_M32: #define __XSAVEC__ 1 // CHECK_CLX_M32: #define __XSAVEOPT__ 1 // CHECK_CLX_M32: #define __XSAVES__ 1 // CHECK_CLX_M32: #define __XSAVE__ 1 // CHECK_CLX_M32: #define __corei7 1 // CHECK_CLX_M32: #define __corei7__ 1 // CHECK_CLX_M32: #define __i386 1 // CHECK_CLX_M32: #define __i386__ 1 // CHECK_CLX_M32: #define __tune_corei7__ 1 // CHECK_CLX_M32: #define i386 1 // RUN: %clang -march=cascadelake -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CLX_M64 // CHECK_CLX_M64: #define __AES__ 1 // CHECK_CLX_M64: #define __AVX2__ 1 // CHECK_CLX_M64: #define __AVX512BW__ 1 // CHECK_CLX_M64: #define __AVX512CD__ 1 // CHECK_CLX_M64: #define __AVX512DQ__ 1 // CHECK_CLX_M64: #define __AVX512F__ 1 // CHECK_CLX_M64: #define __AVX512VL__ 1 // CHECK_CLX_M64: #define __AVX512VNNI__ 1 // CHECK_CLX_M64: #define __AVX__ 1 // CHECK_CLX_M64: #define __BMI2__ 1 // CHECK_CLX_M64: #define __BMI__ 1 // CHECK_CLX_M64: #define __CLFLUSHOPT__ 1 // CHECK_CLX_M64: #define __CLWB__ 1 // CHECK_CLX_M64: #define __F16C__ 1 // CHECK_CLX_M64: #define __FMA__ 1 // CHECK_CLX_M64: #define __INVPCID__ 1 // CHECK_CLX_M64: #define __LZCNT__ 1 // CHECK_CLX_M64: #define __MMX__ 1 // CHECK_CLX_M64: #define __MOVBE__ 1 // CHECK_CLX_M64: #define __MPX__ 1 // CHECK_CLX_M64: #define __PCLMUL__ 1 // CHECK_CLX_M64: #define __PKU__ 1 // CHECK_CLX_M64: #define __POPCNT__ 1 // CHECK_CLX_M64: #define __PRFCHW__ 1 // CHECK_CLX_M64: #define __RDRND__ 1 // CHECK_CLX_M64: #define __RDSEED__ 1 // CHECK_CLX_M64-NOT: #define __SGX__ 1 // CHECK_CLX_M64: #define __SSE2_MATH__ 1 // CHECK_CLX_M64: #define __SSE2__ 1 // CHECK_CLX_M64: #define __SSE3__ 1 // CHECK_CLX_M64: #define __SSE4_1__ 1 // CHECK_CLX_M64: #define __SSE4_2__ 1 // CHECK_CLX_M64: #define __SSE_MATH__ 1 // CHECK_CLX_M64: #define __SSE__ 1 // CHECK_CLX_M64: #define __SSSE3__ 1 // CHECK_CLX_M64: #define __XSAVEC__ 1 // CHECK_CLX_M64: #define __XSAVEOPT__ 1 // CHECK_CLX_M64: #define __XSAVES__ 1 // CHECK_CLX_M64: #define __XSAVE__ 1 // CHECK_CLX_M64: #define __amd64 1 // CHECK_CLX_M64: #define __amd64__ 1 // CHECK_CLX_M64: #define __corei7 1 // CHECK_CLX_M64: #define __corei7__ 1 // CHECK_CLX_M64: #define __tune_corei7__ 1 // CHECK_CLX_M64: #define __x86_64 1 // CHECK_CLX_M64: #define __x86_64__ 1 // RUN: %clang -march=cooperlake -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CPX_M32 // CHECK_CPX_M32: #define __AES__ 1 // CHECK_CPX_M32: #define __AVX2__ 1 // CHECK_CPX_M32: #define __AVX512BF16__ 1 // CHECK_CPX_M32: #define __AVX512BW__ 1 // CHECK_CPX_M32: #define __AVX512CD__ 1 // CHECK_CPX_M32: #define __AVX512DQ__ 1 // CHECK_CPX_M32: #define __AVX512F__ 1 // CHECK_CPX_M32: #define __AVX512VL__ 1 // CHECK_CPX_M32: #define __AVX512VNNI__ 1 // CHECK_CPX_M32: #define __AVX__ 1 // CHECK_CPX_M32: #define __BMI2__ 1 // CHECK_CPX_M32: #define __BMI__ 1 // CHECK_CPX_M32: #define __CLFLUSHOPT__ 1 // CHECK_CPX_M32: #define __CLWB__ 1 // CHECK_CPX_M32: #define __F16C__ 1 // CHECK_CPX_M32: #define __FMA__ 1 // CHECK_CPX_M32: #define __INVPCID__ 1 // CHECK_CPX_M32: #define __LZCNT__ 1 // CHECK_CPX_M32: #define __MMX__ 1 // CHECK_CPX_M32: #define __MOVBE__ 1 // CHECK_CPX_M32: #define __MPX__ 1 // CHECK_CPX_M32: #define __PCLMUL__ 1 // CHECK_CPX_M32: #define __PKU__ 1 // CHECK_CPX_M32: #define __POPCNT__ 1 // CHECK_CPX_M32: #define __PRFCHW__ 1 // CHECK_CPX_M32: #define __RDRND__ 1 // CHECK_CPX_M32: #define __RDSEED__ 1 // CHECK_CPX_M32-NOT: #define __SGX__ 1 // CHECK_CPX_M32: #define __SSE2__ 1 // CHECK_CPX_M32: #define __SSE3__ 1 // CHECK_CPX_M32: #define __SSE4_1__ 1 // CHECK_CPX_M32: #define __SSE4_2__ 1 // CHECK_CPX_M32: #define __SSE__ 1 // CHECK_CPX_M32: #define __SSSE3__ 1 // CHECK_CPX_M32: #define __XSAVEC__ 1 // CHECK_CPX_M32: #define __XSAVEOPT__ 1 // CHECK_CPX_M32: #define __XSAVES__ 1 // CHECK_CPX_M32: #define __XSAVE__ 1 // CHECK_CPX_M32: #define __corei7 1 // CHECK_CPX_M32: #define __corei7__ 1 // CHECK_CPX_M32: #define __i386 1 // CHECK_CPX_M32: #define __i386__ 1 // CHECK_CPX_M32: #define __tune_corei7__ 1 // CHECK_CPX_M32: #define i386 1 // RUN: %clang -march=cooperlake -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CPX_M64 // CHECK_CPX_M64: #define __AES__ 1 // CHECK_CPX_M64: #define __AVX2__ 1 // CHECK_CPX_M64: #define __AVX512BF16__ 1 // CHECK_CPX_M64: #define __AVX512BW__ 1 // CHECK_CPX_M64: #define __AVX512CD__ 1 // CHECK_CPX_M64: #define __AVX512DQ__ 1 // CHECK_CPX_M64: #define __AVX512F__ 1 // CHECK_CPX_M64: #define __AVX512VL__ 1 // CHECK_CPX_M64: #define __AVX512VNNI__ 1 // CHECK_CPX_M64: #define __AVX__ 1 // CHECK_CPX_M64: #define __BMI2__ 1 // CHECK_CPX_M64: #define __BMI__ 1 // CHECK_CPX_M64: #define __CLFLUSHOPT__ 1 // CHECK_CPX_M64: #define __CLWB__ 1 // CHECK_CPX_M64: #define __F16C__ 1 // CHECK_CPX_M64: #define __FMA__ 1 // CHECK_CPX_M64: #define __INVPCID__ 1 // CHECK_CPX_M64: #define __LZCNT__ 1 // CHECK_CPX_M64: #define __MMX__ 1 // CHECK_CPX_M64: #define __MOVBE__ 1 // CHECK_CPX_M64: #define __MPX__ 1 // CHECK_CPX_M64: #define __PCLMUL__ 1 // CHECK_CPX_M64: #define __PKU__ 1 // CHECK_CPX_M64: #define __POPCNT__ 1 // CHECK_CPX_M64: #define __PRFCHW__ 1 // CHECK_CPX_M64: #define __RDRND__ 1 // CHECK_CPX_M64: #define __RDSEED__ 1 // CHECK_CPX_M64-NOT: #define __SGX__ 1 // CHECK_CPX_M64: #define __SSE2_MATH__ 1 // CHECK_CPX_M64: #define __SSE2__ 1 // CHECK_CPX_M64: #define __SSE3__ 1 // CHECK_CPX_M64: #define __SSE4_1__ 1 // CHECK_CPX_M64: #define __SSE4_2__ 1 // CHECK_CPX_M64: #define __SSE_MATH__ 1 // CHECK_CPX_M64: #define __SSE__ 1 // CHECK_CPX_M64: #define __SSSE3__ 1 // CHECK_CPX_M64: #define __XSAVEC__ 1 // CHECK_CPX_M64: #define __XSAVEOPT__ 1 // CHECK_CPX_M64: #define __XSAVES__ 1 // CHECK_CPX_M64: #define __XSAVE__ 1 // CHECK_CPX_M64: #define __amd64 1 // CHECK_CPX_M64: #define __amd64__ 1 // CHECK_CPX_M64: #define __corei7 1 // CHECK_CPX_M64: #define __corei7__ 1 // CHECK_CPX_M64: #define __tune_corei7__ 1 // CHECK_CPX_M64: #define __x86_64 1 // CHECK_CPX_M64: #define __x86_64__ 1 // RUN: %clang -march=cannonlake -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CNL_M32 // CHECK_CNL_M32: #define __AES__ 1 // CHECK_CNL_M32: #define __AVX2__ 1 // CHECK_CNL_M32: #define __AVX512BW__ 1 // CHECK_CNL_M32: #define __AVX512CD__ 1 // CHECK_CNL_M32: #define __AVX512DQ__ 1 // CHECK_CNL_M32: #define __AVX512F__ 1 // CHECK_CNL_M32: #define __AVX512IFMA__ 1 // CHECK_CNL_M32: #define __AVX512VBMI__ 1 // CHECK_CNL_M32: #define __AVX512VL__ 1 // CHECK_CNL_M32: #define __AVX__ 1 // CHECK_CNL_M32: #define __BMI2__ 1 // CHECK_CNL_M32: #define __BMI__ 1 // CHECK_CNL_M32: #define __CLFLUSHOPT__ 1 // CHECK_CNL_M32-NOT: #define __CLWB__ 1 // CHECK_CNL_M32: #define __F16C__ 1 // CHECK_CNL_M32: #define __FMA__ 1 // CHECK_CNL_M32: #define __INVPCID__ 1 // CHECK_CNL_M32: #define __LZCNT__ 1 // CHECK_CNL_M32: #define __MMX__ 1 // CHECK_CNL_M32: #define __MOVBE__ 1 // CHECK_CNL_M32: #define __MPX__ 1 // CHECK_CNL_M32: #define __PCLMUL__ 1 // CHECK_CNL_M32: #define __PKU__ 1 // CHECK_CNL_M32: #define __POPCNT__ 1 // CHECK_CNL_M32: #define __PRFCHW__ 1 // CHECK_CNL_M32: #define __RDRND__ 1 // CHECK_CNL_M32: #define __RDSEED__ 1 // CHECK_CNL_M32: #define __SGX__ 1 // CHECK_CNL_M32: #define __SHA__ 1 // CHECK_CNL_M32: #define __SSE2__ 1 // CHECK_CNL_M32: #define __SSE3__ 1 // CHECK_CNL_M32: #define __SSE4_1__ 1 // CHECK_CNL_M32: #define __SSE4_2__ 1 // CHECK_CNL_M32: #define __SSE__ 1 // CHECK_CNL_M32: #define __SSSE3__ 1 // CHECK_CNL_M32: #define __XSAVEC__ 1 // CHECK_CNL_M32: #define __XSAVEOPT__ 1 // CHECK_CNL_M32: #define __XSAVES__ 1 // CHECK_CNL_M32: #define __XSAVE__ 1 // CHECK_CNL_M32: #define __corei7 1 // CHECK_CNL_M32: #define __corei7__ 1 // CHECK_CNL_M32: #define __i386 1 // CHECK_CNL_M32: #define __i386__ 1 // CHECK_CNL_M32: #define __tune_corei7__ 1 // CHECK_CNL_M32: #define i386 1 // RUN: %clang -march=cannonlake -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_CNL_M64 // CHECK_CNL_M64: #define __AES__ 1 // CHECK_CNL_M64: #define __AVX2__ 1 // CHECK_CNL_M64: #define __AVX512BW__ 1 // CHECK_CNL_M64: #define __AVX512CD__ 1 // CHECK_CNL_M64: #define __AVX512DQ__ 1 // CHECK_CNL_M64: #define __AVX512F__ 1 // CHECK_CNL_M64: #define __AVX512IFMA__ 1 // CHECK_CNL_M64: #define __AVX512VBMI__ 1 // CHECK_CNL_M64: #define __AVX512VL__ 1 // CHECK_CNL_M64: #define __AVX__ 1 // CHECK_CNL_M64: #define __BMI2__ 1 // CHECK_CNL_M64: #define __BMI__ 1 // CHECK_CNL_M64: #define __CLFLUSHOPT__ 1 // CHECK_CNL_M64-NOT: #define __CLWB__ 1 // CHECK_CNL_M64: #define __F16C__ 1 // CHECK_CNL_M64: #define __FMA__ 1 // CHECK_CNL_M64: #define __INVPCID__ 1 // CHECK_CNL_M64: #define __LZCNT__ 1 // CHECK_CNL_M64: #define __MMX__ 1 // CHECK_CNL_M64: #define __MOVBE__ 1 // CHECK_CNL_M64: #define __MPX__ 1 // CHECK_CNL_M64: #define __PCLMUL__ 1 // CHECK_CNL_M64: #define __PKU__ 1 // CHECK_CNL_M64: #define __POPCNT__ 1 // CHECK_CNL_M64: #define __PRFCHW__ 1 // CHECK_CNL_M64: #define __RDRND__ 1 // CHECK_CNL_M64: #define __RDSEED__ 1 // CHECK_CNL_M64: #define __SGX__ 1 // CHECK_CNL_M64: #define __SHA__ 1 // CHECK_CNL_M64: #define __SSE2__ 1 // CHECK_CNL_M64: #define __SSE3__ 1 // CHECK_CNL_M64: #define __SSE4_1__ 1 // CHECK_CNL_M64: #define __SSE4_2__ 1 // CHECK_CNL_M64: #define __SSE__ 1 // CHECK_CNL_M64: #define __SSSE3__ 1 // CHECK_CNL_M64: #define __XSAVEC__ 1 // CHECK_CNL_M64: #define __XSAVEOPT__ 1 // CHECK_CNL_M64: #define __XSAVES__ 1 // CHECK_CNL_M64: #define __XSAVE__ 1 // CHECK_CNL_M64: #define __amd64 1 // CHECK_CNL_M64: #define __amd64__ 1 // CHECK_CNL_M64: #define __corei7 1 // CHECK_CNL_M64: #define __corei7__ 1 // CHECK_CNL_M64: #define __tune_corei7__ 1 // CHECK_CNL_M64: #define __x86_64 1 // CHECK_CNL_M64: #define __x86_64__ 1 // RUN: %clang -march=icelake-client -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M32 // CHECK_ICL_M32: #define __AES__ 1 // CHECK_ICL_M32: #define __AVX2__ 1 // CHECK_ICL_M32: #define __AVX512BITALG__ 1 // CHECK_ICL_M32: #define __AVX512BW__ 1 // CHECK_ICL_M32: #define __AVX512CD__ 1 // CHECK_ICL_M32: #define __AVX512DQ__ 1 // CHECK_ICL_M32: #define __AVX512F__ 1 // CHECK_ICL_M32: #define __AVX512IFMA__ 1 // CHECK_ICL_M32: #define __AVX512VBMI2__ 1 // CHECK_ICL_M32: #define __AVX512VBMI__ 1 // CHECK_ICL_M32: #define __AVX512VL__ 1 // CHECK_ICL_M32: #define __AVX512VNNI__ 1 // CHECK_ICL_M32: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M32: #define __AVX__ 1 // CHECK_ICL_M32: #define __BMI2__ 1 // CHECK_ICL_M32: #define __BMI__ 1 // CHECK_ICL_M32: #define __CLFLUSHOPT__ 1 // CHECK_ICL_M32: #define __CLWB__ 1 // CHECK_ICL_M32: #define __F16C__ 1 // CHECK_ICL_M32: #define __FMA__ 1 // CHECK_ICL_M32: #define __GFNI__ 1 // CHECK_ICL_M32: #define __INVPCID__ 1 // CHECK_ICL_M32: #define __LZCNT__ 1 // CHECK_ICL_M32: #define __MMX__ 1 // CHECK_ICL_M32: #define __MOVBE__ 1 // CHECK_ICL_M32: #define __MPX__ 1 // CHECK_ICL_M32: #define __PCLMUL__ 1 // CHECK_ICL_M32: #define __PKU__ 1 // CHECK_ICL_M32: #define __POPCNT__ 1 // CHECK_ICL_M32: #define __PRFCHW__ 1 // CHECK_ICL_M32: #define __RDPID__ 1 // CHECK_ICL_M32: #define __RDRND__ 1 // CHECK_ICL_M32: #define __RDSEED__ 1 // CHECK_ICL_M32: #define __SGX__ 1 // CHECK_ICL_M32: #define __SHA__ 1 // CHECK_ICL_M32: #define __SSE2__ 1 // CHECK_ICL_M32: #define __SSE3__ 1 // CHECK_ICL_M32: #define __SSE4_1__ 1 // CHECK_ICL_M32: #define __SSE4_2__ 1 // CHECK_ICL_M32: #define __SSE__ 1 // CHECK_ICL_M32: #define __SSSE3__ 1 // CHECK_ICL_M32: #define __VAES__ 1 // CHECK_ICL_M32: #define __VPCLMULQDQ__ 1 // CHECK_ICL_M32-NOT: #define __WBNOINVD__ 1 // CHECK_ICL_M32: #define __XSAVEC__ 1 // CHECK_ICL_M32: #define __XSAVEOPT__ 1 // CHECK_ICL_M32: #define __XSAVES__ 1 // CHECK_ICL_M32: #define __XSAVE__ 1 // CHECK_ICL_M32: #define __corei7 1 // CHECK_ICL_M32: #define __corei7__ 1 // CHECK_ICL_M32: #define __i386 1 // CHECK_ICL_M32: #define __i386__ 1 // CHECK_ICL_M32: #define __tune_corei7__ 1 // CHECK_ICL_M32: #define i386 1 // RUN: %clang -march=icelake-client -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICL_M64 // CHECK_ICL_M64: #define __AES__ 1 // CHECK_ICL_M64: #define __AVX2__ 1 // CHECK_ICL_M64: #define __AVX512BITALG__ 1 // CHECK_ICL_M64: #define __AVX512BW__ 1 // CHECK_ICL_M64: #define __AVX512CD__ 1 // CHECK_ICL_M64: #define __AVX512DQ__ 1 // CHECK_ICL_M64: #define __AVX512F__ 1 // CHECK_ICL_M64: #define __AVX512IFMA__ 1 // CHECK_ICL_M64: #define __AVX512VBMI2__ 1 // CHECK_ICL_M64: #define __AVX512VBMI__ 1 // CHECK_ICL_M64: #define __AVX512VL__ 1 // CHECK_ICL_M64: #define __AVX512VNNI__ 1 // CHECK_ICL_M64: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M64: #define __AVX__ 1 // CHECK_ICL_M64: #define __BMI2__ 1 // CHECK_ICL_M64: #define __BMI__ 1 // CHECK_ICL_M64: #define __CLFLUSHOPT__ 1 // CHECK_ICL_M64: #define __CLWB__ 1 // CHECK_ICL_M64: #define __F16C__ 1 // CHECK_ICL_M64: #define __FMA__ 1 // CHECK_ICL_M64: #define __GFNI__ 1 // CHECK_ICL_M64: #define __INVPCID__ 1 // CHECK_ICL_M64: #define __LZCNT__ 1 // CHECK_ICL_M64: #define __MMX__ 1 // CHECK_ICL_M64: #define __MOVBE__ 1 // CHECK_ICL_M64: #define __MPX__ 1 // CHECK_ICL_M64: #define __PCLMUL__ 1 // CHECK_ICL_M64: #define __PKU__ 1 // CHECK_ICL_M64: #define __POPCNT__ 1 // CHECK_ICL_M64: #define __PRFCHW__ 1 // CHECK_ICL_M64: #define __RDPID__ 1 // CHECK_ICL_M64: #define __RDRND__ 1 // CHECK_ICL_M64: #define __RDSEED__ 1 // CHECK_ICL_M64: #define __SGX__ 1 // CHECK_ICL_M64: #define __SHA__ 1 // CHECK_ICL_M64: #define __SSE2__ 1 // CHECK_ICL_M64: #define __SSE3__ 1 // CHECK_ICL_M64: #define __SSE4_1__ 1 // CHECK_ICL_M64: #define __SSE4_2__ 1 // CHECK_ICL_M64: #define __SSE__ 1 // CHECK_ICL_M64: #define __SSSE3__ 1 // CHECK_ICL_M64: #define __VAES__ 1 // CHECK_ICL_M64: #define __VPCLMULQDQ__ 1 // CHECK_ICL_M64-NOT: #define __WBNOINVD__ 1 // CHECK_ICL_M64: #define __XSAVEC__ 1 // CHECK_ICL_M64: #define __XSAVEOPT__ 1 // CHECK_ICL_M64: #define __XSAVES__ 1 // CHECK_ICL_M64: #define __XSAVE__ 1 // CHECK_ICL_M64: #define __amd64 1 // CHECK_ICL_M64: #define __amd64__ 1 // CHECK_ICL_M64: #define __corei7 1 // CHECK_ICL_M64: #define __corei7__ 1 // CHECK_ICL_M64: #define __tune_corei7__ 1 // CHECK_ICL_M64: #define __x86_64 1 // CHECK_ICL_M64: #define __x86_64__ 1 // RUN: %clang -march=icelake-server -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICX_M32 // CHECK_ICX_M32: #define __AES__ 1 // CHECK_ICX_M32: #define __AVX2__ 1 // CHECK_ICX_M32: #define __AVX512BITALG__ 1 // CHECK_ICX_M32: #define __AVX512BW__ 1 // CHECK_ICX_M32: #define __AVX512CD__ 1 // CHECK_ICX_M32: #define __AVX512DQ__ 1 // CHECK_ICX_M32: #define __AVX512F__ 1 // CHECK_ICX_M32: #define __AVX512IFMA__ 1 // CHECK_ICX_M32: #define __AVX512VBMI2__ 1 // CHECK_ICX_M32: #define __AVX512VBMI__ 1 // CHECK_ICX_M32: #define __AVX512VL__ 1 // CHECK_ICX_M32: #define __AVX512VNNI__ 1 // CHECK_ICX_M32: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICX_M32: #define __AVX__ 1 // CHECK_ICX_M32: #define __BMI2__ 1 // CHECK_ICX_M32: #define __BMI__ 1 // CHECK_ICX_M32: #define __CLFLUSHOPT__ 1 // CHECK_ICX_M32: #define __CLWB__ 1 // CHECK_ICX_M32: #define __F16C__ 1 // CHECK_ICX_M32: #define __FMA__ 1 // CHECK_ICX_M32: #define __GFNI__ 1 // CHECK_ICX_M32: #define __INVPCID__ 1 // CHECK_ICX_M32: #define __LZCNT__ 1 // CHECK_ICX_M32: #define __MMX__ 1 // CHECK_ICX_M32: #define __MOVBE__ 1 // CHECK_ICX_M32: #define __MPX__ 1 // CHECK_ICX_M32: #define __PCLMUL__ 1 // CHECK_ICX_M32: #define __PCONFIG__ 1 // CHECK_ICX_M32: #define __PKU__ 1 // CHECK_ICX_M32: #define __POPCNT__ 1 // CHECK_ICX_M32: #define __PRFCHW__ 1 // CHECK_ICX_M32: #define __RDPID__ 1 // CHECK_ICX_M32: #define __RDRND__ 1 // CHECK_ICX_M32: #define __RDSEED__ 1 // CHECK_ICX_M32: #define __SGX__ 1 // CHECK_ICX_M32: #define __SHA__ 1 // CHECK_ICX_M32: #define __SSE2__ 1 // CHECK_ICX_M32: #define __SSE3__ 1 // CHECK_ICX_M32: #define __SSE4_1__ 1 // CHECK_ICX_M32: #define __SSE4_2__ 1 // CHECK_ICX_M32: #define __SSE__ 1 // CHECK_ICX_M32: #define __SSSE3__ 1 // CHECK_ICX_M32: #define __VAES__ 1 // CHECK_ICX_M32: #define __VPCLMULQDQ__ 1 // CHECK_ICX_M32: #define __WBNOINVD__ 1 // CHECK_ICX_M32: #define __XSAVEC__ 1 // CHECK_ICX_M32: #define __XSAVEOPT__ 1 // CHECK_ICX_M32: #define __XSAVES__ 1 // CHECK_ICX_M32: #define __XSAVE__ 1 // CHECK_ICX_M32: #define __corei7 1 // CHECK_ICX_M32: #define __corei7__ 1 // CHECK_ICX_M32: #define __i386 1 // CHECK_ICX_M32: #define __i386__ 1 // CHECK_ICX_M32: #define __tune_corei7__ 1 // CHECK_ICX_M32: #define i386 1 // RUN: %clang -march=icelake-server -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ICX_M64 // CHECK_ICX_M64: #define __AES__ 1 // CHECK_ICX_M64: #define __AVX2__ 1 // CHECK_ICX_M64: #define __AVX512BITALG__ 1 // CHECK_ICX_M64: #define __AVX512BW__ 1 // CHECK_ICX_M64: #define __AVX512CD__ 1 // CHECK_ICX_M64: #define __AVX512DQ__ 1 // CHECK_ICX_M64: #define __AVX512F__ 1 // CHECK_ICX_M64: #define __AVX512IFMA__ 1 // CHECK_ICX_M64: #define __AVX512VBMI2__ 1 // CHECK_ICX_M64: #define __AVX512VBMI__ 1 // CHECK_ICX_M64: #define __AVX512VL__ 1 // CHECK_ICX_M64: #define __AVX512VNNI__ 1 // CHECK_ICX_M64: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICX_M64: #define __AVX__ 1 // CHECK_ICX_M64: #define __BMI2__ 1 // CHECK_ICX_M64: #define __BMI__ 1 // CHECK_ICX_M64: #define __CLFLUSHOPT__ 1 // CHECK_ICX_M64: #define __CLWB__ 1 // CHECK_ICX_M64: #define __F16C__ 1 // CHECK_ICX_M64: #define __FMA__ 1 // CHECK_ICX_M64: #define __GFNI__ 1 // CHECK_ICX_M64: #define __INVPCID__ 1 // CHECK_ICX_M64: #define __LZCNT__ 1 // CHECK_ICX_M64: #define __MMX__ 1 // CHECK_ICX_M64: #define __MOVBE__ 1 // CHECK_ICX_M64: #define __MPX__ 1 // CHECK_ICX_M64: #define __PCLMUL__ 1 // CHECK_ICX_M64: #define __PCONFIG__ 1 // CHECK_ICX_M64: #define __PKU__ 1 // CHECK_ICX_M64: #define __POPCNT__ 1 // CHECK_ICX_M64: #define __PRFCHW__ 1 // CHECK_ICX_M64: #define __RDPID__ 1 // CHECK_ICX_M64: #define __RDRND__ 1 // CHECK_ICX_M64: #define __RDSEED__ 1 // CHECK_ICX_M64: #define __SGX__ 1 // CHECK_ICX_M64: #define __SHA__ 1 // CHECK_ICX_M64: #define __SSE2__ 1 // CHECK_ICX_M64: #define __SSE3__ 1 // CHECK_ICX_M64: #define __SSE4_1__ 1 // CHECK_ICX_M64: #define __SSE4_2__ 1 // CHECK_ICX_M64: #define __SSE__ 1 // CHECK_ICX_M64: #define __SSSE3__ 1 // CHECK_ICX_M64: #define __VAES__ 1 // CHECK_ICX_M64: #define __VPCLMULQDQ__ 1 // CHECK_ICX_M64: #define __WBNOINVD__ 1 // CHECK_ICX_M64: #define __XSAVEC__ 1 // CHECK_ICX_M64: #define __XSAVEOPT__ 1 // CHECK_ICX_M64: #define __XSAVES__ 1 // CHECK_ICX_M64: #define __XSAVE__ 1 // CHECK_ICX_M64: #define __amd64 1 // CHECK_ICX_M64: #define __amd64__ 1 // CHECK_ICX_M64: #define __corei7 1 // CHECK_ICX_M64: #define __corei7__ 1 // CHECK_ICX_M64: #define __tune_corei7__ 1 // CHECK_ICX_M64: #define __x86_64 1 // CHECK_ICX_M64: #define __x86_64__ 1 +// RUN: %clang -march=tigerlake -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M32 +// CHECK_TGL_M32: #define __AES__ 1 +// CHECK_TGL_M32: #define __AVX2__ 1 +// CHECK_TGL_M32: #define __AVX512BITALG__ 1 +// CHECK_TGL_M32: #define __AVX512BW__ 1 +// CHECK_TGL_M32: #define __AVX512CD__ 1 +// CHECK_TGL_M32: #define __AVX512DQ__ 1 +// CHECK_TGL_M32: #define __AVX512F__ 1 +// CHECK_TGL_M32: #define __AVX512IFMA__ 1 +// CHECK_TGL_M32: #define __AVX512VBMI2__ 1 +// CHECK_TGL_M32: #define __AVX512VBMI__ 1 +// CHECK_TGL_M32: #define __AVX512VL__ 1 +// CHECK_TGL_M32: #define __AVX512VNNI__ 1 +// CHECK_TGL_M32: #define __AVX512VP2INTERSECT__ 1 +// CHECK_TGL_M32: #define __AVX512VPOPCNTDQ__ 1 +// CHECK_TGL_M32: #define __AVX__ 1 +// CHECK_TGL_M32: #define __BMI2__ 1 +// CHECK_TGL_M32: #define __BMI__ 1 +// CHECK_TGL_M32: #define __CLFLUSHOPT__ 1 +// CHECK_TGL_M32: #define __CLWB__ 1 +// CHECK_TGL_M32: #define __F16C__ 1 +// CHECK_TGL_M32: #define __FMA__ 1 +// CHECK_TGL_M32: #define __GFNI__ 1 +// CHECK_TGL_M32: #define __INVPCID__ 1 +// CHECK_TGL_M32: #define __LZCNT__ 1 +// CHECK_TGL_M32: #define __MMX__ 1 +// CHECK_TGL_M32: #define __MOVBE__ 1 +// CHECK_TGL_M32: #define __MOVDIR64B__ 1 +// CHECK_TGL_M32: #define __MOVDIRI__ 1 +// CHECK_TGL_M32: #define __MPX__ 1 +// CHECK_TGL_M32: #define __PCLMUL__ 1 +// CHECK_TGL_M32-NOT: #define __PCONFIG__ 1 +// CHECK_TGL_M32: #define __PKU__ 1 +// CHECK_TGL_M32: #define __POPCNT__ 1 +// CHECK_TGL_M32: #define __PRFCHW__ 1 +// CHECK_TGL_M32: #define __RDPID__ 1 +// CHECK_TGL_M32: #define __RDRND__ 1 +// CHECK_TGL_M32: #define __RDSEED__ 1 +// CHECK_TGL_M32: #define __SGX__ 1 +// CHECK_TGL_M32: #define __SHA__ 1 +// CHECK_TGL_M32: #define __SHSTK__ 1 +// CHECK_TGL_M32: #define __SSE2__ 1 +// CHECK_TGL_M32: #define __SSE3__ 1 +// CHECK_TGL_M32: #define __SSE4_1__ 1 +// CHECK_TGL_M32: #define __SSE4_2__ 1 +// CHECK_TGL_M32: #define __SSE__ 1 +// CHECK_TGL_M32: #define __SSSE3__ 1 +// CHECK_TGL_M32: #define __VAES__ 1 +// CHECK_TGL_M32: #define __VPCLMULQDQ__ 1 +// CHECK_TGL_M32-NOT: #define __WBNOINVD__ 1 +// CHECK_TGL_M32: #define __XSAVEC__ 1 +// CHECK_TGL_M32: #define __XSAVEOPT__ 1 +// CHECK_TGL_M32: #define __XSAVES__ 1 +// CHECK_TGL_M32: #define __XSAVE__ 1 +// CHECK_TGL_M32: #define __corei7 1 +// CHECK_TGL_M32: #define __corei7__ 1 +// CHECK_TGL_M32: #define __i386 1 +// CHECK_TGL_M32: #define __i386__ 1 +// CHECK_TGL_M32: #define __tune_corei7__ 1 +// CHECK_TGL_M32: #define i386 1 + +// RUN: %clang -march=tigerlake -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_TGL_M64 +// CHECK_TGL_M64: #define __AES__ 1 +// CHECK_TGL_M64: #define __AVX2__ 1 +// CHECK_TGL_M64: #define __AVX512BITALG__ 1 +// CHECK_TGL_M64: #define __AVX512BW__ 1 +// CHECK_TGL_M64: #define __AVX512CD__ 1 +// CHECK_TGL_M64: #define __AVX512DQ__ 1 +// CHECK_TGL_M64: #define __AVX512F__ 1 +// CHECK_TGL_M64: #define __AVX512IFMA__ 1 +// CHECK_TGL_M64: #define __AVX512VBMI2__ 1 +// CHECK_TGL_M64: #define __AVX512VBMI__ 1 +// CHECK_TGL_M64: #define __AVX512VL__ 1 +// CHECK_TGL_M64: #define __AVX512VNNI__ 1 +// CHECK_TGL_M64: #define __AVX512VP2INTERSECT__ 1 +// CHECK_TGL_M64: #define __AVX512VPOPCNTDQ__ 1 +// CHECK_TGL_M64: #define __AVX__ 1 +// CHECK_TGL_M64: #define __BMI2__ 1 +// CHECK_TGL_M64: #define __BMI__ 1 +// CHECK_TGL_M64: #define __CLFLUSHOPT__ 1 +// CHECK_TGL_M64: #define __CLWB__ 1 +// CHECK_TGL_M64: #define __F16C__ 1 +// CHECK_TGL_M64: #define __FMA__ 1 +// CHECK_TGL_M64: #define __GFNI__ 1 +// CHECK_TGL_M64: #define __INVPCID__ 1 +// CHECK_TGL_M64: #define __LZCNT__ 1 +// CHECK_TGL_M64: #define __MMX__ 1 +// CHECK_TGL_M64: #define __MOVBE__ 1 +// CHECK_TGL_M64: #define __MOVDIR64B__ 1 +// CHECK_TGL_M64: #define __MOVDIRI__ 1 +// CHECK_TGL_M64: #define __MPX__ 1 +// CHECK_TGL_M64: #define __PCLMUL__ 1 +// CHECK_TGL_M64-NOT: #define __PCONFIG__ 1 +// CHECK_TGL_M64: #define __PKU__ 1 +// CHECK_TGL_M64: #define __POPCNT__ 1 +// CHECK_TGL_M64: #define __PRFCHW__ 1 +// CHECK_TGL_M64: #define __RDPID__ 1 +// CHECK_TGL_M64: #define __RDRND__ 1 +// CHECK_TGL_M64: #define __RDSEED__ 1 +// CHECK_TGL_M64: #define __SGX__ 1 +// CHECK_TGL_M64: #define __SHA__ 1 +// CHECK_TGL_M64: #define __SHSTK__ 1 +// CHECK_TGL_M64: #define __SSE2__ 1 +// CHECK_TGL_M64: #define __SSE3__ 1 +// CHECK_TGL_M64: #define __SSE4_1__ 1 +// CHECK_TGL_M64: #define __SSE4_2__ 1 +// CHECK_TGL_M64: #define __SSE__ 1 +// CHECK_TGL_M64: #define __SSSE3__ 1 +// CHECK_TGL_M64: #define __VAES__ 1 +// CHECK_TGL_M64: #define __VPCLMULQDQ__ 1 +// CHECK_TGL_M64-NOT: #define __WBNOINVD__ 1 +// CHECK_TGL_M64: #define __XSAVEC__ 1 +// CHECK_TGL_M64: #define __XSAVEOPT__ 1 +// CHECK_TGL_M64: #define __XSAVES__ 1 +// CHECK_TGL_M64: #define __XSAVE__ 1 +// CHECK_TGL_M64: #define __amd64 1 +// CHECK_TGL_M64: #define __amd64__ 1 +// CHECK_TGL_M64: #define __corei7 1 +// CHECK_TGL_M64: #define __corei7__ 1 +// CHECK_TGL_M64: #define __tune_corei7__ 1 +// CHECK_TGL_M64: #define __x86_64 1 +// CHECK_TGL_M64: #define __x86_64__ 1 + // RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32 // CHECK_ATOM_M32: #define __MMX__ 1 // CHECK_ATOM_M32: #define __MOVBE__ 1 // CHECK_ATOM_M32: #define __SSE2__ 1 // CHECK_ATOM_M32: #define __SSE3__ 1 // CHECK_ATOM_M32: #define __SSE__ 1 // CHECK_ATOM_M32: #define __SSSE3__ 1 // CHECK_ATOM_M32: #define __atom 1 // CHECK_ATOM_M32: #define __atom__ 1 // CHECK_ATOM_M32: #define __i386 1 // CHECK_ATOM_M32: #define __i386__ 1 // CHECK_ATOM_M32: #define __tune_atom__ 1 // CHECK_ATOM_M32: #define i386 1 // RUN: %clang -march=atom -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M64 // CHECK_ATOM_M64: #define __MMX__ 1 // CHECK_ATOM_M64: #define __MOVBE__ 1 // CHECK_ATOM_M64: #define __SSE2_MATH__ 1 // CHECK_ATOM_M64: #define __SSE2__ 1 // CHECK_ATOM_M64: #define __SSE3__ 1 // CHECK_ATOM_M64: #define __SSE_MATH__ 1 // CHECK_ATOM_M64: #define __SSE__ 1 // CHECK_ATOM_M64: #define __SSSE3__ 1 // CHECK_ATOM_M64: #define __amd64 1 // CHECK_ATOM_M64: #define __amd64__ 1 // CHECK_ATOM_M64: #define __atom 1 // CHECK_ATOM_M64: #define __atom__ 1 // CHECK_ATOM_M64: #define __tune_atom__ 1 // CHECK_ATOM_M64: #define __x86_64 1 // CHECK_ATOM_M64: #define __x86_64__ 1 // RUN: %clang -march=goldmont -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_GLM_M32 // CHECK_GLM_M32: #define __AES__ 1 // CHECK_GLM_M32: #define __CLFLUSHOPT__ 1 // CHECK_GLM_M32: #define __FSGSBASE__ 1 // CHECK_GLM_M32: #define __FXSR__ 1 // CHECK_GLM_M32: #define __MMX__ 1 // CHECK_GLM_M32: #define __MOVBE__ 1 // CHECK_GLM_M32: #define __MPX__ 1 // CHECK_GLM_M32: #define __PCLMUL__ 1 // CHECK_GLM_M32: #define __POPCNT__ 1 // CHECK_GLM_M32: #define __PRFCHW__ 1 // CHECK_GLM_M32: #define __RDRND__ 1 // CHECK_GLM_M32: #define __RDSEED__ 1 // CHECK_GLM_M32: #define __SHA__ 1 // CHECK_GLM_M32: #define __SSE2__ 1 // CHECK_GLM_M32: #define __SSE3__ 1 // CHECK_GLM_M32: #define __SSE4_1__ 1 // CHECK_GLM_M32: #define __SSE4_2__ 1 // CHECK_GLM_M32: #define __SSE_MATH__ 1 // CHECK_GLM_M32: #define __SSE__ 1 // CHECK_GLM_M32: #define __SSSE3__ 1 // CHECK_GLM_M32: #define __XSAVEC__ 1 // CHECK_GLM_M32: #define __XSAVEOPT__ 1 // CHECK_GLM_M32: #define __XSAVES__ 1 // CHECK_GLM_M32: #define __XSAVE__ 1 // CHECK_GLM_M32: #define __goldmont 1 // CHECK_GLM_M32: #define __goldmont__ 1 // CHECK_GLM_M32: #define __i386 1 // CHECK_GLM_M32: #define __i386__ 1 // CHECK_GLM_M32: #define __tune_goldmont__ 1 // CHECK_GLM_M32: #define i386 1 // RUN: %clang -march=goldmont -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_GLM_M64 // CHECK_GLM_M64: #define __AES__ 1 // CHECK_GLM_M64: #define __CLFLUSHOPT__ 1 // CHECK_GLM_M64: #define __FSGSBASE__ 1 // CHECK_GLM_M64: #define __FXSR__ 1 // CHECK_GLM_M64: #define __MMX__ 1 // CHECK_GLM_M64: #define __MOVBE__ 1 // CHECK_GLM_M64: #define __MPX__ 1 // CHECK_GLM_M64: #define __PCLMUL__ 1 // CHECK_GLM_M64: #define __POPCNT__ 1 // CHECK_GLM_M64: #define __PRFCHW__ 1 // CHECK_GLM_M64: #define __RDRND__ 1 // CHECK_GLM_M64: #define __RDSEED__ 1 // CHECK_GLM_M64: #define __SHA__ 1 // CHECK_GLM_M64: #define __SSE2__ 1 // CHECK_GLM_M64: #define __SSE3__ 1 // CHECK_GLM_M64: #define __SSE4_1__ 1 // CHECK_GLM_M64: #define __SSE4_2__ 1 // CHECK_GLM_M64: #define __SSE__ 1 // CHECK_GLM_M64: #define __SSSE3__ 1 // CHECK_GLM_M64: #define __XSAVEC__ 1 // CHECK_GLM_M64: #define __XSAVEOPT__ 1 // CHECK_GLM_M64: #define __XSAVES__ 1 // CHECK_GLM_M64: #define __XSAVE__ 1 // CHECK_GLM_M64: #define __goldmont 1 // CHECK_GLM_M64: #define __goldmont__ 1 // CHECK_GLM_M64: #define __tune_goldmont__ 1 // CHECK_GLM_M64: #define __x86_64 1 // CHECK_GLM_M64: #define __x86_64__ 1 // RUN: %clang -march=goldmont-plus -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_GLMP_M32 // CHECK_GLMP_M32: #define __AES__ 1 // CHECK_GLMP_M32: #define __CLFLUSHOPT__ 1 // CHECK_GLMP_M32: #define __FSGSBASE__ 1 // CHECK_GLMP_M32: #define __FXSR__ 1 // CHECK_GLMP_M32: #define __MMX__ 1 // CHECK_GLMP_M32: #define __MOVBE__ 1 // CHECK_GLMP_M32: #define __MPX__ 1 // CHECK_GLMP_M32: #define __PCLMUL__ 1 // CHECK_GLMP_M32: #define __POPCNT__ 1 // CHECK_GLMP_M32: #define __PRFCHW__ 1 // CHECK_GLMP_M32: #define __PTWRITE__ 1 // CHECK_GLMP_M32: #define __RDPID__ 1 // CHECK_GLMP_M32: #define __RDRND__ 1 // CHECK_GLMP_M32: #define __RDSEED__ 1 // CHECK_GLMP_M32: #define __SGX__ 1 // CHECK_GLMP_M32: #define __SHA__ 1 // CHECK_GLMP_M32: #define __SSE2__ 1 // CHECK_GLMP_M32: #define __SSE3__ 1 // CHECK_GLMP_M32: #define __SSE4_1__ 1 // CHECK_GLMP_M32: #define __SSE4_2__ 1 // CHECK_GLMP_M32: #define __SSE_MATH__ 1 // CHECK_GLMP_M32: #define __SSE__ 1 // CHECK_GLMP_M32: #define __SSSE3__ 1 // CHECK_GLMP_M32: #define __XSAVEC__ 1 // CHECK_GLMP_M32: #define __XSAVEOPT__ 1 // CHECK_GLMP_M32: #define __XSAVES__ 1 // CHECK_GLMP_M32: #define __XSAVE__ 1 // CHECK_GLMP_M32: #define __goldmont_plus 1 // CHECK_GLMP_M32: #define __goldmont_plus__ 1 // CHECK_GLMP_M32: #define __i386 1 // CHECK_GLMP_M32: #define __i386__ 1 // CHECK_GLMP_M32: #define __tune_goldmont_plus__ 1 // CHECK_GLMP_M32: #define i386 1 // RUN: %clang -march=goldmont-plus -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_GLMP_M64 // CHECK_GLMP_M64: #define __AES__ 1 // CHECK_GLMP_M64: #define __CLFLUSHOPT__ 1 // CHECK_GLMP_M64: #define __FSGSBASE__ 1 // CHECK_GLMP_M64: #define __FXSR__ 1 // CHECK_GLMP_M64: #define __MMX__ 1 // CHECK_GLMP_M64: #define __MOVBE__ 1 // CHECK_GLMP_M64: #define __MPX__ 1 // CHECK_GLMP_M64: #define __PCLMUL__ 1 // CHECK_GLMP_M64: #define __POPCNT__ 1 // CHECK_GLMP_M64: #define __PRFCHW__ 1 // CHECK_GLMP_M64: #define __PTWRITE__ 1 // CHECK_GLMP_M64: #define __RDPID__ 1 // CHECK_GLMP_M64: #define __RDRND__ 1 // CHECK_GLMP_M64: #define __RDSEED__ 1 // CHECK_GLMP_M64: #define __SGX__ 1 // CHECK_GLMP_M64: #define __SHA__ 1 // CHECK_GLMP_M64: #define __SSE2__ 1 // CHECK_GLMP_M64: #define __SSE3__ 1 // CHECK_GLMP_M64: #define __SSE4_1__ 1 // CHECK_GLMP_M64: #define __SSE4_2__ 1 // CHECK_GLMP_M64: #define __SSE__ 1 // CHECK_GLMP_M64: #define __SSSE3__ 1 // CHECK_GLMP_M64: #define __XSAVEC__ 1 // CHECK_GLMP_M64: #define __XSAVEOPT__ 1 // CHECK_GLMP_M64: #define __XSAVES__ 1 // CHECK_GLMP_M64: #define __XSAVE__ 1 // CHECK_GLMP_M64: #define __goldmont_plus 1 // CHECK_GLMP_M64: #define __goldmont_plus__ 1 // CHECK_GLMP_M64: #define __tune_goldmont_plus__ 1 // CHECK_GLMP_M64: #define __x86_64 1 // CHECK_GLMP_M64: #define __x86_64__ 1 // RUN: %clang -march=tremont -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_TRM_M32 // CHECK_TRM_M32: #define __AES__ 1 // CHECK_TRM_M32: #define __CLDEMOTE__ 1 // CHECK_TRM_M32: #define __CLFLUSHOPT__ 1 // CHECK_TRM_M32: #define __FSGSBASE__ 1 // CHECK_TRM_M32: #define __FXSR__ 1 // CHECK_TRM_M32: #define __GFNI__ 1 // CHECK_TRM_M32: #define __MMX__ 1 // CHECK_TRM_M32: #define __MOVBE__ 1 // CHECK_TRM_M32: #define __MOVDIR64B__ 1 // CHECK_TRM_M32: #define __MOVDIRI__ 1 // CHECK_TRM_M32: #define __MPX__ 1 // CHECK_TRM_M32: #define __PCLMUL__ 1 // CHECK_TRM_M32: #define __POPCNT__ 1 // CHECK_TRM_M32: #define __PRFCHW__ 1 // CHECK_TRM_M32: #define __PTWRITE__ 1 // CHECK_TRM_M32: #define __RDPID__ 1 // CHECK_TRM_M32: #define __RDRND__ 1 // CHECK_TRM_M32: #define __RDSEED__ 1 // CHECK_TRM_M32: #define __SGX__ 1 // CHECK_TRM_M32: #define __SHA__ 1 // CHECK_TRM_M32: #define __SSE2__ 1 // CHECK_TRM_M32: #define __SSE3__ 1 // CHECK_TRM_M32: #define __SSE4_1__ 1 // CHECK_TRM_M32: #define __SSE4_2__ 1 // CHECK_TRM_M32: #define __SSE_MATH__ 1 // CHECK_TRM_M32: #define __SSE__ 1 // CHECK_TRM_M32: #define __SSSE3__ 1 // CHECK_TRM_M32: #define __WAITPKG__ 1 // CHECK_TRM_M32: #define __XSAVEC__ 1 // CHECK_TRM_M32: #define __XSAVEOPT__ 1 // CHECK_TRM_M32: #define __XSAVES__ 1 // CHECK_TRM_M32: #define __XSAVE__ 1 // CHECK_TRM_M32: #define __i386 1 // CHECK_TRM_M32: #define __i386__ 1 // CHECK_TRM_M32: #define __tremont 1 // CHECK_TRM_M32: #define __tremont__ 1 // CHECK_TRM_M32: #define __tune_tremont__ 1 // CHECK_TRM_M32: #define i386 1 // RUN: %clang -march=tremont -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_TRM_M64 // CHECK_TRM_M64: #define __AES__ 1 // CHECK_TRM_M64: #define __CLDEMOTE__ 1 // CHECK_TRM_M64: #define __CLFLUSHOPT__ 1 // CHECK_TRM_M64: #define __FSGSBASE__ 1 // CHECK_TRM_M64: #define __FXSR__ 1 // CHECK_TRM_M64: #define __GFNI__ 1 // CHECK_TRM_M64: #define __MMX__ 1 // CHECK_TRM_M64: #define __MOVBE__ 1 // CHECK_TRM_M64: #define __MOVDIR64B__ 1 // CHECK_TRM_M64: #define __MOVDIRI__ 1 // CHECK_TRM_M64: #define __MPX__ 1 // CHECK_TRM_M64: #define __PCLMUL__ 1 // CHECK_TRM_M64: #define __POPCNT__ 1 // CHECK_TRM_M64: #define __PRFCHW__ 1 // CHECK_TRM_M64: #define __PTWRITE__ 1 // CHECK_TRM_M64: #define __RDPID__ 1 // CHECK_TRM_M64: #define __RDRND__ 1 // CHECK_TRM_M64: #define __RDSEED__ 1 // CHECK_TRM_M64: #define __SGX__ 1 // CHECK_TRM_M64: #define __SHA__ 1 // CHECK_TRM_M64: #define __SSE2__ 1 // CHECK_TRM_M64: #define __SSE3__ 1 // CHECK_TRM_M64: #define __SSE4_1__ 1 // CHECK_TRM_M64: #define __SSE4_2__ 1 // CHECK_TRM_M64: #define __SSE__ 1 // CHECK_TRM_M64: #define __SSSE3__ 1 // CHECK_TRM_M64: #define __WAITPKG__ 1 // CHECK_TRM_M64: #define __XSAVEC__ 1 // CHECK_TRM_M64: #define __XSAVEOPT__ 1 // CHECK_TRM_M64: #define __XSAVES__ 1 // CHECK_TRM_M64: #define __XSAVE__ 1 // CHECK_TRM_M64: #define __tremont 1 // CHECK_TRM_M64: #define __tremont__ 1 // CHECK_TRM_M64: #define __tune_tremont__ 1 // CHECK_TRM_M64: #define __x86_64 1 // CHECK_TRM_M64: #define __x86_64__ 1 // RUN: %clang -march=slm -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SLM_M32 // CHECK_SLM_M32: #define __FXSR__ 1 // CHECK_SLM_M32: #define __MMX__ 1 // CHECK_SLM_M32: #define __MOVBE__ 1 // CHECK_SLM_M32: #define __PCLMUL__ 1 // CHECK_SLM_M32: #define __POPCNT__ 1 // CHECK_SLM_M32: #define __PRFCHW__ 1 // CHECK_SLM_M32: #define __RDRND__ 1 // CHECK_SLM_M32: #define __SSE2__ 1 // CHECK_SLM_M32: #define __SSE3__ 1 // CHECK_SLM_M32: #define __SSE4_1__ 1 // CHECK_SLM_M32: #define __SSE4_2__ 1 // CHECK_SLM_M32: #define __SSE__ 1 // CHECK_SLM_M32: #define __SSSE3__ 1 // CHECK_SLM_M32: #define __i386 1 // CHECK_SLM_M32: #define __i386__ 1 // CHECK_SLM_M32: #define __slm 1 // CHECK_SLM_M32: #define __slm__ 1 // CHECK_SLM_M32: #define __tune_slm__ 1 // CHECK_SLM_M32: #define i386 1 // RUN: %clang -march=slm -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SLM_M64 // CHECK_SLM_M64: #define __FXSR__ 1 // CHECK_SLM_M64: #define __MMX__ 1 // CHECK_SLM_M64: #define __MOVBE__ 1 // CHECK_SLM_M64: #define __PCLMUL__ 1 // CHECK_SLM_M64: #define __POPCNT__ 1 // CHECK_SLM_M64: #define __PRFCHW__ 1 // CHECK_SLM_M64: #define __RDRND__ 1 // CHECK_SLM_M64: #define __SSE2_MATH__ 1 // CHECK_SLM_M64: #define __SSE2__ 1 // CHECK_SLM_M64: #define __SSE3__ 1 // CHECK_SLM_M64: #define __SSE4_1__ 1 // CHECK_SLM_M64: #define __SSE4_2__ 1 // CHECK_SLM_M64: #define __SSE_MATH__ 1 // CHECK_SLM_M64: #define __SSE__ 1 // CHECK_SLM_M64: #define __SSSE3__ 1 // CHECK_SLM_M64: #define __amd64 1 // CHECK_SLM_M64: #define __amd64__ 1 // CHECK_SLM_M64: #define __slm 1 // CHECK_SLM_M64: #define __slm__ 1 // CHECK_SLM_M64: #define __tune_slm__ 1 // CHECK_SLM_M64: #define __x86_64 1 // CHECK_SLM_M64: #define __x86_64__ 1 // RUN: %clang -march=lakemont -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_LAKEMONT_M32 // CHECK_LAKEMONT_M32: #define __i386 1 // CHECK_LAKEMONT_M32: #define __i386__ 1 // CHECK_LAKEMONT_M32: #define __i586 1 // CHECK_LAKEMONT_M32: #define __i586__ 1 // CHECK_LAKEMONT_M32: #define __pentium 1 // CHECK_LAKEMONT_M32: #define __pentium__ 1 // CHECK_LAKEMONT_M32: #define __tune_lakemont__ 1 // CHECK_LAKEMONT_M32: #define i386 1 // RUN: not %clang -march=lakemont -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck %s -check-prefix=CHECK_LAKEMONT_M64 // CHECK_LAKEMONT_M64: error: // RUN: %clang -march=geode -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_GEODE_M32 // CHECK_GEODE_M32: #define __3dNOW_A__ 1 // CHECK_GEODE_M32: #define __3dNOW__ 1 // CHECK_GEODE_M32: #define __MMX__ 1 // CHECK_GEODE_M32: #define __geode 1 // CHECK_GEODE_M32: #define __geode__ 1 // CHECK_GEODE_M32: #define __i386 1 // CHECK_GEODE_M32: #define __i386__ 1 // CHECK_GEODE_M32: #define __tune_geode__ 1 // CHECK_GEODE_M32: #define i386 1 // RUN: not %clang -march=geode -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_GEODE_M64 // CHECK_GEODE_M64: error: {{.*}} // RUN: %clang -march=k6 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_M32 // CHECK_K6_M32: #define __MMX__ 1 // CHECK_K6_M32: #define __i386 1 // CHECK_K6_M32: #define __i386__ 1 // CHECK_K6_M32: #define __k6 1 // CHECK_K6_M32: #define __k6__ 1 // CHECK_K6_M32: #define __tune_k6__ 1 // CHECK_K6_M32: #define i386 1 // RUN: not %clang -march=k6 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_M64 // CHECK_K6_M64: error: {{.*}} // RUN: %clang -march=k6-2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_2_M32 // CHECK_K6_2_M32: #define __3dNOW__ 1 // CHECK_K6_2_M32: #define __MMX__ 1 // CHECK_K6_2_M32: #define __i386 1 // CHECK_K6_2_M32: #define __i386__ 1 // CHECK_K6_2_M32: #define __k6 1 // CHECK_K6_2_M32: #define __k6_2__ 1 // CHECK_K6_2_M32: #define __k6__ 1 // CHECK_K6_2_M32: #define __tune_k6_2__ 1 // CHECK_K6_2_M32: #define __tune_k6__ 1 // CHECK_K6_2_M32: #define i386 1 // RUN: not %clang -march=k6-2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_2_M64 // CHECK_K6_2_M64: error: {{.*}} // RUN: %clang -march=k6-3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_3_M32 // CHECK_K6_3_M32: #define __3dNOW__ 1 // CHECK_K6_3_M32: #define __MMX__ 1 // CHECK_K6_3_M32: #define __i386 1 // CHECK_K6_3_M32: #define __i386__ 1 // CHECK_K6_3_M32: #define __k6 1 // CHECK_K6_3_M32: #define __k6_3__ 1 // CHECK_K6_3_M32: #define __k6__ 1 // CHECK_K6_3_M32: #define __tune_k6_3__ 1 // CHECK_K6_3_M32: #define __tune_k6__ 1 // CHECK_K6_3_M32: #define i386 1 // RUN: not %clang -march=k6-3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K6_3_M64 // CHECK_K6_3_M64: error: {{.*}} // RUN: %clang -march=athlon -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_M32 // CHECK_ATHLON_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_M32: #define __3dNOW__ 1 // CHECK_ATHLON_M32: #define __MMX__ 1 // CHECK_ATHLON_M32: #define __athlon 1 // CHECK_ATHLON_M32: #define __athlon__ 1 // CHECK_ATHLON_M32: #define __i386 1 // CHECK_ATHLON_M32: #define __i386__ 1 // CHECK_ATHLON_M32: #define __tune_athlon__ 1 // CHECK_ATHLON_M32: #define i386 1 // RUN: not %clang -march=athlon -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_M64 // CHECK_ATHLON_M64: error: {{.*}} // RUN: %clang -march=athlon-tbird -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_TBIRD_M32 // CHECK_ATHLON_TBIRD_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_TBIRD_M32: #define __3dNOW__ 1 // CHECK_ATHLON_TBIRD_M32: #define __MMX__ 1 // CHECK_ATHLON_TBIRD_M32: #define __athlon 1 // CHECK_ATHLON_TBIRD_M32: #define __athlon__ 1 // CHECK_ATHLON_TBIRD_M32: #define __i386 1 // CHECK_ATHLON_TBIRD_M32: #define __i386__ 1 // CHECK_ATHLON_TBIRD_M32: #define __tune_athlon__ 1 // CHECK_ATHLON_TBIRD_M32: #define i386 1 // RUN: not %clang -march=athlon-tbird -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_TBIRD_M64 // CHECK_ATHLON_TBIRD_M64: error: {{.*}} // RUN: %clang -march=athlon-4 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_4_M32 // CHECK_ATHLON_4_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_4_M32: #define __3dNOW__ 1 // CHECK_ATHLON_4_M32: #define __MMX__ 1 // CHECK_ATHLON_4_M32: #define __SSE__ 1 // CHECK_ATHLON_4_M32: #define __athlon 1 // CHECK_ATHLON_4_M32: #define __athlon__ 1 // CHECK_ATHLON_4_M32: #define __athlon_sse__ 1 // CHECK_ATHLON_4_M32: #define __i386 1 // CHECK_ATHLON_4_M32: #define __i386__ 1 // CHECK_ATHLON_4_M32: #define __tune_athlon__ 1 // CHECK_ATHLON_4_M32: #define __tune_athlon_sse__ 1 // CHECK_ATHLON_4_M32: #define i386 1 // RUN: not %clang -march=athlon-4 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_4_M64 // CHECK_ATHLON_4_M64: error: {{.*}} // RUN: %clang -march=athlon-xp -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_XP_M32 // CHECK_ATHLON_XP_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_XP_M32: #define __3dNOW__ 1 // CHECK_ATHLON_XP_M32: #define __MMX__ 1 // CHECK_ATHLON_XP_M32: #define __SSE__ 1 // CHECK_ATHLON_XP_M32: #define __athlon 1 // CHECK_ATHLON_XP_M32: #define __athlon__ 1 // CHECK_ATHLON_XP_M32: #define __athlon_sse__ 1 // CHECK_ATHLON_XP_M32: #define __i386 1 // CHECK_ATHLON_XP_M32: #define __i386__ 1 // CHECK_ATHLON_XP_M32: #define __tune_athlon__ 1 // CHECK_ATHLON_XP_M32: #define __tune_athlon_sse__ 1 // CHECK_ATHLON_XP_M32: #define i386 1 // RUN: not %clang -march=athlon-xp -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_XP_M64 // CHECK_ATHLON_XP_M64: error: {{.*}} // RUN: %clang -march=athlon-mp -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_MP_M32 // CHECK_ATHLON_MP_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_MP_M32: #define __3dNOW__ 1 // CHECK_ATHLON_MP_M32: #define __MMX__ 1 // CHECK_ATHLON_MP_M32: #define __SSE__ 1 // CHECK_ATHLON_MP_M32: #define __athlon 1 // CHECK_ATHLON_MP_M32: #define __athlon__ 1 // CHECK_ATHLON_MP_M32: #define __athlon_sse__ 1 // CHECK_ATHLON_MP_M32: #define __i386 1 // CHECK_ATHLON_MP_M32: #define __i386__ 1 // CHECK_ATHLON_MP_M32: #define __tune_athlon__ 1 // CHECK_ATHLON_MP_M32: #define __tune_athlon_sse__ 1 // CHECK_ATHLON_MP_M32: #define i386 1 // RUN: not %clang -march=athlon-mp -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_MP_M64 // CHECK_ATHLON_MP_M64: error: {{.*}} // RUN: %clang -march=x86-64 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_X86_64_M32 // CHECK_X86_64_M32: #define __MMX__ 1 // CHECK_X86_64_M32: #define __SSE2__ 1 // CHECK_X86_64_M32: #define __SSE__ 1 // CHECK_X86_64_M32: #define __i386 1 // CHECK_X86_64_M32: #define __i386__ 1 // CHECK_X86_64_M32: #define __k8 1 // CHECK_X86_64_M32: #define __k8__ 1 // CHECK_X86_64_M32: #define i386 1 // RUN: %clang -march=x86-64 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_X86_64_M64 // CHECK_X86_64_M64: #define __MMX__ 1 // CHECK_X86_64_M64: #define __SSE2_MATH__ 1 // CHECK_X86_64_M64: #define __SSE2__ 1 // CHECK_X86_64_M64: #define __SSE_MATH__ 1 // CHECK_X86_64_M64: #define __SSE__ 1 // CHECK_X86_64_M64: #define __amd64 1 // CHECK_X86_64_M64: #define __amd64__ 1 // CHECK_X86_64_M64: #define __k8 1 // CHECK_X86_64_M64: #define __k8__ 1 // CHECK_X86_64_M64: #define __x86_64 1 // CHECK_X86_64_M64: #define __x86_64__ 1 // RUN: %clang -march=k8 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_M32 // CHECK_K8_M32: #define __3dNOW_A__ 1 // CHECK_K8_M32: #define __3dNOW__ 1 // CHECK_K8_M32: #define __MMX__ 1 // CHECK_K8_M32: #define __SSE2__ 1 // CHECK_K8_M32: #define __SSE__ 1 // CHECK_K8_M32: #define __i386 1 // CHECK_K8_M32: #define __i386__ 1 // CHECK_K8_M32: #define __k8 1 // CHECK_K8_M32: #define __k8__ 1 // CHECK_K8_M32: #define __tune_k8__ 1 // CHECK_K8_M32: #define i386 1 // RUN: %clang -march=k8 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_M64 // CHECK_K8_M64: #define __3dNOW_A__ 1 // CHECK_K8_M64: #define __3dNOW__ 1 // CHECK_K8_M64: #define __MMX__ 1 // CHECK_K8_M64: #define __SSE2_MATH__ 1 // CHECK_K8_M64: #define __SSE2__ 1 // CHECK_K8_M64: #define __SSE_MATH__ 1 // CHECK_K8_M64: #define __SSE__ 1 // CHECK_K8_M64: #define __amd64 1 // CHECK_K8_M64: #define __amd64__ 1 // CHECK_K8_M64: #define __k8 1 // CHECK_K8_M64: #define __k8__ 1 // CHECK_K8_M64: #define __tune_k8__ 1 // CHECK_K8_M64: #define __x86_64 1 // CHECK_K8_M64: #define __x86_64__ 1 // RUN: %clang -march=k8-sse3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_SSE3_M32 // CHECK_K8_SSE3_M32: #define __3dNOW_A__ 1 // CHECK_K8_SSE3_M32: #define __3dNOW__ 1 // CHECK_K8_SSE3_M32: #define __MMX__ 1 // CHECK_K8_SSE3_M32: #define __SSE2__ 1 // CHECK_K8_SSE3_M32: #define __SSE3__ 1 // CHECK_K8_SSE3_M32: #define __SSE__ 1 // CHECK_K8_SSE3_M32: #define __i386 1 // CHECK_K8_SSE3_M32: #define __i386__ 1 // CHECK_K8_SSE3_M32: #define __k8 1 // CHECK_K8_SSE3_M32: #define __k8__ 1 // CHECK_K8_SSE3_M32: #define __tune_k8__ 1 // CHECK_K8_SSE3_M32: #define i386 1 // RUN: %clang -march=k8-sse3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_K8_SSE3_M64 // CHECK_K8_SSE3_M64: #define __3dNOW_A__ 1 // CHECK_K8_SSE3_M64: #define __3dNOW__ 1 // CHECK_K8_SSE3_M64: #define __MMX__ 1 // CHECK_K8_SSE3_M64: #define __SSE2_MATH__ 1 // CHECK_K8_SSE3_M64: #define __SSE2__ 1 // CHECK_K8_SSE3_M64: #define __SSE3__ 1 // CHECK_K8_SSE3_M64: #define __SSE_MATH__ 1 // CHECK_K8_SSE3_M64: #define __SSE__ 1 // CHECK_K8_SSE3_M64: #define __amd64 1 // CHECK_K8_SSE3_M64: #define __amd64__ 1 // CHECK_K8_SSE3_M64: #define __k8 1 // CHECK_K8_SSE3_M64: #define __k8__ 1 // CHECK_K8_SSE3_M64: #define __tune_k8__ 1 // CHECK_K8_SSE3_M64: #define __x86_64 1 // CHECK_K8_SSE3_M64: #define __x86_64__ 1 // RUN: %clang -march=opteron -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_M32 // CHECK_OPTERON_M32: #define __3dNOW_A__ 1 // CHECK_OPTERON_M32: #define __3dNOW__ 1 // CHECK_OPTERON_M32: #define __MMX__ 1 // CHECK_OPTERON_M32: #define __SSE2__ 1 // CHECK_OPTERON_M32: #define __SSE__ 1 // CHECK_OPTERON_M32: #define __i386 1 // CHECK_OPTERON_M32: #define __i386__ 1 // CHECK_OPTERON_M32: #define __k8 1 // CHECK_OPTERON_M32: #define __k8__ 1 // CHECK_OPTERON_M32: #define __tune_k8__ 1 // CHECK_OPTERON_M32: #define i386 1 // RUN: %clang -march=opteron -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_M64 // CHECK_OPTERON_M64: #define __3dNOW_A__ 1 // CHECK_OPTERON_M64: #define __3dNOW__ 1 // CHECK_OPTERON_M64: #define __MMX__ 1 // CHECK_OPTERON_M64: #define __SSE2_MATH__ 1 // CHECK_OPTERON_M64: #define __SSE2__ 1 // CHECK_OPTERON_M64: #define __SSE_MATH__ 1 // CHECK_OPTERON_M64: #define __SSE__ 1 // CHECK_OPTERON_M64: #define __amd64 1 // CHECK_OPTERON_M64: #define __amd64__ 1 // CHECK_OPTERON_M64: #define __k8 1 // CHECK_OPTERON_M64: #define __k8__ 1 // CHECK_OPTERON_M64: #define __tune_k8__ 1 // CHECK_OPTERON_M64: #define __x86_64 1 // CHECK_OPTERON_M64: #define __x86_64__ 1 // RUN: %clang -march=opteron-sse3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_SSE3_M32 // CHECK_OPTERON_SSE3_M32: #define __3dNOW_A__ 1 // CHECK_OPTERON_SSE3_M32: #define __3dNOW__ 1 // CHECK_OPTERON_SSE3_M32: #define __MMX__ 1 // CHECK_OPTERON_SSE3_M32: #define __SSE2__ 1 // CHECK_OPTERON_SSE3_M32: #define __SSE3__ 1 // CHECK_OPTERON_SSE3_M32: #define __SSE__ 1 // CHECK_OPTERON_SSE3_M32: #define __i386 1 // CHECK_OPTERON_SSE3_M32: #define __i386__ 1 // CHECK_OPTERON_SSE3_M32: #define __k8 1 // CHECK_OPTERON_SSE3_M32: #define __k8__ 1 // CHECK_OPTERON_SSE3_M32: #define __tune_k8__ 1 // CHECK_OPTERON_SSE3_M32: #define i386 1 // RUN: %clang -march=opteron-sse3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_OPTERON_SSE3_M64 // CHECK_OPTERON_SSE3_M64: #define __3dNOW_A__ 1 // CHECK_OPTERON_SSE3_M64: #define __3dNOW__ 1 // CHECK_OPTERON_SSE3_M64: #define __MMX__ 1 // CHECK_OPTERON_SSE3_M64: #define __SSE2_MATH__ 1 // CHECK_OPTERON_SSE3_M64: #define __SSE2__ 1 // CHECK_OPTERON_SSE3_M64: #define __SSE3__ 1 // CHECK_OPTERON_SSE3_M64: #define __SSE_MATH__ 1 // CHECK_OPTERON_SSE3_M64: #define __SSE__ 1 // CHECK_OPTERON_SSE3_M64: #define __amd64 1 // CHECK_OPTERON_SSE3_M64: #define __amd64__ 1 // CHECK_OPTERON_SSE3_M64: #define __k8 1 // CHECK_OPTERON_SSE3_M64: #define __k8__ 1 // CHECK_OPTERON_SSE3_M64: #define __tune_k8__ 1 // CHECK_OPTERON_SSE3_M64: #define __x86_64 1 // CHECK_OPTERON_SSE3_M64: #define __x86_64__ 1 // RUN: %clang -march=athlon64 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_M32 // CHECK_ATHLON64_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON64_M32: #define __3dNOW__ 1 // CHECK_ATHLON64_M32: #define __MMX__ 1 // CHECK_ATHLON64_M32: #define __SSE2__ 1 // CHECK_ATHLON64_M32: #define __SSE__ 1 // CHECK_ATHLON64_M32: #define __i386 1 // CHECK_ATHLON64_M32: #define __i386__ 1 // CHECK_ATHLON64_M32: #define __k8 1 // CHECK_ATHLON64_M32: #define __k8__ 1 // CHECK_ATHLON64_M32: #define __tune_k8__ 1 // CHECK_ATHLON64_M32: #define i386 1 // RUN: %clang -march=athlon64 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_M64 // CHECK_ATHLON64_M64: #define __3dNOW_A__ 1 // CHECK_ATHLON64_M64: #define __3dNOW__ 1 // CHECK_ATHLON64_M64: #define __MMX__ 1 // CHECK_ATHLON64_M64: #define __SSE2_MATH__ 1 // CHECK_ATHLON64_M64: #define __SSE2__ 1 // CHECK_ATHLON64_M64: #define __SSE_MATH__ 1 // CHECK_ATHLON64_M64: #define __SSE__ 1 // CHECK_ATHLON64_M64: #define __amd64 1 // CHECK_ATHLON64_M64: #define __amd64__ 1 // CHECK_ATHLON64_M64: #define __k8 1 // CHECK_ATHLON64_M64: #define __k8__ 1 // CHECK_ATHLON64_M64: #define __tune_k8__ 1 // CHECK_ATHLON64_M64: #define __x86_64 1 // CHECK_ATHLON64_M64: #define __x86_64__ 1 // RUN: %clang -march=athlon64-sse3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_SSE3_M32 // CHECK_ATHLON64_SSE3_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON64_SSE3_M32: #define __3dNOW__ 1 // CHECK_ATHLON64_SSE3_M32: #define __MMX__ 1 // CHECK_ATHLON64_SSE3_M32: #define __SSE2__ 1 // CHECK_ATHLON64_SSE3_M32: #define __SSE3__ 1 // CHECK_ATHLON64_SSE3_M32: #define __SSE__ 1 // CHECK_ATHLON64_SSE3_M32: #define __i386 1 // CHECK_ATHLON64_SSE3_M32: #define __i386__ 1 // CHECK_ATHLON64_SSE3_M32: #define __k8 1 // CHECK_ATHLON64_SSE3_M32: #define __k8__ 1 // CHECK_ATHLON64_SSE3_M32: #define __tune_k8__ 1 // CHECK_ATHLON64_SSE3_M32: #define i386 1 // RUN: %clang -march=athlon64-sse3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON64_SSE3_M64 // CHECK_ATHLON64_SSE3_M64: #define __3dNOW_A__ 1 // CHECK_ATHLON64_SSE3_M64: #define __3dNOW__ 1 // CHECK_ATHLON64_SSE3_M64: #define __MMX__ 1 // CHECK_ATHLON64_SSE3_M64: #define __SSE2_MATH__ 1 // CHECK_ATHLON64_SSE3_M64: #define __SSE2__ 1 // CHECK_ATHLON64_SSE3_M64: #define __SSE3__ 1 // CHECK_ATHLON64_SSE3_M64: #define __SSE_MATH__ 1 // CHECK_ATHLON64_SSE3_M64: #define __SSE__ 1 // CHECK_ATHLON64_SSE3_M64: #define __amd64 1 // CHECK_ATHLON64_SSE3_M64: #define __amd64__ 1 // CHECK_ATHLON64_SSE3_M64: #define __k8 1 // CHECK_ATHLON64_SSE3_M64: #define __k8__ 1 // CHECK_ATHLON64_SSE3_M64: #define __tune_k8__ 1 // CHECK_ATHLON64_SSE3_M64: #define __x86_64 1 // CHECK_ATHLON64_SSE3_M64: #define __x86_64__ 1 // RUN: %clang -march=athlon-fx -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_FX_M32 // CHECK_ATHLON_FX_M32: #define __3dNOW_A__ 1 // CHECK_ATHLON_FX_M32: #define __3dNOW__ 1 // CHECK_ATHLON_FX_M32: #define __MMX__ 1 // CHECK_ATHLON_FX_M32: #define __SSE2__ 1 // CHECK_ATHLON_FX_M32: #define __SSE__ 1 // CHECK_ATHLON_FX_M32: #define __i386 1 // CHECK_ATHLON_FX_M32: #define __i386__ 1 // CHECK_ATHLON_FX_M32: #define __k8 1 // CHECK_ATHLON_FX_M32: #define __k8__ 1 // CHECK_ATHLON_FX_M32: #define __tune_k8__ 1 // CHECK_ATHLON_FX_M32: #define i386 1 // RUN: %clang -march=athlon-fx -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ATHLON_FX_M64 // CHECK_ATHLON_FX_M64: #define __3dNOW_A__ 1 // CHECK_ATHLON_FX_M64: #define __3dNOW__ 1 // CHECK_ATHLON_FX_M64: #define __MMX__ 1 // CHECK_ATHLON_FX_M64: #define __SSE2_MATH__ 1 // CHECK_ATHLON_FX_M64: #define __SSE2__ 1 // CHECK_ATHLON_FX_M64: #define __SSE_MATH__ 1 // CHECK_ATHLON_FX_M64: #define __SSE__ 1 // CHECK_ATHLON_FX_M64: #define __amd64 1 // CHECK_ATHLON_FX_M64: #define __amd64__ 1 // CHECK_ATHLON_FX_M64: #define __k8 1 // CHECK_ATHLON_FX_M64: #define __k8__ 1 // CHECK_ATHLON_FX_M64: #define __tune_k8__ 1 // CHECK_ATHLON_FX_M64: #define __x86_64 1 // CHECK_ATHLON_FX_M64: #define __x86_64__ 1 // RUN: %clang -march=amdfam10 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDFAM10_M32 // CHECK_AMDFAM10_M32: #define __3dNOW_A__ 1 // CHECK_AMDFAM10_M32: #define __3dNOW__ 1 // CHECK_AMDFAM10_M32: #define __LZCNT__ 1 // CHECK_AMDFAM10_M32: #define __MMX__ 1 // CHECK_AMDFAM10_M32: #define __POPCNT__ 1 // CHECK_AMDFAM10_M32: #define __SSE2_MATH__ 1 // CHECK_AMDFAM10_M32: #define __SSE2__ 1 // CHECK_AMDFAM10_M32: #define __SSE3__ 1 // CHECK_AMDFAM10_M32: #define __SSE4A__ 1 // CHECK_AMDFAM10_M32: #define __SSE_MATH__ 1 // CHECK_AMDFAM10_M32: #define __SSE__ 1 // CHECK_AMDFAM10_M32: #define __amdfam10 1 // CHECK_AMDFAM10_M32: #define __amdfam10__ 1 // CHECK_AMDFAM10_M32: #define __i386 1 // CHECK_AMDFAM10_M32: #define __i386__ 1 // CHECK_AMDFAM10_M32: #define __tune_amdfam10__ 1 // RUN: %clang -march=amdfam10 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDFAM10_M64 // CHECK_AMDFAM10_M64: #define __3dNOW_A__ 1 // CHECK_AMDFAM10_M64: #define __3dNOW__ 1 // CHECK_AMDFAM10_M64: #define __LZCNT__ 1 // CHECK_AMDFAM10_M64: #define __MMX__ 1 // CHECK_AMDFAM10_M64: #define __POPCNT__ 1 // CHECK_AMDFAM10_M64: #define __SSE2_MATH__ 1 // CHECK_AMDFAM10_M64: #define __SSE2__ 1 // CHECK_AMDFAM10_M64: #define __SSE3__ 1 // CHECK_AMDFAM10_M64: #define __SSE4A__ 1 // CHECK_AMDFAM10_M64: #define __SSE_MATH__ 1 // CHECK_AMDFAM10_M64: #define __SSE__ 1 // CHECK_AMDFAM10_M64: #define __amd64 1 // CHECK_AMDFAM10_M64: #define __amd64__ 1 // CHECK_AMDFAM10_M64: #define __amdfam10 1 // CHECK_AMDFAM10_M64: #define __amdfam10__ 1 // CHECK_AMDFAM10_M64: #define __tune_amdfam10__ 1 // CHECK_AMDFAM10_M64: #define __x86_64 1 // CHECK_AMDFAM10_M64: #define __x86_64__ 1 // RUN: %clang -march=btver1 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M32 // CHECK_BTVER1_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BTVER1_M32-NOT: #define __3dNOW__ 1 // CHECK_BTVER1_M32: #define __LZCNT__ 1 // CHECK_BTVER1_M32: #define __MMX__ 1 // CHECK_BTVER1_M32: #define __POPCNT__ 1 // CHECK_BTVER1_M32: #define __PRFCHW__ 1 // CHECK_BTVER1_M32: #define __SSE2_MATH__ 1 // CHECK_BTVER1_M32: #define __SSE2__ 1 // CHECK_BTVER1_M32: #define __SSE3__ 1 // CHECK_BTVER1_M32: #define __SSE4A__ 1 // CHECK_BTVER1_M32: #define __SSE_MATH__ 1 // CHECK_BTVER1_M32: #define __SSE__ 1 // CHECK_BTVER1_M32: #define __SSSE3__ 1 // CHECK_BTVER1_M32: #define __btver1 1 // CHECK_BTVER1_M32: #define __btver1__ 1 // CHECK_BTVER1_M32: #define __i386 1 // CHECK_BTVER1_M32: #define __i386__ 1 // CHECK_BTVER1_M32: #define __tune_btver1__ 1 // RUN: %clang -march=btver1 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER1_M64 // CHECK_BTVER1_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BTVER1_M64-NOT: #define __3dNOW__ 1 // CHECK_BTVER1_M64: #define __LZCNT__ 1 // CHECK_BTVER1_M64: #define __MMX__ 1 // CHECK_BTVER1_M64: #define __POPCNT__ 1 // CHECK_BTVER1_M64: #define __PRFCHW__ 1 // CHECK_BTVER1_M64: #define __SSE2_MATH__ 1 // CHECK_BTVER1_M64: #define __SSE2__ 1 // CHECK_BTVER1_M64: #define __SSE3__ 1 // CHECK_BTVER1_M64: #define __SSE4A__ 1 // CHECK_BTVER1_M64: #define __SSE_MATH__ 1 // CHECK_BTVER1_M64: #define __SSE__ 1 // CHECK_BTVER1_M64: #define __SSSE3__ 1 // CHECK_BTVER1_M64: #define __amd64 1 // CHECK_BTVER1_M64: #define __amd64__ 1 // CHECK_BTVER1_M64: #define __btver1 1 // CHECK_BTVER1_M64: #define __btver1__ 1 // CHECK_BTVER1_M64: #define __tune_btver1__ 1 // CHECK_BTVER1_M64: #define __x86_64 1 // CHECK_BTVER1_M64: #define __x86_64__ 1 // RUN: %clang -march=btver2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER2_M32 // CHECK_BTVER2_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BTVER2_M32-NOT: #define __3dNOW__ 1 // CHECK_BTVER2_M32: #define __AES__ 1 // CHECK_BTVER2_M32: #define __AVX__ 1 // CHECK_BTVER2_M32: #define __BMI__ 1 // CHECK_BTVER2_M32: #define __F16C__ 1 // CHECK_BTVER2_M32: #define __LZCNT__ 1 // CHECK_BTVER2_M32: #define __MMX__ 1 // CHECK_BTVER2_M32: #define __MOVBE__ 1 // CHECK_BTVER2_M32: #define __PCLMUL__ 1 // CHECK_BTVER2_M32: #define __POPCNT__ 1 // CHECK_BTVER2_M32: #define __PRFCHW__ 1 // CHECK_BTVER2_M32: #define __SSE2_MATH__ 1 // CHECK_BTVER2_M32: #define __SSE2__ 1 // CHECK_BTVER2_M32: #define __SSE3__ 1 // CHECK_BTVER2_M32: #define __SSE4A__ 1 // CHECK_BTVER2_M32: #define __SSE_MATH__ 1 // CHECK_BTVER2_M32: #define __SSE__ 1 // CHECK_BTVER2_M32: #define __SSSE3__ 1 // CHECK_BTVER2_M32: #define __XSAVEOPT__ 1 // CHECK_BTVER2_M32: #define __XSAVE__ 1 // CHECK_BTVER2_M32: #define __btver2 1 // CHECK_BTVER2_M32: #define __btver2__ 1 // CHECK_BTVER2_M32: #define __i386 1 // CHECK_BTVER2_M32: #define __i386__ 1 // CHECK_BTVER2_M32: #define __tune_btver2__ 1 // RUN: %clang -march=btver2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BTVER2_M64 // CHECK_BTVER2_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BTVER2_M64-NOT: #define __3dNOW__ 1 // CHECK_BTVER2_M64: #define __AES__ 1 // CHECK_BTVER2_M64: #define __AVX__ 1 // CHECK_BTVER2_M64: #define __BMI__ 1 // CHECK_BTVER2_M64: #define __F16C__ 1 // CHECK_BTVER2_M64: #define __LZCNT__ 1 // CHECK_BTVER2_M64: #define __MMX__ 1 // CHECK_BTVER2_M64: #define __MOVBE__ 1 // CHECK_BTVER2_M64: #define __PCLMUL__ 1 // CHECK_BTVER2_M64: #define __POPCNT__ 1 // CHECK_BTVER2_M64: #define __PRFCHW__ 1 // CHECK_BTVER2_M64: #define __SSE2_MATH__ 1 // CHECK_BTVER2_M64: #define __SSE2__ 1 // CHECK_BTVER2_M64: #define __SSE3__ 1 // CHECK_BTVER2_M64: #define __SSE4A__ 1 // CHECK_BTVER2_M64: #define __SSE_MATH__ 1 // CHECK_BTVER2_M64: #define __SSE__ 1 // CHECK_BTVER2_M64: #define __SSSE3__ 1 // CHECK_BTVER2_M64: #define __XSAVEOPT__ 1 // CHECK_BTVER2_M64: #define __XSAVE__ 1 // CHECK_BTVER2_M64: #define __amd64 1 // CHECK_BTVER2_M64: #define __amd64__ 1 // CHECK_BTVER2_M64: #define __btver2 1 // CHECK_BTVER2_M64: #define __btver2__ 1 // CHECK_BTVER2_M64: #define __tune_btver2__ 1 // CHECK_BTVER2_M64: #define __x86_64 1 // CHECK_BTVER2_M64: #define __x86_64__ 1 // RUN: %clang -march=bdver1 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER1_M32 // CHECK_BDVER1_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER1_M32-NOT: #define __3dNOW__ 1 // CHECK_BDVER1_M32: #define __AES__ 1 // CHECK_BDVER1_M32: #define __AVX__ 1 // CHECK_BDVER1_M32: #define __FMA4__ 1 // CHECK_BDVER1_M32: #define __LWP__ 1 // CHECK_BDVER1_M32: #define __LZCNT__ 1 // CHECK_BDVER1_M32: #define __MMX__ 1 // CHECK_BDVER1_M32: #define __PCLMUL__ 1 // CHECK_BDVER1_M32: #define __POPCNT__ 1 // CHECK_BDVER1_M32: #define __PRFCHW__ 1 // CHECK_BDVER1_M32: #define __SSE2_MATH__ 1 // CHECK_BDVER1_M32: #define __SSE2__ 1 // CHECK_BDVER1_M32: #define __SSE3__ 1 // CHECK_BDVER1_M32: #define __SSE4A__ 1 // CHECK_BDVER1_M32: #define __SSE4_1__ 1 // CHECK_BDVER1_M32: #define __SSE4_2__ 1 // CHECK_BDVER1_M32: #define __SSE_MATH__ 1 // CHECK_BDVER1_M32: #define __SSE__ 1 // CHECK_BDVER1_M32: #define __SSSE3__ 1 // CHECK_BDVER1_M32: #define __XOP__ 1 // CHECK_BDVER1_M32: #define __XSAVE__ 1 // CHECK_BDVER1_M32: #define __bdver1 1 // CHECK_BDVER1_M32: #define __bdver1__ 1 // CHECK_BDVER1_M32: #define __i386 1 // CHECK_BDVER1_M32: #define __i386__ 1 // CHECK_BDVER1_M32: #define __tune_bdver1__ 1 // RUN: %clang -march=bdver1 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER1_M64 // CHECK_BDVER1_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER1_M64-NOT: #define __3dNOW__ 1 // CHECK_BDVER1_M64: #define __AES__ 1 // CHECK_BDVER1_M64: #define __AVX__ 1 // CHECK_BDVER1_M64: #define __FMA4__ 1 // CHECK_BDVER1_M64: #define __LWP__ 1 // CHECK_BDVER1_M64: #define __LZCNT__ 1 // CHECK_BDVER1_M64: #define __MMX__ 1 // CHECK_BDVER1_M64: #define __PCLMUL__ 1 // CHECK_BDVER1_M64: #define __POPCNT__ 1 // CHECK_BDVER1_M64: #define __PRFCHW__ 1 // CHECK_BDVER1_M64: #define __SSE2_MATH__ 1 // CHECK_BDVER1_M64: #define __SSE2__ 1 // CHECK_BDVER1_M64: #define __SSE3__ 1 // CHECK_BDVER1_M64: #define __SSE4A__ 1 // CHECK_BDVER1_M64: #define __SSE4_1__ 1 // CHECK_BDVER1_M64: #define __SSE4_2__ 1 // CHECK_BDVER1_M64: #define __SSE_MATH__ 1 // CHECK_BDVER1_M64: #define __SSE__ 1 // CHECK_BDVER1_M64: #define __SSSE3__ 1 // CHECK_BDVER1_M64: #define __XOP__ 1 // CHECK_BDVER1_M64: #define __XSAVE__ 1 // CHECK_BDVER1_M64: #define __amd64 1 // CHECK_BDVER1_M64: #define __amd64__ 1 // CHECK_BDVER1_M64: #define __bdver1 1 // CHECK_BDVER1_M64: #define __bdver1__ 1 // CHECK_BDVER1_M64: #define __tune_bdver1__ 1 // CHECK_BDVER1_M64: #define __x86_64 1 // CHECK_BDVER1_M64: #define __x86_64__ 1 // RUN: %clang -march=bdver2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER2_M32 // CHECK_BDVER2_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER2_M32-NOT: #define __3dNOW__ 1 // CHECK_BDVER2_M32: #define __AES__ 1 // CHECK_BDVER2_M32: #define __AVX__ 1 // CHECK_BDVER2_M32: #define __BMI__ 1 // CHECK_BDVER2_M32: #define __F16C__ 1 // CHECK_BDVER2_M32: #define __FMA4__ 1 // CHECK_BDVER2_M32: #define __FMA__ 1 // CHECK_BDVER2_M32: #define __LWP__ 1 // CHECK_BDVER2_M32: #define __LZCNT__ 1 // CHECK_BDVER2_M32: #define __MMX__ 1 // CHECK_BDVER2_M32: #define __PCLMUL__ 1 // CHECK_BDVER2_M32: #define __POPCNT__ 1 // CHECK_BDVER2_M32: #define __PRFCHW__ 1 // CHECK_BDVER2_M32: #define __SSE2_MATH__ 1 // CHECK_BDVER2_M32: #define __SSE2__ 1 // CHECK_BDVER2_M32: #define __SSE3__ 1 // CHECK_BDVER2_M32: #define __SSE4A__ 1 // CHECK_BDVER2_M32: #define __SSE4_1__ 1 // CHECK_BDVER2_M32: #define __SSE4_2__ 1 // CHECK_BDVER2_M32: #define __SSE_MATH__ 1 // CHECK_BDVER2_M32: #define __SSE__ 1 // CHECK_BDVER2_M32: #define __SSSE3__ 1 // CHECK_BDVER2_M32: #define __TBM__ 1 // CHECK_BDVER2_M32: #define __XOP__ 1 // CHECK_BDVER2_M32: #define __XSAVE__ 1 // CHECK_BDVER2_M32: #define __bdver2 1 // CHECK_BDVER2_M32: #define __bdver2__ 1 // CHECK_BDVER2_M32: #define __i386 1 // CHECK_BDVER2_M32: #define __i386__ 1 // CHECK_BDVER2_M32: #define __tune_bdver2__ 1 // RUN: %clang -march=bdver2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER2_M64 // CHECK_BDVER2_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER2_M64-NOT: #define __3dNOW__ 1 // CHECK_BDVER2_M64: #define __AES__ 1 // CHECK_BDVER2_M64: #define __AVX__ 1 // CHECK_BDVER2_M64: #define __BMI__ 1 // CHECK_BDVER2_M64: #define __F16C__ 1 // CHECK_BDVER2_M64: #define __FMA4__ 1 // CHECK_BDVER2_M64: #define __FMA__ 1 // CHECK_BDVER2_M64: #define __LWP__ 1 // CHECK_BDVER2_M64: #define __LZCNT__ 1 // CHECK_BDVER2_M64: #define __MMX__ 1 // CHECK_BDVER2_M64: #define __PCLMUL__ 1 // CHECK_BDVER2_M64: #define __POPCNT__ 1 // CHECK_BDVER2_M64: #define __PRFCHW__ 1 // CHECK_BDVER2_M64: #define __SSE2_MATH__ 1 // CHECK_BDVER2_M64: #define __SSE2__ 1 // CHECK_BDVER2_M64: #define __SSE3__ 1 // CHECK_BDVER2_M64: #define __SSE4A__ 1 // CHECK_BDVER2_M64: #define __SSE4_1__ 1 // CHECK_BDVER2_M64: #define __SSE4_2__ 1 // CHECK_BDVER2_M64: #define __SSE_MATH__ 1 // CHECK_BDVER2_M64: #define __SSE__ 1 // CHECK_BDVER2_M64: #define __SSSE3__ 1 // CHECK_BDVER2_M64: #define __TBM__ 1 // CHECK_BDVER2_M64: #define __XOP__ 1 // CHECK_BDVER2_M64: #define __XSAVE__ 1 // CHECK_BDVER2_M64: #define __amd64 1 // CHECK_BDVER2_M64: #define __amd64__ 1 // CHECK_BDVER2_M64: #define __bdver2 1 // CHECK_BDVER2_M64: #define __bdver2__ 1 // CHECK_BDVER2_M64: #define __tune_bdver2__ 1 // CHECK_BDVER2_M64: #define __x86_64 1 // CHECK_BDVER2_M64: #define __x86_64__ 1 // RUN: %clang -march=bdver3 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER3_M32 // CHECK_BDVER3_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER3_M32-NOT: #define __3dNOW__ 1 // CHECK_BDVER3_M32: #define __AES__ 1 // CHECK_BDVER3_M32: #define __AVX__ 1 // CHECK_BDVER3_M32: #define __BMI__ 1 // CHECK_BDVER3_M32: #define __F16C__ 1 // CHECK_BDVER3_M32: #define __FMA4__ 1 // CHECK_BDVER3_M32: #define __FMA__ 1 // CHECK_BDVER3_M32: #define __FSGSBASE__ 1 // CHECK_BDVER3_M32: #define __LWP__ 1 // CHECK_BDVER3_M32: #define __LZCNT__ 1 // CHECK_BDVER3_M32: #define __MMX__ 1 // CHECK_BDVER3_M32: #define __PCLMUL__ 1 // CHECK_BDVER3_M32: #define __POPCNT__ 1 // CHECK_BDVER3_M32: #define __PRFCHW__ 1 // CHECK_BDVER3_M32: #define __SSE2_MATH__ 1 // CHECK_BDVER3_M32: #define __SSE2__ 1 // CHECK_BDVER3_M32: #define __SSE3__ 1 // CHECK_BDVER3_M32: #define __SSE4A__ 1 // CHECK_BDVER3_M32: #define __SSE4_1__ 1 // CHECK_BDVER3_M32: #define __SSE4_2__ 1 // CHECK_BDVER3_M32: #define __SSE_MATH__ 1 // CHECK_BDVER3_M32: #define __SSE__ 1 // CHECK_BDVER3_M32: #define __SSSE3__ 1 // CHECK_BDVER3_M32: #define __TBM__ 1 // CHECK_BDVER3_M32: #define __XOP__ 1 // CHECK_BDVER3_M32: #define __XSAVEOPT__ 1 // CHECK_BDVER3_M32: #define __XSAVE__ 1 // CHECK_BDVER3_M32: #define __bdver3 1 // CHECK_BDVER3_M32: #define __bdver3__ 1 // CHECK_BDVER3_M32: #define __i386 1 // CHECK_BDVER3_M32: #define __i386__ 1 // CHECK_BDVER3_M32: #define __tune_bdver3__ 1 // RUN: %clang -march=bdver3 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER3_M64 // CHECK_BDVER3_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER3_M64-NOT: #define __3dNOW__ 1 // CHECK_BDVER3_M64: #define __AES__ 1 // CHECK_BDVER3_M64: #define __AVX__ 1 // CHECK_BDVER3_M64: #define __BMI__ 1 // CHECK_BDVER3_M64: #define __F16C__ 1 // CHECK_BDVER3_M64: #define __FMA4__ 1 // CHECK_BDVER3_M64: #define __FMA__ 1 // CHECK_BDVER3_M64: #define __FSGSBASE__ 1 // CHECK_BDVER3_M64: #define __LWP__ 1 // CHECK_BDVER3_M64: #define __LZCNT__ 1 // CHECK_BDVER3_M64: #define __MMX__ 1 // CHECK_BDVER3_M64: #define __PCLMUL__ 1 // CHECK_BDVER3_M64: #define __POPCNT__ 1 // CHECK_BDVER3_M64: #define __PRFCHW__ 1 // CHECK_BDVER3_M64: #define __SSE2_MATH__ 1 // CHECK_BDVER3_M64: #define __SSE2__ 1 // CHECK_BDVER3_M64: #define __SSE3__ 1 // CHECK_BDVER3_M64: #define __SSE4A__ 1 // CHECK_BDVER3_M64: #define __SSE4_1__ 1 // CHECK_BDVER3_M64: #define __SSE4_2__ 1 // CHECK_BDVER3_M64: #define __SSE_MATH__ 1 // CHECK_BDVER3_M64: #define __SSE__ 1 // CHECK_BDVER3_M64: #define __SSSE3__ 1 // CHECK_BDVER3_M64: #define __TBM__ 1 // CHECK_BDVER3_M64: #define __XOP__ 1 // CHECK_BDVER3_M64: #define __XSAVEOPT__ 1 // CHECK_BDVER3_M64: #define __XSAVE__ 1 // CHECK_BDVER3_M64: #define __amd64 1 // CHECK_BDVER3_M64: #define __amd64__ 1 // CHECK_BDVER3_M64: #define __bdver3 1 // CHECK_BDVER3_M64: #define __bdver3__ 1 // CHECK_BDVER3_M64: #define __tune_bdver3__ 1 // CHECK_BDVER3_M64: #define __x86_64 1 // CHECK_BDVER3_M64: #define __x86_64__ 1 // RUN: %clang -march=bdver4 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER4_M32 // CHECK_BDVER4_M32-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER4_M32-NOT: #define __3dNOW__ 1 // CHECK_BDVER4_M32: #define __AES__ 1 // CHECK_BDVER4_M32: #define __AVX2__ 1 // CHECK_BDVER4_M32: #define __AVX__ 1 // CHECK_BDVER4_M32: #define __BMI2__ 1 // CHECK_BDVER4_M32: #define __BMI__ 1 // CHECK_BDVER4_M32: #define __F16C__ 1 // CHECK_BDVER4_M32: #define __FMA4__ 1 // CHECK_BDVER4_M32: #define __FMA__ 1 // CHECK_BDVER4_M32: #define __FSGSBASE__ 1 // CHECK_BDVER4_M32: #define __LWP__ 1 // CHECK_BDVER4_M32: #define __LZCNT__ 1 // CHECK_BDVER4_M32: #define __MMX__ 1 // CHECK_BDVER4_M32: #define __PCLMUL__ 1 // CHECK_BDVER4_M32: #define __POPCNT__ 1 // CHECK_BDVER4_M32: #define __PRFCHW__ 1 // CHECK_BDVER4_M32: #define __SSE2_MATH__ 1 // CHECK_BDVER4_M32: #define __SSE2__ 1 // CHECK_BDVER4_M32: #define __SSE3__ 1 // CHECK_BDVER4_M32: #define __SSE4A__ 1 // CHECK_BDVER4_M32: #define __SSE4_1__ 1 // CHECK_BDVER4_M32: #define __SSE4_2__ 1 // CHECK_BDVER4_M32: #define __SSE_MATH__ 1 // CHECK_BDVER4_M32: #define __SSE__ 1 // CHECK_BDVER4_M32: #define __SSSE3__ 1 // CHECK_BDVER4_M32: #define __TBM__ 1 // CHECK_BDVER4_M32: #define __XOP__ 1 // CHECK_BDVER4_M32: #define __XSAVE__ 1 // CHECK_BDVER4_M32: #define __bdver4 1 // CHECK_BDVER4_M32: #define __bdver4__ 1 // CHECK_BDVER4_M32: #define __i386 1 // CHECK_BDVER4_M32: #define __i386__ 1 // CHECK_BDVER4_M32: #define __tune_bdver4__ 1 // RUN: %clang -march=bdver4 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_BDVER4_M64 // CHECK_BDVER4_M64-NOT: #define __3dNOW_A__ 1 // CHECK_BDVER4_M64-NOT: #define __3dNOW__ 1 // CHECK_BDVER4_M64: #define __AES__ 1 // CHECK_BDVER4_M64: #define __AVX2__ 1 // CHECK_BDVER4_M64: #define __AVX__ 1 // CHECK_BDVER4_M64: #define __BMI2__ 1 // CHECK_BDVER4_M64: #define __BMI__ 1 // CHECK_BDVER4_M64: #define __F16C__ 1 // CHECK_BDVER4_M64: #define __FMA4__ 1 // CHECK_BDVER4_M64: #define __FMA__ 1 // CHECK_BDVER4_M64: #define __FSGSBASE__ 1 // CHECK_BDVER4_M64: #define __LWP__ 1 // CHECK_BDVER4_M64: #define __LZCNT__ 1 // CHECK_BDVER4_M64: #define __MMX__ 1 // CHECK_BDVER4_M64: #define __PCLMUL__ 1 // CHECK_BDVER4_M64: #define __POPCNT__ 1 // CHECK_BDVER4_M64: #define __PRFCHW__ 1 // CHECK_BDVER4_M64: #define __SSE2_MATH__ 1 // CHECK_BDVER4_M64: #define __SSE2__ 1 // CHECK_BDVER4_M64: #define __SSE3__ 1 // CHECK_BDVER4_M64: #define __SSE4A__ 1 // CHECK_BDVER4_M64: #define __SSE4_1__ 1 // CHECK_BDVER4_M64: #define __SSE4_2__ 1 // CHECK_BDVER4_M64: #define __SSE_MATH__ 1 // CHECK_BDVER4_M64: #define __SSE__ 1 // CHECK_BDVER4_M64: #define __SSSE3__ 1 // CHECK_BDVER4_M64: #define __TBM__ 1 // CHECK_BDVER4_M64: #define __XOP__ 1 // CHECK_BDVER4_M64: #define __XSAVE__ 1 // CHECK_BDVER4_M64: #define __amd64 1 // CHECK_BDVER4_M64: #define __amd64__ 1 // CHECK_BDVER4_M64: #define __bdver4 1 // CHECK_BDVER4_M64: #define __bdver4__ 1 // CHECK_BDVER4_M64: #define __tune_bdver4__ 1 // CHECK_BDVER4_M64: #define __x86_64 1 // CHECK_BDVER4_M64: #define __x86_64__ 1 // RUN: %clang -march=znver1 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M32 // CHECK_ZNVER1_M32-NOT: #define __3dNOW_A__ 1 // CHECK_ZNVER1_M32-NOT: #define __3dNOW__ 1 // CHECK_ZNVER1_M32: #define __ADX__ 1 // CHECK_ZNVER1_M32: #define __AES__ 1 // CHECK_ZNVER1_M32: #define __AVX2__ 1 // CHECK_ZNVER1_M32: #define __AVX__ 1 // CHECK_ZNVER1_M32: #define __BMI2__ 1 // CHECK_ZNVER1_M32: #define __BMI__ 1 // CHECK_ZNVER1_M32: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER1_M32: #define __CLZERO__ 1 // CHECK_ZNVER1_M32: #define __F16C__ 1 // CHECK_ZNVER1_M32: #define __FMA__ 1 // CHECK_ZNVER1_M32: #define __FSGSBASE__ 1 // CHECK_ZNVER1_M32: #define __LZCNT__ 1 // CHECK_ZNVER1_M32: #define __MMX__ 1 // CHECK_ZNVER1_M32: #define __MOVBE__ 1 // CHECK_ZNVER1_M32: #define __PCLMUL__ 1 // CHECK_ZNVER1_M32: #define __POPCNT__ 1 // CHECK_ZNVER1_M32: #define __PRFCHW__ 1 // CHECK_ZNVER1_M32: #define __RDRND__ 1 // CHECK_ZNVER1_M32: #define __RDSEED__ 1 // CHECK_ZNVER1_M32: #define __SHA__ 1 // CHECK_ZNVER1_M32: #define __SSE2_MATH__ 1 // CHECK_ZNVER1_M32: #define __SSE2__ 1 // CHECK_ZNVER1_M32: #define __SSE3__ 1 // CHECK_ZNVER1_M32: #define __SSE4A__ 1 // CHECK_ZNVER1_M32: #define __SSE4_1__ 1 // CHECK_ZNVER1_M32: #define __SSE4_2__ 1 // CHECK_ZNVER1_M32: #define __SSE_MATH__ 1 // CHECK_ZNVER1_M32: #define __SSE__ 1 // CHECK_ZNVER1_M32: #define __SSSE3__ 1 // CHECK_ZNVER1_M32: #define __XSAVEC__ 1 // CHECK_ZNVER1_M32: #define __XSAVEOPT__ 1 // CHECK_ZNVER1_M32: #define __XSAVES__ 1 // CHECK_ZNVER1_M32: #define __XSAVE__ 1 // CHECK_ZNVER1_M32: #define __i386 1 // CHECK_ZNVER1_M32: #define __i386__ 1 // CHECK_ZNVER1_M32: #define __tune_znver1__ 1 // CHECK_ZNVER1_M32: #define __znver1 1 // CHECK_ZNVER1_M32: #define __znver1__ 1 // RUN: %clang -march=znver1 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M64 // CHECK_ZNVER1_M64-NOT: #define __3dNOW_A__ 1 // CHECK_ZNVER1_M64-NOT: #define __3dNOW__ 1 // CHECK_ZNVER1_M64: #define __ADX__ 1 // CHECK_ZNVER1_M64: #define __AES__ 1 // CHECK_ZNVER1_M64: #define __AVX2__ 1 // CHECK_ZNVER1_M64: #define __AVX__ 1 // CHECK_ZNVER1_M64: #define __BMI2__ 1 // CHECK_ZNVER1_M64: #define __BMI__ 1 // CHECK_ZNVER1_M64: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER1_M64: #define __CLZERO__ 1 // CHECK_ZNVER1_M64: #define __F16C__ 1 // CHECK_ZNVER1_M64: #define __FMA__ 1 // CHECK_ZNVER1_M64: #define __FSGSBASE__ 1 // CHECK_ZNVER1_M64: #define __LZCNT__ 1 // CHECK_ZNVER1_M64: #define __MMX__ 1 // CHECK_ZNVER1_M64: #define __MOVBE__ 1 // CHECK_ZNVER1_M64: #define __PCLMUL__ 1 // CHECK_ZNVER1_M64: #define __POPCNT__ 1 // CHECK_ZNVER1_M64: #define __PRFCHW__ 1 // CHECK_ZNVER1_M64: #define __RDRND__ 1 // CHECK_ZNVER1_M64: #define __RDSEED__ 1 // CHECK_ZNVER1_M64: #define __SHA__ 1 // CHECK_ZNVER1_M64: #define __SSE2_MATH__ 1 // CHECK_ZNVER1_M64: #define __SSE2__ 1 // CHECK_ZNVER1_M64: #define __SSE3__ 1 // CHECK_ZNVER1_M64: #define __SSE4A__ 1 // CHECK_ZNVER1_M64: #define __SSE4_1__ 1 // CHECK_ZNVER1_M64: #define __SSE4_2__ 1 // CHECK_ZNVER1_M64: #define __SSE_MATH__ 1 // CHECK_ZNVER1_M64: #define __SSE__ 1 // CHECK_ZNVER1_M64: #define __SSSE3__ 1 // CHECK_ZNVER1_M64: #define __XSAVEC__ 1 // CHECK_ZNVER1_M64: #define __XSAVEOPT__ 1 // CHECK_ZNVER1_M64: #define __XSAVES__ 1 // CHECK_ZNVER1_M64: #define __XSAVE__ 1 // CHECK_ZNVER1_M64: #define __amd64 1 // CHECK_ZNVER1_M64: #define __amd64__ 1 // CHECK_ZNVER1_M64: #define __tune_znver1__ 1 // CHECK_ZNVER1_M64: #define __x86_64 1 // CHECK_ZNVER1_M64: #define __x86_64__ 1 // CHECK_ZNVER1_M64: #define __znver1 1 // CHECK_ZNVER1_M64: #define __znver1__ 1 // RUN: %clang -march=znver2 -m32 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M32 // CHECK_ZNVER2_M32-NOT: #define __3dNOW_A__ 1 // CHECK_ZNVER2_M32-NOT: #define __3dNOW__ 1 // CHECK_ZNVER2_M32: #define __ADX__ 1 // CHECK_ZNVER2_M32: #define __AES__ 1 // CHECK_ZNVER2_M32: #define __AVX2__ 1 // CHECK_ZNVER2_M32: #define __AVX__ 1 // CHECK_ZNVER2_M32: #define __BMI2__ 1 // CHECK_ZNVER2_M32: #define __BMI__ 1 // CHECK_ZNVER2_M32: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER2_M32: #define __CLWB__ 1 // CHECK_ZNVER2_M32: #define __CLZERO__ 1 // CHECK_ZNVER2_M32: #define __F16C__ 1 // CHECK_ZNVER2_M32: #define __FMA__ 1 // CHECK_ZNVER2_M32: #define __FSGSBASE__ 1 // CHECK_ZNVER2_M32: #define __LZCNT__ 1 // CHECK_ZNVER2_M32: #define __MMX__ 1 // CHECK_ZNVER2_M32: #define __PCLMUL__ 1 // CHECK_ZNVER2_M32: #define __POPCNT__ 1 // CHECK_ZNVER2_M32: #define __PRFCHW__ 1 // CHECK_ZNVER2_M32: #define __RDPID__ 1 // CHECK_ZNVER2_M32: #define __RDRND__ 1 // CHECK_ZNVER2_M32: #define __RDSEED__ 1 // CHECK_ZNVER2_M32: #define __SHA__ 1 // CHECK_ZNVER2_M32: #define __SSE2_MATH__ 1 // CHECK_ZNVER2_M32: #define __SSE2__ 1 // CHECK_ZNVER2_M32: #define __SSE3__ 1 // CHECK_ZNVER2_M32: #define __SSE4A__ 1 // CHECK_ZNVER2_M32: #define __SSE4_1__ 1 // CHECK_ZNVER2_M32: #define __SSE4_2__ 1 // CHECK_ZNVER2_M32: #define __SSE_MATH__ 1 // CHECK_ZNVER2_M32: #define __SSE__ 1 // CHECK_ZNVER2_M32: #define __SSSE3__ 1 // CHECK_ZNVER2_M32: #define __WBNOINVD__ 1 // CHECK_ZNVER2_M32: #define __XSAVEC__ 1 // CHECK_ZNVER2_M32: #define __XSAVEOPT__ 1 // CHECK_ZNVER2_M32: #define __XSAVES__ 1 // CHECK_ZNVER2_M32: #define __XSAVE__ 1 // CHECK_ZNVER2_M32: #define __i386 1 // CHECK_ZNVER2_M32: #define __i386__ 1 // CHECK_ZNVER2_M32: #define __tune_znver2__ 1 // CHECK_ZNVER2_M32: #define __znver2 1 // CHECK_ZNVER2_M32: #define __znver2__ 1 // RUN: %clang -march=znver2 -m64 -E -dM %s -o - 2>&1 \ // RUN: -target i386-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER2_M64 // CHECK_ZNVER2_M64-NOT: #define __3dNOW_A__ 1 // CHECK_ZNVER2_M64-NOT: #define __3dNOW__ 1 // CHECK_ZNVER2_M64: #define __ADX__ 1 // CHECK_ZNVER2_M64: #define __AES__ 1 // CHECK_ZNVER2_M64: #define __AVX2__ 1 // CHECK_ZNVER2_M64: #define __AVX__ 1 // CHECK_ZNVER2_M64: #define __BMI2__ 1 // CHECK_ZNVER2_M64: #define __BMI__ 1 // CHECK_ZNVER2_M64: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER2_M64: #define __CLWB__ 1 // CHECK_ZNVER2_M64: #define __CLZERO__ 1 // CHECK_ZNVER2_M64: #define __F16C__ 1 // CHECK_ZNVER2_M64: #define __FMA__ 1 // CHECK_ZNVER2_M64: #define __FSGSBASE__ 1 // CHECK_ZNVER2_M64: #define __LZCNT__ 1 // CHECK_ZNVER2_M64: #define __MMX__ 1 // CHECK_ZNVER2_M64: #define __PCLMUL__ 1 // CHECK_ZNVER2_M64: #define __POPCNT__ 1 // CHECK_ZNVER2_M64: #define __PRFCHW__ 1 // CHECK_ZNVER2_M64: #define __RDPID__ 1 // CHECK_ZNVER2_M64: #define __RDRND__ 1 // CHECK_ZNVER2_M64: #define __RDSEED__ 1 // CHECK_ZNVER2_M64: #define __SHA__ 1 // CHECK_ZNVER2_M64: #define __SSE2_MATH__ 1 // CHECK_ZNVER2_M64: #define __SSE2__ 1 // CHECK_ZNVER2_M64: #define __SSE3__ 1 // CHECK_ZNVER2_M64: #define __SSE4A__ 1 // CHECK_ZNVER2_M64: #define __SSE4_1__ 1 // CHECK_ZNVER2_M64: #define __SSE4_2__ 1 // CHECK_ZNVER2_M64: #define __SSE_MATH__ 1 // CHECK_ZNVER2_M64: #define __SSE__ 1 // CHECK_ZNVER2_M64: #define __SSSE3__ 1 // CHECK_ZNVER2_M64: #define __WBNOINVD__ 1 // CHECK_ZNVER2_M64: #define __XSAVEC__ 1 // CHECK_ZNVER2_M64: #define __XSAVEOPT__ 1 // CHECK_ZNVER2_M64: #define __XSAVES__ 1 // CHECK_ZNVER2_M64: #define __XSAVE__ 1 // CHECK_ZNVER2_M64: #define __amd64 1 // CHECK_ZNVER2_M64: #define __amd64__ 1 // CHECK_ZNVER2_M64: #define __tune_znver2__ 1 // CHECK_ZNVER2_M64: #define __x86_64 1 // CHECK_ZNVER2_M64: #define __x86_64__ 1 // CHECK_ZNVER2_M64: #define __znver2 1 // CHECK_ZNVER2_M64: #define __znver2__ 1 // End X86/GCC/Linux tests ------------------ // Begin PPC/GCC/Linux tests ---------------- // Check that VSX also turns on altivec. // RUN: %clang -mvsx -E -dM %s -o - 2>&1 \ // RUN: -target powerpc-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_VSX_M32 // CHECK_PPC_VSX_M32: #define __ALTIVEC__ 1 // CHECK_PPC_VSX_M32: #define __VSX__ 1 // RUN: %clang -mvsx -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_VSX_M64 // CHECK_PPC_VSX_M64: #define __VSX__ 1 // RUN: %clang -mpower8-vector -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_POWER8_VECTOR_M64 // CHECK_PPC_POWER8_VECTOR_M64: #define __POWER8_VECTOR__ 1 // RUN: %clang -mpower9-vector -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_POWER9_VECTOR_M64 // CHECK_PPC_POWER9_VECTOR_M64: #define __POWER9_VECTOR__ 1 // RUN: %clang -mcrypto -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_CRYPTO_M64 // CHECK_PPC_CRYPTO_M64: #define __CRYPTO__ 1 // HTM is available on power8 or later which includes all of powerpc64le as an // ABI choice. Test that, the cpus, and the option. // RUN: %clang -mhtm -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64le-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM // RUN: %clang -mcpu=pwr8 -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM // RUN: %clang -mcpu=pwr9 -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_HTM // CHECK_PPC_HTM: #define __HTM__ 1 // RUN: %clang -mcpu=ppc64 -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-unknown \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS // RUN: %clang -mcpu=pwr8 -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64-unknown-unknown \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target powerpc64le-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // End PPC/GCC/Linux tests ------------------ // Begin Sparc/GCC/Linux tests ---------------- // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target sparc-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC // CHECK_SPARC: #define __BIG_ENDIAN__ 1 // CHECK_SPARC: #define __sparc 1 // CHECK_SPARC: #define __sparc__ 1 // CHECK_SPARC-NOT: #define __sparcv9 1 // CHECK_SPARC-NOT: #define __sparcv9__ 1 // CHECK_SPARC: #define __sparcv8 1 // CHECK_SPARC-NOT: #define __sparcv9 1 // CHECK_SPARC-NOT: #define __sparcv9__ 1 // RUN: %clang -mcpu=v9 -E -dM %s -o - 2>&1 \ // RUN: -target sparc-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC-V9 // CHECK_SPARC-V9-NOT: #define __sparcv8 1 // CHECK_SPARC-V9: #define __sparc_v9__ 1 // CHECK_SPARC-V9: #define __sparcv9 1 // CHECK_SPARC-V9-NOT: #define __sparcv8 1 // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target sparcel-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARCEL // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.1 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-1 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.2 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=myriad2.3 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2100 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-1 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2150 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2155 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2450 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2455 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2x5x 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-2 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2080 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2085 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2480 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2485 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // RUN: %clang -E -dM %s -o - -target sparcel-myriad -mcpu=ma2x8x 2>&1 \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_MYRIAD2-3 \ // RUN: -check-prefix=CHECK_SPARCEL -check-prefix=CHECK_MYRIAD2 // CHECK_SPARCEL: #define __LITTLE_ENDIAN__ 1 // CHECK_MYRIAD2: #define __leon__ 1 // CHECK_MYRIAD2-1: #define __myriad2 1 // CHECK_MYRIAD2-1: #define __myriad2__ 1 // CHECK_MYRIAD2-2: #define __ma2x5x 1 // CHECK_MYRIAD2-2: #define __ma2x5x__ 1 // CHECK_MYRIAD2-2: #define __myriad2 2 // CHECK_MYRIAD2-2: #define __myriad2__ 2 // CHECK_MYRIAD2-3: #define __ma2x8x 1 // CHECK_MYRIAD2-3: #define __ma2x8x__ 1 // CHECK_MYRIAD2-3: #define __myriad2 3 // CHECK_MYRIAD2-3: #define __myriad2__ 3 // CHECK_SPARCEL: #define __sparc 1 // CHECK_SPARCEL: #define __sparc__ 1 // CHECK_MYRIAD2: #define __sparc_v8__ 1 // CHECK_SPARCEL: #define __sparcv8 1 // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target sparcv9-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARCV9 // CHECK_SPARCV9: #define __BIG_ENDIAN__ 1 // CHECK_SPARCV9: #define __sparc 1 // CHECK_SPARCV9: #define __sparc64__ 1 // CHECK_SPARCV9: #define __sparc__ 1 // CHECK_SPARCV9: #define __sparc_v9__ 1 // CHECK_SPARCV9: #define __sparcv9 1 // CHECK_SPARCV9: #define __sparcv9__ 1 // Begin SystemZ/GCC/Linux tests ---------------- // RUN: %clang -march=arch8 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH8 // RUN: %clang -march=z10 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH8 // CHECK_SYSTEMZ_ARCH8: #define __ARCH__ 8 // CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH8: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH8: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH8: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH8: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH8: #define __zarch__ 1 // RUN: %clang -march=arch9 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH9 // RUN: %clang -march=z196 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH9 // CHECK_SYSTEMZ_ARCH9: #define __ARCH__ 9 // CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH9: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH9: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH9: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH9: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH9: #define __zarch__ 1 // RUN: %clang -march=arch10 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH10 // RUN: %clang -march=zEC12 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH10 // CHECK_SYSTEMZ_ARCH10: #define __ARCH__ 10 // CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH10: #define __HTM__ 1 // CHECK_SYSTEMZ_ARCH10: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH10: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH10: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH10: #define __zarch__ 1 // RUN: %clang -march=arch11 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH11 // RUN: %clang -march=z13 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH11 // CHECK_SYSTEMZ_ARCH11: #define __ARCH__ 11 // CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH11: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH11: #define __HTM__ 1 // CHECK_SYSTEMZ_ARCH11: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH11: #define __VX__ 1 // CHECK_SYSTEMZ_ARCH11: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH11: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH11: #define __zarch__ 1 // RUN: %clang -march=arch12 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH12 // RUN: %clang -march=z14 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH12 // CHECK_SYSTEMZ_ARCH12: #define __ARCH__ 12 // CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH12: #define __HTM__ 1 // CHECK_SYSTEMZ_ARCH12: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH12: #define __VX__ 1 // CHECK_SYSTEMZ_ARCH12: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH12: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH12: #define __zarch__ 1 // RUN: %clang -march=arch13 -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH13 // CHECK_SYSTEMZ_ARCH13: #define __ARCH__ 13 // CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 // CHECK_SYSTEMZ_ARCH13: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1 // CHECK_SYSTEMZ_ARCH13: #define __HTM__ 1 // CHECK_SYSTEMZ_ARCH13: #define __LONG_DOUBLE_128__ 1 // CHECK_SYSTEMZ_ARCH13: #define __VX__ 1 // CHECK_SYSTEMZ_ARCH13: #define __s390__ 1 // CHECK_SYSTEMZ_ARCH13: #define __s390x__ 1 // CHECK_SYSTEMZ_ARCH13: #define __zarch__ 1 // RUN: %clang -mhtm -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_HTM // CHECK_SYSTEMZ_HTM: #define __HTM__ 1 // RUN: %clang -mvx -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_VX // CHECK_SYSTEMZ_VX: #define __VX__ 1 // RUN: %clang -fzvector -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR // RUN: %clang -mzvector -E -dM %s -o - 2>&1 \ // RUN: -target s390x-unknown-linux \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZVECTOR // CHECK_SYSTEMZ_ZVECTOR: #define __VEC__ 10303 // Begin amdgcn tests ---------------- // RUN: %clang -march=amdgcn -E -dM %s -o - 2>&1 \ // RUN: -target amdgcn-unknown-unknown \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_AMDGCN // CHECK_AMDGCN: #define __AMDGCN__ 1 // CHECK_AMDGCN: #define __HAS_FMAF__ 1 // CHECK_AMDGCN: #define __HAS_FP64__ 1 // CHECK_AMDGCN: #define __HAS_LDEXPF__ 1 // Begin r600 tests ---------------- // RUN: %clang -march=amdgcn -E -dM %s -o - 2>&1 \ // RUN: -target r600-unknown-unknown \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_R600 // CHECK_R600: #define __R600__ 1 // CHECK_R600-NOT: #define __HAS_FMAF__ 1 // RUN: %clang -march=amdgcn -mcpu=cypress -E -dM %s -o - 2>&1 \ // RUN: -target r600-unknown-unknown \ // RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_R600_FP64 // CHECK_R600_FP64-DAG: #define __R600__ 1 // CHECK_R600_FP64-DAG: #define __HAS_FMAF__ 1 diff --git a/llvm/include/llvm/Support/X86TargetParser.def b/llvm/include/llvm/Support/X86TargetParser.def index 1749be3b3ae2..a4ed8ee21c96 100644 --- a/llvm/include/llvm/Support/X86TargetParser.def +++ b/llvm/include/llvm/Support/X86TargetParser.def @@ -1,171 +1,173 @@ //===- X86TargetParser.def - X86 target parsing defines ---------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file provides defines to build up the X86 target parser's logic. // //===----------------------------------------------------------------------===// // NOTE: NO INCLUDE GUARD DESIRED! #ifndef X86_VENDOR #define X86_VENDOR(ENUM, STR) #endif X86_VENDOR(VENDOR_INTEL, "intel") X86_VENDOR(VENDOR_AMD, "amd") #undef X86_VENDOR // This macro is used to implement CPU types that have an alias. As of now // there is only ever one alias. #ifndef X86_CPU_TYPE_COMPAT_WITH_ALIAS #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) #endif // This macro is used for cpu types present in compiler-rt/libgcc. #ifndef X86_CPU_TYPE_COMPAT #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) X86_CPU_TYPE(ARCHNAME, ENUM) #endif #ifndef X86_CPU_TYPE #define X86_CPU_TYPE(ARCHNAME, ENUM) #endif // The first part of this list must match what is implemented in libgcc and // compilert-rt. Clang uses this to know how to implement __builtin_cpu_is. X86_CPU_TYPE_COMPAT_WITH_ALIAS("bonnell", INTEL_BONNELL, "bonnell", "atom") X86_CPU_TYPE_COMPAT ("core2", INTEL_CORE2, "core2") X86_CPU_TYPE_COMPAT ("nehalem", INTEL_COREI7, "corei7") X86_CPU_TYPE_COMPAT_WITH_ALIAS("amdfam10", AMDFAM10H, "amdfam10h", "amdfam10") X86_CPU_TYPE_COMPAT_WITH_ALIAS("bdver1", AMDFAM15H, "amdfam15h", "amdfam15") X86_CPU_TYPE_COMPAT_WITH_ALIAS("silvermont", INTEL_SILVERMONT, "silvermont", "slm") X86_CPU_TYPE_COMPAT ("knl", INTEL_KNL, "knl") X86_CPU_TYPE_COMPAT ("btver1", AMD_BTVER1, "btver1") X86_CPU_TYPE_COMPAT ("btver2", AMD_BTVER2, "btver2") X86_CPU_TYPE_COMPAT ("znver1", AMDFAM17H, "amdfam17h") X86_CPU_TYPE_COMPAT ("knm", INTEL_KNM, "knm") X86_CPU_TYPE_COMPAT ("goldmont", INTEL_GOLDMONT, "goldmont") X86_CPU_TYPE_COMPAT ("goldmont-plus", INTEL_GOLDMONT_PLUS, "goldmont-plus") X86_CPU_TYPE_COMPAT ("tremont", INTEL_TREMONT, "tremont") // Entries below this are not in libgcc/compiler-rt. X86_CPU_TYPE ("i386", INTEL_i386) X86_CPU_TYPE ("i486", INTEL_i486) X86_CPU_TYPE ("pentium", INTEL_PENTIUM) X86_CPU_TYPE ("pentium-mmx", INTEL_PENTIUM_MMX) X86_CPU_TYPE ("pentiumpro", INTEL_PENTIUM_PRO) X86_CPU_TYPE ("pentium2", INTEL_PENTIUM_II) X86_CPU_TYPE ("pentium3", INTEL_PENTIUM_III) X86_CPU_TYPE ("pentium4", INTEL_PENTIUM_IV) X86_CPU_TYPE ("pentium-m", INTEL_PENTIUM_M) X86_CPU_TYPE ("yonah", INTEL_CORE_DUO) X86_CPU_TYPE ("nocona", INTEL_NOCONA) X86_CPU_TYPE ("prescott", INTEL_PRESCOTT) X86_CPU_TYPE ("i486", AMD_i486) X86_CPU_TYPE ("pentium", AMDPENTIUM) X86_CPU_TYPE ("athlon", AMD_ATHLON) X86_CPU_TYPE ("athlon-xp", AMD_ATHLON_XP) X86_CPU_TYPE ("k8", AMD_K8) X86_CPU_TYPE ("k8-sse3", AMD_K8SSE3) #undef X86_CPU_TYPE_COMPAT_WITH_ALIAS #undef X86_CPU_TYPE_COMPAT #undef X86_CPU_TYPE // This macro is used for cpu subtypes present in compiler-rt/libgcc. #ifndef X86_CPU_SUBTYPE_COMPAT #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) X86_CPU_SUBTYPE(ARCHNAME, ENUM) #endif #ifndef X86_CPU_SUBTYPE #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) #endif // The first part of this list must match what is implemented in libgcc and // compilert-rt. Clang uses this to know how to implement __builtin_cpu_is. X86_CPU_SUBTYPE_COMPAT("nehalem", INTEL_COREI7_NEHALEM, "nehalem") X86_CPU_SUBTYPE_COMPAT("westmere", INTEL_COREI7_WESTMERE, "westmere") X86_CPU_SUBTYPE_COMPAT("sandybridge", INTEL_COREI7_SANDYBRIDGE, "sandybridge") X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_BARCELONA, "barcelona") X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_SHANGHAI, "shanghai") X86_CPU_SUBTYPE_COMPAT("amdfam10", AMDFAM10H_ISTANBUL, "istanbul") X86_CPU_SUBTYPE_COMPAT("bdver1", AMDFAM15H_BDVER1, "bdver1") X86_CPU_SUBTYPE_COMPAT("bdver2", AMDFAM15H_BDVER2, "bdver2") X86_CPU_SUBTYPE_COMPAT("bdver3", AMDFAM15H_BDVER3, "bdver3") X86_CPU_SUBTYPE_COMPAT("bdver4", AMDFAM15H_BDVER4, "bdver4") X86_CPU_SUBTYPE_COMPAT("znver1", AMDFAM17H_ZNVER1, "znver1") X86_CPU_SUBTYPE_COMPAT("ivybridge", INTEL_COREI7_IVYBRIDGE, "ivybridge") X86_CPU_SUBTYPE_COMPAT("haswell", INTEL_COREI7_HASWELL, "haswell") X86_CPU_SUBTYPE_COMPAT("broadwell", INTEL_COREI7_BROADWELL, "broadwell") X86_CPU_SUBTYPE_COMPAT("skylake", INTEL_COREI7_SKYLAKE, "skylake") X86_CPU_SUBTYPE_COMPAT("skylake-avx512", INTEL_COREI7_SKYLAKE_AVX512, "skylake-avx512") X86_CPU_SUBTYPE_COMPAT("cannonlake", INTEL_COREI7_CANNONLAKE, "cannonlake") X86_CPU_SUBTYPE_COMPAT("icelake-client", INTEL_COREI7_ICELAKE_CLIENT, "icelake-client") X86_CPU_SUBTYPE_COMPAT("icelake-server", INTEL_COREI7_ICELAKE_SERVER, "icelake-server") X86_CPU_SUBTYPE_COMPAT("znver2", AMDFAM17H_ZNVER2, "znver2") X86_CPU_SUBTYPE_COMPAT("cascadelake", INTEL_COREI7_CASCADELAKE, "cascadelake") // Entries below this are not in libgcc/compiler-rt. X86_CPU_SUBTYPE ("core2", INTEL_CORE2_65) X86_CPU_SUBTYPE ("penryn", INTEL_CORE2_45) X86_CPU_SUBTYPE ("k6", AMDPENTIUM_K6) X86_CPU_SUBTYPE ("k6-2", AMDPENTIUM_K62) X86_CPU_SUBTYPE ("k6-3", AMDPENTIUM_K63) X86_CPU_SUBTYPE ("geode", AMDPENTIUM_GEODE) X86_CPU_SUBTYPE ("cooperlake", INTEL_COREI7_COOPERLAKE) +X86_CPU_SUBTYPE ("tigerlake", INTEL_COREI7_TIGERLAKE) #undef X86_CPU_SUBTYPE_COMPAT #undef X86_CPU_SUBTYPE // This macro is used for cpu types present in compiler-rt/libgcc. #ifndef X86_FEATURE_COMPAT #define X86_FEATURE_COMPAT(VAL, ENUM, STR) X86_FEATURE(VAL, ENUM) #endif #ifndef X86_FEATURE #define X86_FEATURE(VAL, ENUM) #endif X86_FEATURE_COMPAT( 0, FEATURE_CMOV, "cmov") X86_FEATURE_COMPAT( 1, FEATURE_MMX, "mmx") X86_FEATURE_COMPAT( 2, FEATURE_POPCNT, "popcnt") X86_FEATURE_COMPAT( 3, FEATURE_SSE, "sse") X86_FEATURE_COMPAT( 4, FEATURE_SSE2, "sse2") X86_FEATURE_COMPAT( 5, FEATURE_SSE3, "sse3") X86_FEATURE_COMPAT( 6, FEATURE_SSSE3, "ssse3") X86_FEATURE_COMPAT( 7, FEATURE_SSE4_1, "sse4.1") X86_FEATURE_COMPAT( 8, FEATURE_SSE4_2, "sse4.2") X86_FEATURE_COMPAT( 9, FEATURE_AVX, "avx") X86_FEATURE_COMPAT(10, FEATURE_AVX2, "avx2") X86_FEATURE_COMPAT(11, FEATURE_SSE4_A, "sse4a") X86_FEATURE_COMPAT(12, FEATURE_FMA4, "fma4") X86_FEATURE_COMPAT(13, FEATURE_XOP, "xop") X86_FEATURE_COMPAT(14, FEATURE_FMA, "fma") X86_FEATURE_COMPAT(15, FEATURE_AVX512F, "avx512f") X86_FEATURE_COMPAT(16, FEATURE_BMI, "bmi") X86_FEATURE_COMPAT(17, FEATURE_BMI2, "bmi2") X86_FEATURE_COMPAT(18, FEATURE_AES, "aes") X86_FEATURE_COMPAT(19, FEATURE_PCLMUL, "pclmul") X86_FEATURE_COMPAT(20, FEATURE_AVX512VL, "avx512vl") X86_FEATURE_COMPAT(21, FEATURE_AVX512BW, "avx512bw") X86_FEATURE_COMPAT(22, FEATURE_AVX512DQ, "avx512dq") X86_FEATURE_COMPAT(23, FEATURE_AVX512CD, "avx512cd") X86_FEATURE_COMPAT(24, FEATURE_AVX512ER, "avx512er") X86_FEATURE_COMPAT(25, FEATURE_AVX512PF, "avx512pf") X86_FEATURE_COMPAT(26, FEATURE_AVX512VBMI, "avx512vbmi") X86_FEATURE_COMPAT(27, FEATURE_AVX512IFMA, "avx512ifma") X86_FEATURE_COMPAT(28, FEATURE_AVX5124VNNIW, "avx5124vnniw") X86_FEATURE_COMPAT(29, FEATURE_AVX5124FMAPS, "avx5124fmaps") X86_FEATURE_COMPAT(30, FEATURE_AVX512VPOPCNTDQ, "avx512vpopcntdq") X86_FEATURE_COMPAT(31, FEATURE_AVX512VBMI2, "avx512vbmi2") X86_FEATURE_COMPAT(32, FEATURE_GFNI, "gfni") X86_FEATURE_COMPAT(33, FEATURE_VPCLMULQDQ, "vpclmulqdq") X86_FEATURE_COMPAT(34, FEATURE_AVX512VNNI, "avx512vnni") X86_FEATURE_COMPAT(35, FEATURE_AVX512BITALG, "avx512bitalg") // Features below here are not in libgcc/compiler-rt. X86_FEATURE (64, FEATURE_MOVBE) X86_FEATURE (65, FEATURE_ADX) X86_FEATURE (66, FEATURE_EM64T) X86_FEATURE (67, FEATURE_CLFLUSHOPT) X86_FEATURE (68, FEATURE_SHA) X86_FEATURE (69, FEATURE_AVX512BF16) +X86_FEATURE (70, FEATURE_AVX512VP2INTERSECT) #undef X86_FEATURE_COMPAT #undef X86_FEATURE diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index 3ad1495957bf..836b363efd9a 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -1,1516 +1,1525 @@ //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements the operating system Host concept. // //===----------------------------------------------------------------------===// #include "llvm/Support/Host.h" #include "llvm/Support/TargetParser.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Triple.h" #include "llvm/Config/llvm-config.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/raw_ostream.h" #include #include // Include the platform-specific parts of this class. #ifdef LLVM_ON_UNIX #include "Unix/Host.inc" #endif #ifdef _WIN32 #include "Windows/Host.inc" #endif #ifdef _MSC_VER #include #endif #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) #include #include #include #include #endif #define DEBUG_TYPE "host-detection" //===----------------------------------------------------------------------===// // // Implementations of the CPU detection routines // //===----------------------------------------------------------------------===// using namespace llvm; static std::unique_ptr LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { llvm::ErrorOr> Text = llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); if (std::error_code EC = Text.getError()) { llvm::errs() << "Can't read " << "/proc/cpuinfo: " << EC.message() << "\n"; return nullptr; } return std::move(*Text); } StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) { // Access to the Processor Version Register (PVR) on PowerPC is privileged, // and so we must use an operating-system interface to determine the current // processor type. On Linux, this is exposed through the /proc/cpuinfo file. const char *generic = "generic"; // The cpu line is second (after the 'processor: 0' line), so if this // buffer is too small then something has changed (or is wrong). StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); StringRef::const_iterator CIP = CPUInfoStart; StringRef::const_iterator CPUStart = 0; size_t CPULen = 0; // We need to find the first line which starts with cpu, spaces, and a colon. // After the colon, there may be some additional spaces and then the cpu type. while (CIP < CPUInfoEnd && CPUStart == 0) { if (CIP < CPUInfoEnd && *CIP == '\n') ++CIP; if (CIP < CPUInfoEnd && *CIP == 'c') { ++CIP; if (CIP < CPUInfoEnd && *CIP == 'p') { ++CIP; if (CIP < CPUInfoEnd && *CIP == 'u') { ++CIP; while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) ++CIP; if (CIP < CPUInfoEnd && *CIP == ':') { ++CIP; while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) ++CIP; if (CIP < CPUInfoEnd) { CPUStart = CIP; while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && *CIP != ',' && *CIP != '\n')) ++CIP; CPULen = CIP - CPUStart; } } } } } if (CPUStart == 0) while (CIP < CPUInfoEnd && *CIP != '\n') ++CIP; } if (CPUStart == 0) return generic; return StringSwitch(StringRef(CPUStart, CPULen)) .Case("604e", "604e") .Case("604", "604") .Case("7400", "7400") .Case("7410", "7400") .Case("7447", "7400") .Case("7455", "7450") .Case("G4", "g4") .Case("POWER4", "970") .Case("PPC970FX", "970") .Case("PPC970MP", "970") .Case("G5", "g5") .Case("POWER5", "g5") .Case("A2", "a2") .Case("POWER6", "pwr6") .Case("POWER7", "pwr7") .Case("POWER8", "pwr8") .Case("POWER8E", "pwr8") .Case("POWER8NVL", "pwr8") .Case("POWER9", "pwr9") .Default(generic); } StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { // The cpuid register on arm is not accessible from user space. On Linux, // it is exposed through the /proc/cpuinfo file. // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line // in all cases. SmallVector Lines; ProcCpuinfoContent.split(Lines, "\n"); // Look for the CPU implementer line. StringRef Implementer; StringRef Hardware; for (unsigned I = 0, E = Lines.size(); I != E; ++I) { if (Lines[I].startswith("CPU implementer")) Implementer = Lines[I].substr(15).ltrim("\t :"); if (Lines[I].startswith("Hardware")) Hardware = Lines[I].substr(8).ltrim("\t :"); } if (Implementer == "0x41") { // ARM Ltd. // MSM8992/8994 may give cpu part for the core that the kernel is running on, // which is undeterministic and wrong. Always return cortex-a53 for these SoC. if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) return "cortex-a53"; // Look for the CPU part line. for (unsigned I = 0, E = Lines.size(); I != E; ++I) if (Lines[I].startswith("CPU part")) // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The // values correspond to the "Part number" in the CP15/c0 register. The // contents are specified in the various processor manuals. return StringSwitch(Lines[I].substr(8).ltrim("\t :")) .Case("0x926", "arm926ej-s") .Case("0xb02", "mpcore") .Case("0xb36", "arm1136j-s") .Case("0xb56", "arm1156t2-s") .Case("0xb76", "arm1176jz-s") .Case("0xc08", "cortex-a8") .Case("0xc09", "cortex-a9") .Case("0xc0f", "cortex-a15") .Case("0xc20", "cortex-m0") .Case("0xc23", "cortex-m3") .Case("0xc24", "cortex-m4") .Case("0xd04", "cortex-a35") .Case("0xd03", "cortex-a53") .Case("0xd07", "cortex-a57") .Case("0xd08", "cortex-a72") .Case("0xd09", "cortex-a73") .Case("0xd0a", "cortex-a75") .Case("0xd0b", "cortex-a76") .Default("generic"); } if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. for (unsigned I = 0, E = Lines.size(); I != E; ++I) { if (Lines[I].startswith("CPU part")) { return StringSwitch(Lines[I].substr(8).ltrim("\t :")) .Case("0x516", "thunderx2t99") .Case("0x0516", "thunderx2t99") .Case("0xaf", "thunderx2t99") .Case("0x0af", "thunderx2t99") .Case("0xa1", "thunderxt88") .Case("0x0a1", "thunderxt88") .Default("generic"); } } } if (Implementer == "0x48") // HiSilicon Technologies, Inc. // Look for the CPU part line. for (unsigned I = 0, E = Lines.size(); I != E; ++I) if (Lines[I].startswith("CPU part")) // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The // values correspond to the "Part number" in the CP15/c0 register. The // contents are specified in the various processor manuals. return StringSwitch(Lines[I].substr(8).ltrim("\t :")) .Case("0xd01", "tsv110") .Default("generic"); if (Implementer == "0x51") // Qualcomm Technologies, Inc. // Look for the CPU part line. for (unsigned I = 0, E = Lines.size(); I != E; ++I) if (Lines[I].startswith("CPU part")) // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The // values correspond to the "Part number" in the CP15/c0 register. The // contents are specified in the various processor manuals. return StringSwitch(Lines[I].substr(8).ltrim("\t :")) .Case("0x06f", "krait") // APQ8064 .Case("0x201", "kryo") .Case("0x205", "kryo") .Case("0x211", "kryo") .Case("0x800", "cortex-a73") .Case("0x801", "cortex-a73") .Case("0x802", "cortex-a73") .Case("0x803", "cortex-a73") .Case("0x804", "cortex-a73") .Case("0x805", "cortex-a73") .Case("0xc00", "falkor") .Case("0xc01", "saphira") .Default("generic"); if (Implementer == "0x53") { // Samsung Electronics Co., Ltd. // The Exynos chips have a convoluted ID scheme that doesn't seem to follow // any predictive pattern across variants and parts. unsigned Variant = 0, Part = 0; // Look for the CPU variant line, whose value is a 1 digit hexadecimal // number, corresponding to the Variant bits in the CP15/C0 register. for (auto I : Lines) if (I.consume_front("CPU variant")) I.ltrim("\t :").getAsInteger(0, Variant); // Look for the CPU part line, whose value is a 3 digit hexadecimal // number, corresponding to the PartNum bits in the CP15/C0 register. for (auto I : Lines) if (I.consume_front("CPU part")) I.ltrim("\t :").getAsInteger(0, Part); unsigned Exynos = (Variant << 12) | Part; switch (Exynos) { default: // Default by falling through to Exynos M1. LLVM_FALLTHROUGH; case 0x1001: return "exynos-m1"; case 0x4001: return "exynos-m2"; } } return "generic"; } StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { // STIDP is a privileged operation, so use /proc/cpuinfo instead. // The "processor 0:" line comes after a fair amount of other information, // including a cache breakdown, but this should be plenty. SmallVector Lines; ProcCpuinfoContent.split(Lines, "\n"); // Look for the CPU features. SmallVector CPUFeatures; for (unsigned I = 0, E = Lines.size(); I != E; ++I) if (Lines[I].startswith("features")) { size_t Pos = Lines[I].find(":"); if (Pos != StringRef::npos) { Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); break; } } // We need to check for the presence of vector support independently of // the machine type, since we may only use the vector register set when // supported by the kernel (and hypervisor). bool HaveVectorSupport = false; for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { if (CPUFeatures[I] == "vx") HaveVectorSupport = true; } // Now check the processor machine type. for (unsigned I = 0, E = Lines.size(); I != E; ++I) { if (Lines[I].startswith("processor ")) { size_t Pos = Lines[I].find("machine = "); if (Pos != StringRef::npos) { Pos += sizeof("machine = ") - 1; unsigned int Id; if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { if (Id >= 8561 && HaveVectorSupport) return "arch13"; if (Id >= 3906 && HaveVectorSupport) return "z14"; if (Id >= 2964 && HaveVectorSupport) return "z13"; if (Id >= 2827) return "zEC12"; if (Id >= 2817) return "z196"; } } break; } } return "generic"; } StringRef sys::detail::getHostCPUNameForBPF() { #if !defined(__linux__) || !defined(__x86_64__) return "generic"; #else uint8_t v3_insns[40] __attribute__ ((aligned (8))) = /* BPF_MOV64_IMM(BPF_REG_0, 0) */ { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, /* BPF_EXIT_INSN() */ 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; uint8_t v2_insns[40] __attribute__ ((aligned (8))) = /* BPF_MOV64_IMM(BPF_REG_0, 0) */ { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, /* BPF_MOV64_IMM(BPF_REG_2, 1) */ 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */ 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, /* BPF_MOV64_IMM(BPF_REG_0, 1) */ 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, /* BPF_EXIT_INSN() */ 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; struct bpf_prog_load_attr { uint32_t prog_type; uint32_t insn_cnt; uint64_t insns; uint64_t license; uint32_t log_level; uint32_t log_size; uint64_t log_buf; uint32_t kern_version; uint32_t prog_flags; } attr = {}; attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ attr.insn_cnt = 5; attr.insns = (uint64_t)v3_insns; attr.license = (uint64_t)"DUMMY"; int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); if (fd >= 0) { close(fd); return "v3"; } /* Clear the whole attr in case its content changed by syscall. */ memset(&attr, 0, sizeof(attr)); attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */ attr.insn_cnt = 5; attr.insns = (uint64_t)v2_insns; attr.license = (uint64_t)"DUMMY"; fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr)); if (fd >= 0) { close(fd); return "v2"; } return "v1"; #endif } #if defined(__i386__) || defined(_M_IX86) || \ defined(__x86_64__) || defined(_M_X64) enum VendorSignatures { SIG_INTEL = 0x756e6547 /* Genu */, SIG_AMD = 0x68747541 /* Auth */ }; // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID // support. Consequently, for i386, the presence of CPUID is checked first // via the corresponding eflags bit. // Removal of cpuid.h header motivated by PR30384 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp // or test-suite, but are used in external projects e.g. libstdcxx static bool isCpuIdSupported() { #if defined(__GNUC__) || defined(__clang__) #if defined(__i386__) int __cpuid_supported; __asm__(" pushfl\n" " popl %%eax\n" " movl %%eax,%%ecx\n" " xorl $0x00200000,%%eax\n" " pushl %%eax\n" " popfl\n" " pushfl\n" " popl %%eax\n" " movl $0,%0\n" " cmpl %%eax,%%ecx\n" " je 1f\n" " movl $1,%0\n" "1:" : "=r"(__cpuid_supported) : : "eax", "ecx"); if (!__cpuid_supported) return false; #endif return true; #endif return true; } /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in /// the specified arguments. If we can't run cpuid on the host, return true. static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { #if defined(__GNUC__) || defined(__clang__) #if defined(__x86_64__) // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. // FIXME: should we save this for Clang? __asm__("movq\t%%rbx, %%rsi\n\t" "cpuid\n\t" "xchgq\t%%rbx, %%rsi\n\t" : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) : "a"(value)); return false; #elif defined(__i386__) __asm__("movl\t%%ebx, %%esi\n\t" "cpuid\n\t" "xchgl\t%%ebx, %%esi\n\t" : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) : "a"(value)); return false; #else return true; #endif #elif defined(_MSC_VER) // The MSVC intrinsic is portable across x86 and x64. int registers[4]; __cpuid(registers, value); *rEAX = registers[0]; *rEBX = registers[1]; *rECX = registers[2]; *rEDX = registers[3]; return false; #else return true; #endif } /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return /// the 4 values in the specified arguments. If we can't run cpuid on the host, /// return true. static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, unsigned *rEBX, unsigned *rECX, unsigned *rEDX) { #if defined(__GNUC__) || defined(__clang__) #if defined(__x86_64__) // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. // FIXME: should we save this for Clang? __asm__("movq\t%%rbx, %%rsi\n\t" "cpuid\n\t" "xchgq\t%%rbx, %%rsi\n\t" : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) : "a"(value), "c"(subleaf)); return false; #elif defined(__i386__) __asm__("movl\t%%ebx, %%esi\n\t" "cpuid\n\t" "xchgl\t%%ebx, %%esi\n\t" : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) : "a"(value), "c"(subleaf)); return false; #else return true; #endif #elif defined(_MSC_VER) int registers[4]; __cpuidex(registers, value, subleaf); *rEAX = registers[0]; *rEBX = registers[1]; *rECX = registers[2]; *rEDX = registers[3]; return false; #else return true; #endif } // Read control register 0 (XCR0). Used to detect features such as AVX. static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { #if defined(__GNUC__) || defined(__clang__) // Check xgetbv; this uses a .byte sequence instead of the instruction // directly because older assemblers do not include support for xgetbv and // there is no easy way to conditionally compile based on the assembler used. __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); return false; #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); *rEAX = Result; *rEDX = Result >> 32; return false; #else return true; #endif } static void detectX86FamilyModel(unsigned EAX, unsigned *Family, unsigned *Model) { *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 if (*Family == 6 || *Family == 0xf) { if (*Family == 0xf) // Examine extended family ID if family ID is F. *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 // Examine extended model ID if family ID is 6 or F. *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 } } static void getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, unsigned Brand_id, unsigned Features, unsigned Features2, unsigned Features3, unsigned *Type, unsigned *Subtype) { if (Brand_id != 0) return; switch (Family) { case 3: *Type = X86::INTEL_i386; break; case 4: *Type = X86::INTEL_i486; break; case 5: if (Features & (1 << X86::FEATURE_MMX)) { *Type = X86::INTEL_PENTIUM_MMX; break; } *Type = X86::INTEL_PENTIUM; break; case 6: switch (Model) { case 0x01: // Pentium Pro processor *Type = X86::INTEL_PENTIUM_PRO; break; case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, // model 03 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, // model 05, and Intel Celeron processor, model 05 case 0x06: // Celeron processor, model 06 *Type = X86::INTEL_PENTIUM_II; break; case 0x07: // Pentium III processor, model 07, and Pentium III Xeon // processor, model 07 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, // model 08, and Celeron processor, model 08 case 0x0a: // Pentium III Xeon processor, model 0Ah case 0x0b: // Pentium III processor, model 0Bh *Type = X86::INTEL_PENTIUM_III; break; case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model // 0Dh. All processors are manufactured using the 90 nm process. case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 // Integrated Processor with Intel QuickAssist Technology *Type = X86::INTEL_PENTIUM_M; break; case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model // 0Eh. All processors are manufactured using the 65 nm process. *Type = X86::INTEL_CORE_DUO; break; // yonah case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile // processor, Intel Core 2 Quad processor, Intel Core 2 Quad // mobile processor, Intel Core 2 Extreme processor, Intel // Pentium Dual-Core processor, Intel Xeon processor, model // 0Fh. All processors are manufactured using the 65 nm process. case 0x16: // Intel Celeron processor model 16h. All processors are // manufactured using the 65 nm process *Type = X86::INTEL_CORE2; // "core2" *Subtype = X86::INTEL_CORE2_65; break; case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model // 17h. All processors are manufactured using the 45 nm process. // // 45nm: Penryn , Wolfdale, Yorkfield (XE) case 0x1d: // Intel Xeon processor MP. All processors are manufactured using // the 45 nm process. *Type = X86::INTEL_CORE2; // "penryn" *Subtype = X86::INTEL_CORE2_45; break; case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All // processors are manufactured using the 45 nm process. case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. // As found in a Summer 2010 model iMac. case 0x1f: case 0x2e: // Nehalem EX *Type = X86::INTEL_COREI7; // "nehalem" *Subtype = X86::INTEL_COREI7_NEHALEM; break; case 0x25: // Intel Core i7, laptop version. case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All // processors are manufactured using the 32 nm process. case 0x2f: // Westmere EX *Type = X86::INTEL_COREI7; // "westmere" *Subtype = X86::INTEL_COREI7_WESTMERE; break; case 0x2a: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. case 0x2d: *Type = X86::INTEL_COREI7; //"sandybridge" *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; break; case 0x3a: case 0x3e: // Ivy Bridge EP *Type = X86::INTEL_COREI7; // "ivybridge" *Subtype = X86::INTEL_COREI7_IVYBRIDGE; break; // Haswell: case 0x3c: case 0x3f: case 0x45: case 0x46: *Type = X86::INTEL_COREI7; // "haswell" *Subtype = X86::INTEL_COREI7_HASWELL; break; // Broadwell: case 0x3d: case 0x47: case 0x4f: case 0x56: *Type = X86::INTEL_COREI7; // "broadwell" *Subtype = X86::INTEL_COREI7_BROADWELL; break; // Skylake: case 0x4e: // Skylake mobile case 0x5e: // Skylake desktop case 0x8e: // Kaby Lake mobile case 0x9e: // Kaby Lake desktop *Type = X86::INTEL_COREI7; // "skylake" *Subtype = X86::INTEL_COREI7_SKYLAKE; break; // Skylake Xeon: case 0x55: *Type = X86::INTEL_COREI7; if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake" else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake" else *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" break; // Cannonlake: case 0x66: *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake" break; // Icelake: case 0x7d: case 0x7e: *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" break; // Icelake Xeon: case 0x6a: case 0x6c: *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" break; case 0x1c: // Most 45 nm Intel Atom processors case 0x26: // 45 nm Atom Lincroft case 0x27: // 32 nm Atom Medfield case 0x35: // 32 nm Atom Midview case 0x36: // 32 nm Atom Midview *Type = X86::INTEL_BONNELL; break; // "bonnell" // Atom Silvermont codes from the Intel software optimization guide. case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d: case 0x4c: // really airmont *Type = X86::INTEL_SILVERMONT; break; // "silvermont" // Goldmont: case 0x5c: // Apollo Lake case 0x5f: // Denverton *Type = X86::INTEL_GOLDMONT; break; // "goldmont" case 0x7a: *Type = X86::INTEL_GOLDMONT_PLUS; break; case 0x86: *Type = X86::INTEL_TREMONT; break; case 0x57: *Type = X86::INTEL_KNL; // knl break; case 0x85: *Type = X86::INTEL_KNM; // knm break; default: // Unknown family 6 CPU, try to guess. + // TODO detect tigerlake host + if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) { + *Type = X86::INTEL_COREI7; + *Subtype = X86::INTEL_COREI7_TIGERLAKE; + break; + } + if (Features & (1 << X86::FEATURE_AVX512VBMI2)) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; break; } if (Features & (1 << X86::FEATURE_AVX512VBMI)) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_CANNONLAKE; break; } if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_COOPERLAKE; break; } if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_CASCADELAKE; break; } if (Features & (1 << X86::FEATURE_AVX512VL)) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; break; } if (Features & (1 << X86::FEATURE_AVX512ER)) { *Type = X86::INTEL_KNL; // knl break; } if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) { if (Features3 & (1 << (X86::FEATURE_SHA - 64))) { *Type = X86::INTEL_GOLDMONT; } else { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_SKYLAKE; } break; } if (Features3 & (1 << (X86::FEATURE_ADX - 64))) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_BROADWELL; break; } if (Features & (1 << X86::FEATURE_AVX2)) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_HASWELL; break; } if (Features & (1 << X86::FEATURE_AVX)) { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_SANDYBRIDGE; break; } if (Features & (1 << X86::FEATURE_SSE4_2)) { if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { *Type = X86::INTEL_SILVERMONT; } else { *Type = X86::INTEL_COREI7; *Subtype = X86::INTEL_COREI7_NEHALEM; } break; } if (Features & (1 << X86::FEATURE_SSE4_1)) { *Type = X86::INTEL_CORE2; // "penryn" *Subtype = X86::INTEL_CORE2_45; break; } if (Features & (1 << X86::FEATURE_SSSE3)) { if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) { *Type = X86::INTEL_BONNELL; // "bonnell" } else { *Type = X86::INTEL_CORE2; // "core2" *Subtype = X86::INTEL_CORE2_65; } break; } if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { *Type = X86::INTEL_CORE2; // "core2" *Subtype = X86::INTEL_CORE2_65; break; } if (Features & (1 << X86::FEATURE_SSE3)) { *Type = X86::INTEL_CORE_DUO; break; } if (Features & (1 << X86::FEATURE_SSE2)) { *Type = X86::INTEL_PENTIUM_M; break; } if (Features & (1 << X86::FEATURE_SSE)) { *Type = X86::INTEL_PENTIUM_III; break; } if (Features & (1 << X86::FEATURE_MMX)) { *Type = X86::INTEL_PENTIUM_II; break; } *Type = X86::INTEL_PENTIUM_PRO; break; } break; case 15: { if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) { *Type = X86::INTEL_NOCONA; break; } if (Features & (1 << X86::FEATURE_SSE3)) { *Type = X86::INTEL_PRESCOTT; break; } *Type = X86::INTEL_PENTIUM_IV; break; } default: break; /*"generic"*/ } } static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, unsigned Features, unsigned *Type, unsigned *Subtype) { // FIXME: this poorly matches the generated SubtargetFeatureKV table. There // appears to be no way to generate the wide variety of AMD-specific targets // from the information returned from CPUID. switch (Family) { case 4: *Type = X86::AMD_i486; break; case 5: *Type = X86::AMDPENTIUM; switch (Model) { case 6: case 7: *Subtype = X86::AMDPENTIUM_K6; break; // "k6" case 8: *Subtype = X86::AMDPENTIUM_K62; break; // "k6-2" case 9: case 13: *Subtype = X86::AMDPENTIUM_K63; break; // "k6-3" case 10: *Subtype = X86::AMDPENTIUM_GEODE; break; // "geode" } break; case 6: if (Features & (1 << X86::FEATURE_SSE)) { *Type = X86::AMD_ATHLON_XP; break; // "athlon-xp" } *Type = X86::AMD_ATHLON; break; // "athlon" case 15: if (Features & (1 << X86::FEATURE_SSE3)) { *Type = X86::AMD_K8SSE3; break; // "k8-sse3" } *Type = X86::AMD_K8; break; // "k8" case 16: *Type = X86::AMDFAM10H; // "amdfam10" switch (Model) { case 2: *Subtype = X86::AMDFAM10H_BARCELONA; break; case 4: *Subtype = X86::AMDFAM10H_SHANGHAI; break; case 8: *Subtype = X86::AMDFAM10H_ISTANBUL; break; } break; case 20: *Type = X86::AMD_BTVER1; break; // "btver1"; case 21: *Type = X86::AMDFAM15H; if (Model >= 0x60 && Model <= 0x7f) { *Subtype = X86::AMDFAM15H_BDVER4; break; // "bdver4"; 60h-7Fh: Excavator } if (Model >= 0x30 && Model <= 0x3f) { *Subtype = X86::AMDFAM15H_BDVER3; break; // "bdver3"; 30h-3Fh: Steamroller } if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) { *Subtype = X86::AMDFAM15H_BDVER2; break; // "bdver2"; 02h, 10h-1Fh: Piledriver } if (Model <= 0x0f) { *Subtype = X86::AMDFAM15H_BDVER1; break; // "bdver1"; 00h-0Fh: Bulldozer } break; case 22: *Type = X86::AMD_BTVER2; break; // "btver2" case 23: *Type = X86::AMDFAM17H; if (Model >= 0x30 && Model <= 0x3f) { *Subtype = X86::AMDFAM17H_ZNVER2; break; // "znver2"; 30h-3fh: Zen2 } if (Model <= 0x0f) { *Subtype = X86::AMDFAM17H_ZNVER1; break; // "znver1"; 00h-0Fh: Zen1 } break; default: break; // "generic" } } static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, unsigned *FeaturesOut, unsigned *Features2Out, unsigned *Features3Out) { unsigned Features = 0; unsigned Features2 = 0; unsigned Features3 = 0; unsigned EAX, EBX; auto setFeature = [&](unsigned F) { if (F < 32) Features |= 1U << (F & 0x1f); else if (F < 64) Features2 |= 1U << ((F - 32) & 0x1f); else if (F < 96) Features3 |= 1U << ((F - 64) & 0x1f); else llvm_unreachable("Unexpected FeatureBit"); }; if ((EDX >> 15) & 1) setFeature(X86::FEATURE_CMOV); if ((EDX >> 23) & 1) setFeature(X86::FEATURE_MMX); if ((EDX >> 25) & 1) setFeature(X86::FEATURE_SSE); if ((EDX >> 26) & 1) setFeature(X86::FEATURE_SSE2); if ((ECX >> 0) & 1) setFeature(X86::FEATURE_SSE3); if ((ECX >> 1) & 1) setFeature(X86::FEATURE_PCLMUL); if ((ECX >> 9) & 1) setFeature(X86::FEATURE_SSSE3); if ((ECX >> 12) & 1) setFeature(X86::FEATURE_FMA); if ((ECX >> 19) & 1) setFeature(X86::FEATURE_SSE4_1); if ((ECX >> 20) & 1) setFeature(X86::FEATURE_SSE4_2); if ((ECX >> 23) & 1) setFeature(X86::FEATURE_POPCNT); if ((ECX >> 25) & 1) setFeature(X86::FEATURE_AES); if ((ECX >> 22) & 1) setFeature(X86::FEATURE_MOVBE); // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // indicates that the AVX registers will be saved and restored on context // switch, then we have full AVX support. const unsigned AVXBits = (1 << 27) | (1 << 28); bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); if (HasAVX) setFeature(X86::FEATURE_AVX); bool HasLeaf7 = MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); if (HasLeaf7 && ((EBX >> 3) & 1)) setFeature(X86::FEATURE_BMI); if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) setFeature(X86::FEATURE_AVX2); if (HasLeaf7 && ((EBX >> 8) & 1)) setFeature(X86::FEATURE_BMI2); if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512F); if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512DQ); if (HasLeaf7 && ((EBX >> 19) & 1)) setFeature(X86::FEATURE_ADX); if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512IFMA); if (HasLeaf7 && ((EBX >> 23) & 1)) setFeature(X86::FEATURE_CLFLUSHOPT); if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512PF); if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512ER); if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512CD); if (HasLeaf7 && ((EBX >> 29) & 1)) setFeature(X86::FEATURE_SHA); if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512BW); if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VL); if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VBMI); if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VBMI2); if (HasLeaf7 && ((ECX >> 8) & 1)) setFeature(X86::FEATURE_GFNI); if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX) setFeature(X86::FEATURE_VPCLMULQDQ); if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VNNI); if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512BITALG); if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512VPOPCNTDQ); if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX5124VNNIW); if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX5124FMAPS); + if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) + setFeature(X86::FEATURE_AVX512VP2INTERSECT); unsigned MaxExtLevel; getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); if (HasExtLeaf1 && ((ECX >> 6) & 1)) setFeature(X86::FEATURE_SSE4_A); if (HasExtLeaf1 && ((ECX >> 11) & 1)) setFeature(X86::FEATURE_XOP); if (HasExtLeaf1 && ((ECX >> 16) & 1)) setFeature(X86::FEATURE_FMA4); if (HasExtLeaf1 && ((EDX >> 29) & 1)) setFeature(X86::FEATURE_EM64T); *FeaturesOut = Features; *Features2Out = Features2; *Features3Out = Features3; } StringRef sys::getHostCPUName() { unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; unsigned MaxLeaf, Vendor; #if defined(__GNUC__) || defined(__clang__) //FIXME: include cpuid.h from clang or copy __get_cpuid_max here // and simplify it to not invoke __cpuid (like cpu_model.c in // compiler-rt/lib/builtins/cpu_model.c? // Opting for the second option. if(!isCpuIdSupported()) return "generic"; #endif if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) return "generic"; getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); unsigned Brand_id = EBX & 0xff; unsigned Family = 0, Model = 0; unsigned Features = 0, Features2 = 0, Features3 = 0; detectX86FamilyModel(EAX, &Family, &Model); getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3); unsigned Type = 0; unsigned Subtype = 0; if (Vendor == SIG_INTEL) { getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, Features2, Features3, &Type, &Subtype); } else if (Vendor == SIG_AMD) { getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); } // Check subtypes first since those are more specific. #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ if (Subtype == X86::ENUM) \ return ARCHNAME; #include "llvm/Support/X86TargetParser.def" // Now check types. #define X86_CPU_TYPE(ARCHNAME, ENUM) \ if (Type == X86::ENUM) \ return ARCHNAME; #include "llvm/Support/X86TargetParser.def" return "generic"; } #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) StringRef sys::getHostCPUName() { host_basic_info_data_t hostInfo; mach_msg_type_number_t infoCount; infoCount = HOST_BASIC_INFO_COUNT; mach_port_t hostPort = mach_host_self(); host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo, &infoCount); mach_port_deallocate(mach_task_self(), hostPort); if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic"; switch (hostInfo.cpu_subtype) { case CPU_SUBTYPE_POWERPC_601: return "601"; case CPU_SUBTYPE_POWERPC_602: return "602"; case CPU_SUBTYPE_POWERPC_603: return "603"; case CPU_SUBTYPE_POWERPC_603e: return "603e"; case CPU_SUBTYPE_POWERPC_603ev: return "603ev"; case CPU_SUBTYPE_POWERPC_604: return "604"; case CPU_SUBTYPE_POWERPC_604e: return "604e"; case CPU_SUBTYPE_POWERPC_620: return "620"; case CPU_SUBTYPE_POWERPC_750: return "750"; case CPU_SUBTYPE_POWERPC_7400: return "7400"; case CPU_SUBTYPE_POWERPC_7450: return "7450"; case CPU_SUBTYPE_POWERPC_970: return "970"; default:; } return "generic"; } #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) StringRef sys::getHostCPUName() { std::unique_ptr P = getProcCpuinfoContent(); StringRef Content = P ? P->getBuffer() : ""; return detail::getHostCPUNameForPowerPC(Content); } #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) StringRef sys::getHostCPUName() { std::unique_ptr P = getProcCpuinfoContent(); StringRef Content = P ? P->getBuffer() : ""; return detail::getHostCPUNameForARM(Content); } #elif defined(__linux__) && defined(__s390x__) StringRef sys::getHostCPUName() { std::unique_ptr P = getProcCpuinfoContent(); StringRef Content = P ? P->getBuffer() : ""; return detail::getHostCPUNameForS390x(Content); } #else StringRef sys::getHostCPUName() { return "generic"; } #endif #if defined(__linux__) && defined(__x86_64__) // On Linux, the number of physical cores can be computed from /proc/cpuinfo, // using the number of unique physical/core id pairs. The following // implementation reads the /proc/cpuinfo format on an x86_64 system. static int computeHostNumPhysicalCores() { // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be // mmapped because it appears to have 0 size. llvm::ErrorOr> Text = llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); if (std::error_code EC = Text.getError()) { llvm::errs() << "Can't read " << "/proc/cpuinfo: " << EC.message() << "\n"; return -1; } SmallVector strs; (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, /*KeepEmpty=*/false); int CurPhysicalId = -1; int CurCoreId = -1; SmallSet, 32> UniqueItems; for (auto &Line : strs) { Line = Line.trim(); if (!Line.startswith("physical id") && !Line.startswith("core id")) continue; std::pair Data = Line.split(':'); auto Name = Data.first.trim(); auto Val = Data.second.trim(); if (Name == "physical id") { assert(CurPhysicalId == -1 && "Expected a core id before seeing another physical id"); Val.getAsInteger(10, CurPhysicalId); } if (Name == "core id") { assert(CurCoreId == -1 && "Expected a physical id before seeing another core id"); Val.getAsInteger(10, CurCoreId); } if (CurPhysicalId != -1 && CurCoreId != -1) { UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); CurPhysicalId = -1; CurCoreId = -1; } } return UniqueItems.size(); } #elif defined(__APPLE__) && defined(__x86_64__) #include #include // Gets the number of *physical cores* on the machine. static int computeHostNumPhysicalCores() { uint32_t count; size_t len = sizeof(count); sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); if (count < 1) { int nm[2]; nm[0] = CTL_HW; nm[1] = HW_AVAILCPU; sysctl(nm, 2, &count, &len, NULL, 0); if (count < 1) return -1; } return count; } #else // On other systems, return -1 to indicate unknown. static int computeHostNumPhysicalCores() { return -1; } #endif int sys::getHostNumPhysicalCores() { static int NumCores = computeHostNumPhysicalCores(); return NumCores; } #if defined(__i386__) || defined(_M_IX86) || \ defined(__x86_64__) || defined(_M_X64) bool sys::getHostCPUFeatures(StringMap &Features) { unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; unsigned MaxLevel; union { unsigned u[3]; char c[12]; } text; if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || MaxLevel < 1) return false; getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); Features["cx8"] = (EDX >> 8) & 1; Features["cmov"] = (EDX >> 15) & 1; Features["mmx"] = (EDX >> 23) & 1; Features["fxsr"] = (EDX >> 24) & 1; Features["sse"] = (EDX >> 25) & 1; Features["sse2"] = (EDX >> 26) & 1; Features["sse3"] = (ECX >> 0) & 1; Features["pclmul"] = (ECX >> 1) & 1; Features["ssse3"] = (ECX >> 9) & 1; Features["cx16"] = (ECX >> 13) & 1; Features["sse4.1"] = (ECX >> 19) & 1; Features["sse4.2"] = (ECX >> 20) & 1; Features["movbe"] = (ECX >> 22) & 1; Features["popcnt"] = (ECX >> 23) & 1; Features["aes"] = (ECX >> 25) & 1; Features["rdrnd"] = (ECX >> 30) & 1; // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // indicates that the AVX registers will be saved and restored on context // switch, then we have full AVX support. bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); // AVX512 requires additional context to be saved by the OS. bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); Features["avx"] = HasAVXSave; Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; // Only enable XSAVE if OS has enabled support for saving YMM state. Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave; Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave; unsigned MaxExtLevel; getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1); Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1); // Miscellaneous memory related features, detected by // using the 0x80000008 leaf of the CPUID instruction bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX); Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1); bool HasLeaf7 = MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); // AVX2 is only supported if we have the OS save support from AVX. Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave; Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1); // AVX512 is only supported if the OS supports the context save for it. Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1); Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1); Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save; Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1); Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1); Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave; Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave; Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save; Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save; Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1); Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1); Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1); Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1); Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1); // There are two CPUID leafs which information associated with the pconfig // instruction: // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th // bit of EDX), while the EAX=0x1b leaf returns information on the // availability of specific pconfig leafs. // The target feature here only refers to the the first of these two. // Users might need to check for the availability of specific pconfig // leaves using cpuid, since that information is ignored while // detecting features using the "-march=native" flag. // For more info, see X86 ISA docs. Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); bool HasLeaf7Subleaf1 = MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; bool HasLeafD = MaxLevel >= 0xd && !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); // Only enable XSAVE if OS has enabled support for saving YMM state. Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave; Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave; Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave; bool HasLeaf14 = MaxLevel >= 0x14 && !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX); Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1); return true; } #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) bool sys::getHostCPUFeatures(StringMap &Features) { std::unique_ptr P = getProcCpuinfoContent(); if (!P) return false; SmallVector Lines; P->getBuffer().split(Lines, "\n"); SmallVector CPUFeatures; // Look for the CPU features. for (unsigned I = 0, E = Lines.size(); I != E; ++I) if (Lines[I].startswith("Features")) { Lines[I].split(CPUFeatures, ' '); break; } #if defined(__aarch64__) // Keep track of which crypto features we have seen enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; uint32_t crypto = 0; #endif for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { StringRef LLVMFeatureStr = StringSwitch(CPUFeatures[I]) #if defined(__aarch64__) .Case("asimd", "neon") .Case("fp", "fp-armv8") .Case("crc32", "crc") #else .Case("half", "fp16") .Case("neon", "neon") .Case("vfpv3", "vfp3") .Case("vfpv3d16", "d16") .Case("vfpv4", "vfp4") .Case("idiva", "hwdiv-arm") .Case("idivt", "hwdiv") #endif .Default(""); #if defined(__aarch64__) // We need to check crypto separately since we need all of the crypto // extensions to enable the subtarget feature if (CPUFeatures[I] == "aes") crypto |= CAP_AES; else if (CPUFeatures[I] == "pmull") crypto |= CAP_PMULL; else if (CPUFeatures[I] == "sha1") crypto |= CAP_SHA1; else if (CPUFeatures[I] == "sha2") crypto |= CAP_SHA2; #endif if (LLVMFeatureStr != "") Features[LLVMFeatureStr] = true; } #if defined(__aarch64__) // If we have all crypto bits we can add the feature if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) Features["crypto"] = true; #endif return true; } #else bool sys::getHostCPUFeatures(StringMap &Features) { return false; } #endif std::string sys::getProcessTriple() { std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); Triple PT(Triple::normalize(TargetTripleString)); if (sizeof(void *) == 8 && PT.isArch32Bit()) PT = PT.get64BitArchVariant(); if (sizeof(void *) == 4 && PT.isArch64Bit()) PT = PT.get32BitArchVariant(); return PT.str(); } diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index d5f4a72cafcd..b720dac307a4 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1,1267 +1,1280 @@ //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This is a target description file for the Intel i386 architecture, referred // to here as the "X86" architecture. // //===----------------------------------------------------------------------===// // Get the target-independent interfaces which we are implementing... // include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // X86 Subtarget state // def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", "64-bit mode (x86_64)">; def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", "32-bit mode (80386)">; def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", "16-bit mode (i8086)">; //===----------------------------------------------------------------------===// // X86 Subtarget features //===----------------------------------------------------------------------===// def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", "Enable X87 float instructions">; def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", "Enable NOPL instruction">; def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", "Enable conditional move instructions">; def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true", "Support CMPXCHG8B instructions">; def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", "Support POPCNT instruction">; def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", "Support fxsave/fxrestore instructions">; def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", "Support xsave instructions">; def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", "Support xsaveopt instructions">; def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", "Support xsavec instructions">; def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", "Support xsaves instructions">; def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", "Enable SSE instructions">; def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", "Enable SSE2 instructions", [FeatureSSE1]>; def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", "Enable SSE3 instructions", [FeatureSSE2]>; def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", "Enable SSSE3 instructions", [FeatureSSE3]>; def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", "Enable SSE 4.1 instructions", [FeatureSSSE3]>; def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", "Enable SSE 4.2 instructions", [FeatureSSE41]>; // The MMX subtarget feature is separate from the rest of the SSE features // because it's important (for odd compatibility reasons) to be able to // turn it off explicitly while allowing SSE+ to be on. def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", "Enable MMX instructions">; def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", "Enable 3DNow! instructions", [FeatureMMX]>; def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", "Enable 3DNow! Athlon instructions", [Feature3DNow]>; // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) // without disabling 64-bit mode. Nothing should imply this feature bit. It // is used to enforce that only 64-bit capable CPUs are used in 64-bit mode. def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", "Support 64-bit instructions">; def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", "64-bit with cmpxchg16b", [FeatureCMPXCHG8B]>; def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", "SHLD instruction is slow">; def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", "PMULLD instruction is slow">; def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", "true", "PMADDWD is slower than PMULLD">; // FIXME: This should not apply to CPUs that do not have SSE. def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", "IsUAMem16Slow", "true", "Slow unaligned 16-byte memory access">; def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", "IsUAMem32Slow", "true", "Slow unaligned 32-byte memory access">; def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", "Support SSE 4a instructions", [FeatureSSE3]>; def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", "Enable AVX instructions", [FeatureSSE42]>; def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", "Enable AVX2 instructions", [FeatureAVX]>; def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", "Enable three-operand fused multiple-add", [FeatureAVX]>; def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", "Support 16-bit floating point conversion instructions", [FeatureAVX]>; def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", "Enable AVX-512 instructions", [FeatureAVX2, FeatureFMA, FeatureF16C]>; def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", "Enable AVX-512 Exponential and Reciprocal Instructions", [FeatureAVX512]>; def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", "Enable AVX-512 Conflict Detection Instructions", [FeatureAVX512]>; def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", "true", "Enable AVX-512 Population Count Instructions", [FeatureAVX512]>; def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", "Enable AVX-512 PreFetch Instructions", [FeatureAVX512]>; def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", "true", "Prefetch with Intent to Write and T1 Hint">; def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", "Enable AVX-512 Doubleword and Quadword Instructions", [FeatureAVX512]>; def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", "Enable AVX-512 Byte and Word Instructions", [FeatureAVX512]>; def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", "Enable AVX-512 Vector Length eXtensions", [FeatureAVX512]>; def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", "Enable AVX-512 Vector Byte Manipulation Instructions", [FeatureBWI]>; def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", "Enable AVX-512 further Vector Byte Manipulation Instructions", [FeatureBWI]>; def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", "Enable AVX-512 Integer Fused Multiple-Add", [FeatureAVX512]>; def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", "Enable protection keys">; def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", "Enable AVX-512 Vector Neural Network Instructions", [FeatureAVX512]>; def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true", "Support bfloat16 floating point", [FeatureBWI]>; def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", "Enable AVX-512 Bit Algorithms", [FeatureBWI]>; def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect", "HasVP2INTERSECT", "true", "Enable AVX-512 vp2intersect", [FeatureAVX512]>; def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", "Enable packed carry-less multiplication instructions", [FeatureSSE2]>; def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", "Enable Galois Field Arithmetic Instructions", [FeatureSSE2]>; def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", "Enable vpclmulqdq instructions", [FeatureAVX, FeaturePCLMUL]>; def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", "Enable four-operand fused multiple-add", [FeatureAVX, FeatureSSE4A]>; def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", "Enable XOP instructions", [FeatureFMA4]>; def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", "HasSSEUnalignedMem", "true", "Allow unaligned memory operands with SSE instructions">; def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES instructions", [FeatureSSE2]>; def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", "Promote selected AES instructions to AVX512/AVX registers", [FeatureAVX, FeatureAES]>; def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", "Enable TBM instructions">; def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", "Enable LWP instructions">; def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", "Support MOVBE instruction">; def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", "Support RDRAND instruction">; def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", "Support FS/GS Base instructions">; def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", "Support LZCNT instruction">; def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", "Support BMI instructions">; def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", "Support BMI2 instructions">; def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", "Support RTM instructions">; def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", "Support ADX instructions">; def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", "Enable SHA instructions", [FeatureSSE2]>; def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", "Support CET Shadow-Stack instructions">; def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", "Support PRFCHW instructions">; def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", "Support RDSEED instruction">; def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", "Support LAHF and SAHF instructions">; def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", "Enable MONITORX/MWAITX timer functionality">; def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", "Enable Cache Line Zero">; def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", "Enable Cache Demote">; def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", "Support ptwrite instruction">; def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", "Support MPX instructions">; def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", "Use LEA for adjusting the stack pointer">; def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", "HasSlowDivide32", "true", "Use 8-bit divide for positive values less than 256">; def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", "HasSlowDivide64", "true", "Use 32-bit divide for positive values less than 2^32">; def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", "PadShortFunctions", "true", "Pad short functions">; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", "Invalidate Process-Context Identifier">; def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", "Enable Software Guard Extensions">; def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", "Flush A Cache Line Optimized">; def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", "Cache Line Write Back">; def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", "Write Back No Invalidate">; def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", "Support RDPID instructions">; def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", "Wait and pause enhancements">; def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", "Has ENQCMD instructions">; // On some processors, instructions that implicitly take two memory operands are // slow. In practice, this means that CALL, PUSH, and POP with memory operands // should be avoided in favor of a MOV + register CALL/PUSH/POP. def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", "SlowTwoMemOps", "true", "Two memory operand instructions are slow">; def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", "LEA instruction needs inputs at AG stage">; def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", "LEA instruction with certain arguments is slow">; def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", "LEA instruction with 3 ops or certain registers is slow">; def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", "INC and DEC instructions are slower than ADD and SUB">; def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", "Use software floating point features">; def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", "HasPOPCNTFalseDeps", "true", "POPCNT has a false dependency on dest register">; def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", "HasLZCNTFalseDeps", "true", "LZCNT/TZCNT have a false dependency on dest register">; def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", "platform configuration instruction">; // On recent X86 (port bound) processors, its preferable to combine to a single shuffle // using a variable mask over multiple fixed shuffles. def FeatureFastVariableShuffle : SubtargetFeature<"fast-variable-shuffle", "HasFastVariableShuffle", "true", "Shuffles with variable masks are fast">; // On some X86 processors, there is no performance hazard to writing only the // lower parts of a YMM or ZMM register without clearing the upper part. def FeatureFastPartialYMMorZMMWrite : SubtargetFeature<"fast-partial-ymm-or-zmm-write", "HasFastPartialYMMorZMMWrite", "true", "Partial writes to YMM/ZMM registers are fast">; // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if // vector FSQRT has higher throughput than the corresponding NR code. // The idea is that throughput bound code is likely to be vectorized, so for // vectorized code we should care about the throughput of SQRT operations. // But if the code is scalar that probably means that the code has some kind of // dependency and we should care more about reducing the latency. def FeatureFastScalarFSQRT : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", "true", "Scalar SQRT is fast (disable Newton-Raphson)">; def FeatureFastVectorFSQRT : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", "true", "Vector SQRT is fast (disable Newton-Raphson)">; // If lzcnt has equivalent latency/throughput to most simple integer ops, it can // be used to replace test/set sequences. def FeatureFastLZCNT : SubtargetFeature< "fast-lzcnt", "HasFastLZCNT", "true", "LZCNT instructions are as fast as most simple integer ops">; // If the target can efficiently decode NOPs upto 11-bytes in length. def FeatureFast11ByteNOP : SubtargetFeature< "fast-11bytenop", "HasFast11ByteNOP", "true", "Target can quickly decode up to 11 byte NOPs">; // If the target can efficiently decode NOPs upto 15-bytes in length. def FeatureFast15ByteNOP : SubtargetFeature< "fast-15bytenop", "HasFast15ByteNOP", "true", "Target can quickly decode up to 15 byte NOPs">; // Sandy Bridge and newer processors can use SHLD with the same source on both // inputs to implement rotate to avoid the partial flag update of the normal // rotate instructions. def FeatureFastSHLDRotate : SubtargetFeature< "fast-shld-rotate", "HasFastSHLDRotate", "true", "SHLD can be used as a faster rotate">; // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka // "string operations"). See "REP String Enhancement" in the Intel Software // Development Manual. This feature essentially means that REP MOVSB will copy // using the largest available size instead of copying bytes one by one, making // it at least as fast as REPMOVS{W,D,Q}. def FeatureERMSB : SubtargetFeature< "ermsb", "HasERMSB", "true", "REP MOVS/STOS are fast">; // Bulldozer and newer processors can merge CMP/TEST (but not other // instructions) with conditional branches. def FeatureBranchFusion : SubtargetFeature<"branchfusion", "HasBranchFusion", "true", "CMP/TEST can be fused with conditional branches">; // Sandy Bridge and newer processors have many instructions that can be // fused with conditional branches and pass through the CPU as a single // operation. def FeatureMacroFusion : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", "Various instructions can be fused with conditional branches">; // Gather is available since Haswell (AVX2 set). So technically, we can // generate Gathers on all AVX2 processors. But the overhead on HSW is high. // Skylake Client processor has faster Gathers than HSW and performance is // similar to Skylake Server (AVX-512). def FeatureHasFastGather : SubtargetFeature<"fast-gather", "HasFastGather", "true", "Indicates if gather is reasonably fast">; def FeaturePrefer256Bit : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", "Prefer 256-bit AVX instructions">; // Lower indirect calls using a special construct called a `retpoline` to // mitigate potential Spectre v2 attacks against them. def FeatureRetpolineIndirectCalls : SubtargetFeature< "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true", "Remove speculation of indirect calls from the generated code">; // Lower indirect branches and switches either using conditional branch trees // or using a special construct called a `retpoline` to mitigate potential // Spectre v2 attacks against them. def FeatureRetpolineIndirectBranches : SubtargetFeature< "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true", "Remove speculation of indirect branches from the generated code">; // Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and // `retpoline-indirect-branches` above. def FeatureRetpoline : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true", "Remove speculation of indirect branches from the " "generated code, either by avoiding them entirely or " "lowering them with a speculation blocking construct", [FeatureRetpolineIndirectCalls, FeatureRetpolineIndirectBranches]>; // Rely on external thunks for the emitted retpoline calls. This allows users // to provide their own custom thunk definitions in highly specialized // environments such as a kernel that does boot-time hot patching. def FeatureRetpolineExternalThunk : SubtargetFeature< "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", "When lowering an indirect call or branch using a `retpoline`, rely " "on the specified user provided thunk rather than emitting one " "ourselves. Only has effect when combined with some other retpoline " "feature", [FeatureRetpolineIndirectCalls]>; // Direct Move instructions. def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", "Support movdiri instruction">; def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", "Support movdir64b instruction">; def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true", "Indicates that the BEXTR instruction is implemented as a single uop " "with good throughput">; // Combine vector math operations with shuffles into horizontal math // instructions if a CPU implements horizontal operations (introduced with // SSE3) with better latency/throughput than the alternative sequence. def FeatureFastHorizontalOps : SubtargetFeature< "fast-hops", "HasFastHorizontalOps", "true", "Prefer horizontal vector math instructions (haddp, phsub, etc.) over " "normal vector instructions with shuffles", [FeatureSSE3]>; def FeatureFastScalarShiftMasks : SubtargetFeature< "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true", "Prefer a left/right scalar logical shift pair over a shift+and pair">; def FeatureFastVectorShiftMasks : SubtargetFeature< "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true", "Prefer a left/right vector logical shift pair over a shift+and pair">; // Merge branches using three-way conditional code. def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch", "ThreewayBranchProfitable", "true", "Merge branches to a three-way " "conditional branch">; // Bonnell def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; // Silvermont def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">; // Goldmont def ProcIntelGLM : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">; // Goldmont Plus def ProcIntelGLP : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">; // Tremont def ProcIntelTRM : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">; //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// include "X86RegisterInfo.td" include "X86RegisterBanks.td" //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// include "X86Schedule.td" include "X86InstrInfo.td" include "X86SchedPredicates.td" def X86InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // X86 Scheduler Models //===----------------------------------------------------------------------===// include "X86ScheduleAtom.td" include "X86SchedSandyBridge.td" include "X86SchedHaswell.td" include "X86SchedBroadwell.td" include "X86ScheduleSLM.td" include "X86ScheduleZnver1.td" include "X86ScheduleBdVer2.td" include "X86ScheduleBtVer2.td" include "X86SchedSkylakeClient.td" include "X86SchedSkylakeServer.td" //===----------------------------------------------------------------------===// // X86 Processor Feature Lists //===----------------------------------------------------------------------===// def ProcessorFeatures { // Nehalem list NHMInheritableFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE42, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeaturePOPCNT, FeatureLAHFSAHF, FeatureMacroFusion]; list NHMSpecificFeatures = []; list NHMFeatures = !listconcat(NHMInheritableFeatures, NHMSpecificFeatures); // Westmere list WSMAdditionalFeatures = [FeaturePCLMUL]; list WSMSpecificFeatures = []; list WSMInheritableFeatures = !listconcat(NHMInheritableFeatures, WSMAdditionalFeatures); list WSMFeatures = !listconcat(WSMInheritableFeatures, WSMSpecificFeatures); // Sandybridge list SNBAdditionalFeatures = [FeatureAVX, FeatureSlowDivide64, FeatureXSAVE, FeatureXSAVEOPT, FeatureSlow3OpsLEA, FeatureFastScalarFSQRT, FeatureFastSHLDRotate, FeatureMergeToThreeWayBranch]; list SNBSpecificFeatures = [FeatureSlowUAMem32, FeaturePOPCNTFalseDeps]; list SNBInheritableFeatures = !listconcat(WSMInheritableFeatures, SNBAdditionalFeatures); list SNBFeatures = !listconcat(SNBInheritableFeatures, SNBSpecificFeatures); // Ivybridge list IVBAdditionalFeatures = [FeatureRDRAND, FeatureF16C, FeatureFSGSBase]; list IVBSpecificFeatures = [FeatureSlowUAMem32, FeaturePOPCNTFalseDeps]; list IVBInheritableFeatures = !listconcat(SNBInheritableFeatures, IVBAdditionalFeatures); list IVBFeatures = !listconcat(IVBInheritableFeatures, IVBSpecificFeatures); // Haswell list HSWAdditionalFeatures = [FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureERMSB, FeatureFMA, FeatureINVPCID, FeatureLZCNT, FeatureMOVBE, FeatureFastVariableShuffle]; list HSWSpecificFeatures = [FeaturePOPCNTFalseDeps, FeatureLZCNTFalseDeps]; list HSWInheritableFeatures = !listconcat(IVBInheritableFeatures, HSWAdditionalFeatures); list HSWFeatures = !listconcat(HSWInheritableFeatures, HSWSpecificFeatures); // Broadwell list BDWAdditionalFeatures = [FeatureADX, FeatureRDSEED, FeaturePRFCHW]; list BDWSpecificFeatures = [FeaturePOPCNTFalseDeps, FeatureLZCNTFalseDeps]; list BDWInheritableFeatures = !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures); list BDWFeatures = !listconcat(BDWInheritableFeatures, BDWSpecificFeatures); // Skylake list SKLAdditionalFeatures = [FeatureAES, FeatureMPX, FeatureXSAVEC, FeatureXSAVES, FeatureCLFLUSHOPT, FeatureFastVectorFSQRT]; list SKLSpecificFeatures = [FeatureHasFastGather, FeaturePOPCNTFalseDeps, FeatureSGX]; list SKLInheritableFeatures = !listconcat(BDWInheritableFeatures, SKLAdditionalFeatures); list SKLFeatures = !listconcat(SKLInheritableFeatures, SKLSpecificFeatures); // Skylake-AVX512 list SKXAdditionalFeatures = [FeatureAVX512, FeatureCDI, FeatureDQI, FeatureBWI, FeatureVLX, FeaturePKU, FeatureCLWB]; list SKXSpecificFeatures = [FeatureHasFastGather, FeaturePOPCNTFalseDeps]; list SKXInheritableFeatures = !listconcat(SKLInheritableFeatures, SKXAdditionalFeatures); list SKXFeatures = !listconcat(SKXInheritableFeatures, SKXSpecificFeatures); // Cascadelake list CLXAdditionalFeatures = [FeatureVNNI]; list CLXSpecificFeatures = [FeatureHasFastGather, FeaturePOPCNTFalseDeps]; list CLXInheritableFeatures = !listconcat(SKXInheritableFeatures, CLXAdditionalFeatures); list CLXFeatures = !listconcat(CLXInheritableFeatures, CLXSpecificFeatures); // Cooperlake list CPXAdditionalFeatures = [FeatureBF16]; list CPXSpecificFeatures = [FeatureHasFastGather, FeaturePOPCNTFalseDeps]; list CPXInheritableFeatures = !listconcat(CLXInheritableFeatures, CPXAdditionalFeatures); list CPXFeatures = !listconcat(CPXInheritableFeatures, CPXSpecificFeatures); // Cannonlake list CNLAdditionalFeatures = [FeatureAVX512, FeatureCDI, FeatureDQI, FeatureBWI, FeatureVLX, FeaturePKU, FeatureVBMI, FeatureIFMA, FeatureSHA, FeatureSGX]; list CNLSpecificFeatures = [FeatureHasFastGather]; list CNLInheritableFeatures = !listconcat(SKLInheritableFeatures, CNLAdditionalFeatures); list CNLFeatures = !listconcat(CNLInheritableFeatures, CNLSpecificFeatures); // Icelake list ICLAdditionalFeatures = [FeatureBITALG, FeatureVAES, FeatureVBMI2, FeatureVNNI, FeatureVPCLMULQDQ, FeatureVPOPCNTDQ, FeatureGFNI, FeatureCLWB, FeatureRDPID]; list ICLSpecificFeatures = [FeatureHasFastGather]; list ICLInheritableFeatures = !listconcat(CNLInheritableFeatures, ICLAdditionalFeatures); list ICLFeatures = !listconcat(ICLInheritableFeatures, ICLSpecificFeatures); // Icelake Server list ICXSpecificFeatures = [FeaturePCONFIG, FeatureWBNOINVD, FeatureHasFastGather]; list ICXFeatures = !listconcat(ICLInheritableFeatures, ICXSpecificFeatures); + //Tigerlake + list TGLAdditionalFeatures = [FeatureVP2INTERSECT, + FeatureMOVDIRI, + FeatureMOVDIR64B, + FeatureSHSTK]; + list TGLSpecificFeatures = [FeatureHasFastGather]; + list TGLInheritableFeatures = + !listconcat(TGLAdditionalFeatures ,TGLSpecificFeatures); + list TGLFeatures = + !listconcat(ICLFeatures, TGLInheritableFeatures ); + // Atom list AtomInheritableFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeatureMOVBE, FeatureSlowTwoMemOps, FeatureLAHFSAHF]; list AtomSpecificFeatures = [ProcIntelAtom, FeatureSlowUAMem16, FeatureLEAForSP, FeatureSlowDivide32, FeatureSlowDivide64, FeatureLEAUsesAG, FeaturePadShortFunctions]; list AtomFeatures = !listconcat(AtomInheritableFeatures, AtomSpecificFeatures); // Silvermont list SLMAdditionalFeatures = [FeatureSSE42, FeaturePOPCNT, FeaturePCLMUL, FeaturePRFCHW, FeatureSlowLEA, FeatureSlowIncDec, FeatureRDRAND]; list SLMSpecificFeatures = [ProcIntelSLM, FeatureSlowDivide64, FeatureSlowPMULLD, FeaturePOPCNTFalseDeps]; list SLMInheritableFeatures = !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures); list SLMFeatures = !listconcat(SLMInheritableFeatures, SLMSpecificFeatures); // Goldmont list GLMAdditionalFeatures = [FeatureAES, FeatureMPX, FeatureSHA, FeatureRDSEED, FeatureXSAVE, FeatureXSAVEOPT, FeatureXSAVEC, FeatureXSAVES, FeatureCLFLUSHOPT, FeatureFSGSBase]; list GLMSpecificFeatures = [ProcIntelGLM, FeaturePOPCNTFalseDeps]; list GLMInheritableFeatures = !listconcat(SLMInheritableFeatures, GLMAdditionalFeatures); list GLMFeatures = !listconcat(GLMInheritableFeatures, GLMSpecificFeatures); // Goldmont Plus list GLPAdditionalFeatures = [FeaturePTWRITE, FeatureRDPID, FeatureSGX]; list GLPSpecificFeatures = [ProcIntelGLP]; list GLPInheritableFeatures = !listconcat(GLMInheritableFeatures, GLPAdditionalFeatures); list GLPFeatures = !listconcat(GLPInheritableFeatures, GLPSpecificFeatures); // Tremont list TRMAdditionalFeatures = [FeatureCLDEMOTE, FeatureGFNI, FeatureMOVDIRI, FeatureMOVDIR64B, FeatureWAITPKG]; list TRMSpecificFeatures = [ProcIntelTRM]; list TRMFeatures = !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures, TRMSpecificFeatures); // Knights Landing list KNLFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeaturePOPCNT, FeatureSlowDivide64, FeaturePCLMUL, FeatureXSAVE, FeatureXSAVEOPT, FeatureLAHFSAHF, FeatureSlow3OpsLEA, FeatureSlowIncDec, FeatureAES, FeatureRDRAND, FeatureF16C, FeatureFSGSBase, FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI, FeaturePREFETCHWT1, FeatureADX, FeatureRDSEED, FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureBMI2, FeatureFMA, FeaturePRFCHW, FeatureSlowTwoMemOps, FeatureFastPartialYMMorZMMWrite, FeatureHasFastGather, FeatureSlowPMADDWD]; // TODO Add AVX5124FMAPS/AVX5124VNNIW features list KNMFeatures = !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); // Barcelona list BarcelonaInheritableFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureSSE4A, Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV, Feature64Bit, FeatureFastScalarShiftMasks]; list BarcelonaFeatures = BarcelonaInheritableFeatures; // Bobcat list BtVer1InheritableFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureSSE4A, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureFast15ByteNOP, FeatureFastScalarShiftMasks, FeatureFastVectorShiftMasks]; list BtVer1Features = BtVer1InheritableFeatures; // Jaguar list BtVer2AdditionalFeatures = [FeatureAVX, FeatureAES, FeaturePCLMUL, FeatureBMI, FeatureF16C, FeatureMOVBE, FeatureXSAVE, FeatureXSAVEOPT]; list BtVer2SpecificFeatures = [FeatureFastLZCNT, FeatureFastBEXTR, FeatureFastPartialYMMorZMMWrite, FeatureFastHorizontalOps]; list BtVer2InheritableFeatures = !listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures); list BtVer2Features = !listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures); // Bulldozer list BdVer1InheritableFeatures = [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureXOP, Feature64Bit, FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW, FeaturePCLMUL, FeatureMMX, FeatureFXSR, FeatureNOPL, FeatureLZCNT, FeaturePOPCNT, FeatureXSAVE, FeatureLWP, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureFast11ByteNOP, FeatureFastScalarShiftMasks, FeatureBranchFusion]; list BdVer1Features = BdVer1InheritableFeatures; // PileDriver list BdVer2AdditionalFeatures = [FeatureF16C, FeatureBMI, FeatureTBM, FeatureFMA, FeatureFastBEXTR]; list BdVer2InheritableFeatures = !listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures); list BdVer2Features = BdVer2InheritableFeatures; // Steamroller list BdVer3AdditionalFeatures = [FeatureXSAVEOPT, FeatureFSGSBase]; list BdVer3InheritableFeatures = !listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures); list BdVer3Features = BdVer3InheritableFeatures; // Excavator list BdVer4AdditionalFeatures = [FeatureAVX2, FeatureBMI2, FeatureMWAITX]; list BdVer4InheritableFeatures = !listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures); list BdVer4Features = BdVer4InheritableFeatures; // AMD Zen Processors common ISAs list ZNFeatures = [FeatureADX, FeatureAES, FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureCLFLUSHOPT, FeatureCLZERO, FeatureCMOV, Feature64Bit, FeatureCMPXCHG16B, FeatureF16C, FeatureFMA, FeatureFSGSBase, FeatureFXSR, FeatureNOPL, FeatureFastLZCNT, FeatureLAHFSAHF, FeatureLZCNT, FeatureFastBEXTR, FeatureFast15ByteNOP, FeatureBranchFusion, FeatureFastScalarShiftMasks, FeatureMMX, FeatureMOVBE, FeatureMWAITX, FeaturePCLMUL, FeaturePOPCNT, FeaturePRFCHW, FeatureRDRAND, FeatureRDSEED, FeatureSHA, FeatureSSE4A, FeatureSlowSHLD, FeatureX87, FeatureXSAVE, FeatureXSAVEC, FeatureXSAVEOPT, FeatureXSAVES]; list ZN2AdditionalFeatures = [FeatureCLWB, FeatureRDPID, FeatureWBNOINVD]; list ZN2Features = !listconcat(ZNFeatures, ZN2AdditionalFeatures); } //===----------------------------------------------------------------------===// // X86 processors supported. //===----------------------------------------------------------------------===// class Proc Features> : ProcessorModel; // NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled // if i386/i486 is specifically requested. def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B]>; def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B]>; def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B]>; def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX]>; def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV]>; def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, FeatureNOPL]>; def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV, FeatureFXSR, FeatureNOPL]>; foreach P = ["pentium3", "pentium3m"] in { def : Proc; } // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. // The intent is to enable it for pentium4 which is the current default // processor in a vanilla 32-bit clang compilation when no specific // architecture is specified. This generally gives a nice performance // increase on silvermont, with largely neutral behavior on other // contemporary large core processors. // pentium-m, pentium4m, prescott and nocona are included as a preventative // measure to avoid performance surprises, in case clang's default cpu // changes slightly. def : ProcessorModel<"pentium-m", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; foreach P = ["pentium4", "pentium4m"] in { def : ProcessorModel; } // Intel Quark. def : Proc<"lakemont", []>; // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; // NetBurst. def : ProcessorModel<"prescott", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; def : ProcessorModel<"nocona", GenericPostRAModel, [ FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B ]>; // Intel Core 2 Solo/Duo. def : ProcessorModel<"core2", SandyBridgeModel, [ FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeatureLAHFSAHF, FeatureMacroFusion ]>; def : ProcessorModel<"penryn", SandyBridgeModel, [ FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE41, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMPXCHG16B, FeatureLAHFSAHF, FeatureMacroFusion ]>; // Atom CPUs. foreach P = ["bonnell", "atom"] in { def : ProcessorModel; } foreach P = ["silvermont", "slm"] in { def : ProcessorModel; } def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>; def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>; def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>; // "Arrandale" along with corei3 and corei5 foreach P = ["nehalem", "corei7"] in { def : ProcessorModel; } // Westmere is the corei3/i5/i7 path from nehalem to sandybridge def : ProcessorModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures>; foreach P = ["sandybridge", "corei7-avx"] in { def : ProcessorModel; } foreach P = ["ivybridge", "core-avx-i"] in { def : ProcessorModel; } foreach P = ["haswell", "core-avx2"] in { def : ProcessorModel; } def : ProcessorModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures>; def : ProcessorModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures>; // FIXME: define KNL scheduler model def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>; def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>; foreach P = ["skylake-avx512", "skx"] in { def : ProcessorModel; } def : ProcessorModel<"cascadelake", SkylakeServerModel, ProcessorFeatures.CLXFeatures>; def : ProcessorModel<"cooperlake", SkylakeServerModel, ProcessorFeatures.CPXFeatures>; def : ProcessorModel<"cannonlake", SkylakeServerModel, ProcessorFeatures.CNLFeatures>; def : ProcessorModel<"icelake-client", SkylakeServerModel, ProcessorFeatures.ICLFeatures>; def : ProcessorModel<"icelake-server", SkylakeServerModel, ProcessorFeatures.ICXFeatures>; +def : ProcessorModel<"tigerlake", SkylakeServerModel, + ProcessorFeatures.TGLFeatures>; // AMD CPUs. def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX]>; def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, Feature3DNow]>; def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, Feature3DNow]>; foreach P = ["athlon", "athlon-tbird"] in { def : Proc; } foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { def : Proc; } foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { def : Proc; } foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { def : Proc; } foreach P = ["amdfam10", "barcelona"] in { def : Proc; } // Bobcat def : Proc<"btver1", ProcessorFeatures.BtVer1Features>; // Jaguar def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>; // Bulldozer def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>; // Piledriver def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>; // Steamroller def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>; // Excavator def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>; def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>; def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>; def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, Feature3DNowA]>; def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE1, FeatureFXSR, FeatureCMOV]>; // We also provide a generic 64-bit specific x86 processor model which tries to // be good for modern chips without enabling instruction set encodings past the // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and // modern 64-bit x86 chip, and enables features that are generally beneficial. // // We currently use the Sandy Bridge model as the default scheduling model as // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which // covers a huge swath of x86 processors. If there are specific scheduling // knobs which need to be tuned differently for AMD chips, we might consider // forming a common base for them. def : ProcessorModel<"x86-64", SandyBridgeModel, [ FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlow3OpsLEA, FeatureSlowIncDec, FeatureMacroFusion ]>; //===----------------------------------------------------------------------===// // Calling Conventions //===----------------------------------------------------------------------===// include "X86CallingConv.td" //===----------------------------------------------------------------------===// // Assembly Parser //===----------------------------------------------------------------------===// def ATTAsmParserVariant : AsmParserVariant { int Variant = 0; // Variant name. string Name = "att"; // Discard comments in assembly strings. string CommentDelimiter = "#"; // Recognize hard coded registers. string RegisterPrefix = "%"; } def IntelAsmParserVariant : AsmParserVariant { int Variant = 1; // Variant name. string Name = "intel"; // Discard comments in assembly strings. string CommentDelimiter = ";"; // Recognize hard coded registers. string RegisterPrefix = ""; } //===----------------------------------------------------------------------===// // Assembly Printers //===----------------------------------------------------------------------===// // The X86 target supports two different syntaxes for emitting machine code. // This is controlled by the -x86-asm-syntax={att|intel} def ATTAsmWriter : AsmWriter { string AsmWriterClassName = "ATTInstPrinter"; int Variant = 0; } def IntelAsmWriter : AsmWriter { string AsmWriterClassName = "IntelInstPrinter"; int Variant = 1; } def X86 : Target { // Information about the instructions... let InstructionSet = X86InstrInfo; let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; let AllowRegisterRenaming = 1; } //===----------------------------------------------------------------------===// // Pfm Counters //===----------------------------------------------------------------------===// include "X86PfmCounters.td" diff --git a/llvm/test/CodeGen/X86/cpus-intel.ll b/llvm/test/CodeGen/X86/cpus-intel.ll index 1177ebcecc3f..e0dd647409f9 100644 --- a/llvm/test/CodeGen/X86/cpus-intel.ll +++ b/llvm/test/CodeGen/X86/cpus-intel.ll @@ -1,54 +1,55 @@ ; Test that the CPU names work. ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=corei7 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=ivybridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=haswell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=broadwell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skylake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cascadelake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=slm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty define void @foo() { ret void }