diff --git a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp index 743df41a00ff..0a79b793a980 100644 --- a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp +++ b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp @@ -1,145 +1,156 @@ //===---- X86IndirectBranchTracking.cpp - Enables CET IBT mechanism -------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines a pass that enables Indirect Branch Tracking (IBT) as part // of Control-Flow Enforcement Technology (CET). // The pass adds ENDBR (End Branch) machine instructions at the beginning of // each basic block or function that is referenced by an indrect jump/call // instruction. // The ENDBR instructions have a NOP encoding and as such are ignored in // targets that do not support CET IBT mechanism. //===----------------------------------------------------------------------===// #include "X86.h" #include "X86InstrInfo.h" #include "X86Subtarget.h" +#include "X86TargetMachine.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" using namespace llvm; #define DEBUG_TYPE "x86-indirect-branch-tracking" static cl::opt IndirectBranchTracking( "x86-indirect-branch-tracking", cl::init(false), cl::Hidden, cl::desc("Enable X86 indirect branch tracking pass.")); STATISTIC(NumEndBranchAdded, "Number of ENDBR instructions added"); namespace { class X86IndirectBranchTrackingPass : public MachineFunctionPass { public: X86IndirectBranchTrackingPass() : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "X86 Indirect Branch Tracking"; } bool runOnMachineFunction(MachineFunction &MF) override; private: static char ID; /// Machine instruction info used throughout the class. const X86InstrInfo *TII = nullptr; /// Endbr opcode for the current machine function. unsigned int EndbrOpcode = 0; /// Adds a new ENDBR instruction to the beginning of the MBB. /// The function will not add it if already exists. /// It will add ENDBR32 or ENDBR64 opcode, depending on the target. /// \returns true if the ENDBR was added and false otherwise. bool addENDBR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; }; } // end anonymous namespace char X86IndirectBranchTrackingPass::ID = 0; FunctionPass *llvm::createX86IndirectBranchTrackingPass() { return new X86IndirectBranchTrackingPass(); } bool X86IndirectBranchTrackingPass::addENDBR( MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { assert(TII && "Target instruction info was not initialized"); assert((X86::ENDBR64 == EndbrOpcode || X86::ENDBR32 == EndbrOpcode) && "Unexpected Endbr opcode"); // If the MBB/I is empty or the current instruction is not ENDBR, // insert ENDBR instruction to the location of I. if (I == MBB.end() || I->getOpcode() != EndbrOpcode) { BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(EndbrOpcode)); ++NumEndBranchAdded; return true; } return false; } static bool IsCallReturnTwice(llvm::MachineOperand &MOp) { if (!MOp.isGlobal()) return false; auto *CalleeFn = dyn_cast(MOp.getGlobal()); if (!CalleeFn) return false; AttributeList Attrs = CalleeFn->getAttributes(); if (Attrs.hasAttribute(AttributeList::FunctionIndex, Attribute::ReturnsTwice)) return true; return false; } bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) { const X86Subtarget &SubTarget = MF.getSubtarget(); // Check that the cf-protection-branch is enabled. Metadata *isCFProtectionSupported = MF.getMMI().getModule()->getModuleFlag("cf-protection-branch"); - if (!isCFProtectionSupported && !IndirectBranchTracking) + // NB: We need to enable IBT in jitted code if JIT compiler is CET + // enabled. + const X86TargetMachine *TM = + static_cast(&MF.getTarget()); +#ifdef __CET__ + bool isJITwithCET = TM->isJIT(); +#else + bool isJITwithCET = false; +#endif + if (!isCFProtectionSupported && !IndirectBranchTracking && !isJITwithCET) return false; // True if the current MF was changed and false otherwise. bool Changed = false; TII = SubTarget.getInstrInfo(); EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; - // Non-internal function or function whose address was taken, can be - // accessed through indirect calls. Mark the first BB with ENDBR instruction - // unless nocf_check attribute is used. - if ((MF.getFunction().hasAddressTaken() || + // Large code model, non-internal function or function whose address + // was taken, can be accessed through indirect calls. Mark the first + // BB with ENDBR instruction unless nocf_check attribute is used. + if ((TM->getCodeModel() == CodeModel::Large || + MF.getFunction().hasAddressTaken() || !MF.getFunction().hasLocalLinkage()) && !MF.getFunction().doesNoCfCheck()) { auto MBB = MF.begin(); Changed |= addENDBR(*MBB, MBB->begin()); } for (auto &MBB : MF) { // Find all basic blocks that their address was taken (for example // in the case of indirect jump) and add ENDBR instruction. if (MBB.hasAddressTaken()) Changed |= addENDBR(MBB, MBB.begin()); // Exception handle may indirectly jump to catch pad, So we should add // ENDBR before catch pad instructions. bool EHPadIBTNeeded = MBB.isEHPad(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) { if (I->isCall() && IsCallReturnTwice(I->getOperand(0))) Changed |= addENDBR(MBB, std::next(I)); if (EHPadIBTNeeded && I->isEHLabel()) { - Changed |= addENDBR(MBB, std::next(I)); - EHPadIBTNeeded = false; + Changed |= addENDBR(MBB, std::next(I)); + EHPadIBTNeeded = false; } } } return Changed; } diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index d723ee5634d0..b2551b64eb0d 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -1,549 +1,549 @@ //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines the X86 specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// #include "X86TargetMachine.h" #include "MCTargetDesc/X86MCTargetDesc.h" #include "TargetInfo/X86TargetInfo.h" #include "X86.h" #include "X86CallLowering.h" #include "X86LegalizerInfo.h" #include "X86MacroFusion.h" #include "X86Subtarget.h" #include "X86TargetObjectFile.h" #include "X86TargetTransformInfo.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/ExecutionDomainFix.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/CFGuard.h" #include #include using namespace llvm; static cl::opt EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden); static cl::opt EnableCondBrFoldingPass("x86-condbr-folding", cl::desc("Enable the conditional branch " "folding pass"), cl::init(false), cl::Hidden); extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() { // Register the target. RegisterTargetMachine X(getTheX86_32Target()); RegisterTargetMachine Y(getTheX86_64Target()); PassRegistry &PR = *PassRegistry::getPassRegistry(); initializeGlobalISel(PR); initializeWinEHStatePassPass(PR); initializeFixupBWInstPassPass(PR); initializeEvexToVexInstPassPass(PR); initializeFixupLEAPassPass(PR); initializeFPSPass(PR); initializeX86CallFrameOptimizationPass(PR); initializeX86CmovConverterPassPass(PR); initializeX86ExpandPseudoPass(PR); initializeX86ExecutionDomainFixPass(PR); initializeX86DomainReassignmentPass(PR); initializeX86AvoidSFBPassPass(PR); initializeX86AvoidTrailingCallPassPass(PR); initializeX86SpeculativeLoadHardeningPassPass(PR); initializeX86FlagsCopyLoweringPassPass(PR); initializeX86CondBrFoldingPassPass(PR); initializeX86LoadValueInjectionRetHardeningPassPass(PR); initializeX86OptimizeLEAPassPass(PR); initializeX86PartialReductionPass(PR); } static std::unique_ptr createTLOF(const Triple &TT) { if (TT.isOSBinFormatMachO()) { if (TT.getArch() == Triple::x86_64) return std::make_unique(); return std::make_unique(); } if (TT.isOSBinFormatCOFF()) return std::make_unique(); return std::make_unique(); } static std::string computeDataLayout(const Triple &TT) { // X86 is little endian std::string Ret = "e"; Ret += DataLayout::getManglingComponent(TT); // X86 and x32 have 32 bit pointers. if ((TT.isArch64Bit() && (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) || !TT.isArch64Bit()) Ret += "-p:32:32"; // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers. Ret += "-p270:32:32-p271:32:32-p272:64:64"; // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32. if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl()) Ret += "-i64:64"; else if (TT.isOSIAMCU()) Ret += "-i64:32-f64:32"; else Ret += "-f64:32:64"; // Some ABIs align long double to 128 bits, others to 32. if (TT.isOSNaCl() || TT.isOSIAMCU()) ; // No f80 else if (TT.isArch64Bit() || TT.isOSDarwin()) Ret += "-f80:128"; else Ret += "-f80:32"; if (TT.isOSIAMCU()) Ret += "-f128:32"; // The registers can hold 8, 16, 32 or, in x86-64, 64 bits. if (TT.isArch64Bit()) Ret += "-n8:16:32:64"; else Ret += "-n8:16:32"; // The stack is aligned to 32 bits on some ABIs and 128 bits on others. if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU()) Ret += "-a:0:32-S32"; else Ret += "-S128"; return Ret; } static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, Optional RM) { bool is64Bit = TT.getArch() == Triple::x86_64; if (!RM.hasValue()) { // JIT codegen should use static relocations by default, since it's // typically executed in process and not relocatable. if (JIT) return Reloc::Static; // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we // use static relocation model by default. if (TT.isOSDarwin()) { if (is64Bit) return Reloc::PIC_; return Reloc::DynamicNoPIC; } if (TT.isOSWindows() && is64Bit) return Reloc::PIC_; return Reloc::Static; } // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC // is defined as a model for code which may be used in static or dynamic // executables but not necessarily a shared library. On X86-32 we just // compile in -static mode, in x86-64 we use PIC. if (*RM == Reloc::DynamicNoPIC) { if (is64Bit) return Reloc::PIC_; if (!TT.isOSDarwin()) return Reloc::Static; } // If we are on Darwin, disallow static relocation model in X86-64 mode, since // the Mach-O file format doesn't support it. if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit) return Reloc::PIC_; return *RM; } static CodeModel::Model getEffectiveX86CodeModel(Optional CM, bool JIT, bool Is64Bit) { if (CM) { if (*CM == CodeModel::Tiny) report_fatal_error("Target does not support the tiny CodeModel", false); return *CM; } if (JIT) return Is64Bit ? CodeModel::Large : CodeModel::Small; return CodeModel::Small; } /// Create an X86 target. /// X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, JIT, RM), getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL), - TLOF(createTLOF(getTargetTriple())) { + TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) { // On PS4, the "return address" of a 'noreturn' call must still be within // the calling function, and TrapUnreachable is an easy way to get that. if (TT.isPS4() || TT.isOSBinFormatMachO()) { this->Options.TrapUnreachable = true; this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO(); } setMachineOutliner(true); // x86 supports the debug entry values. setSupportsDebugEntryValues(true); initAsmInfo(); } X86TargetMachine::~X86TargetMachine() = default; const X86Subtarget * X86TargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); StringRef CPU = !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : (StringRef)TargetCPU; StringRef FS = !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : (StringRef)TargetFS; SmallString<512> Key; Key.reserve(CPU.size() + FS.size()); Key += CPU; Key += FS; // FIXME: This is related to the code below to reset the target options, // we need to know whether or not the soft float flag is set on the // function before we can generate a subtarget. We also need to use // it as a key for the subtarget since that can be the only difference // between two functions. bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsString() == "true"; // If the soft float attribute is set on the function turn on the soft float // subtarget feature. if (SoftFloat) Key += FS.empty() ? "+soft-float" : ",+soft-float"; // Keep track of the key width after all features are added so we can extract // the feature string out later. unsigned CPUFSWidth = Key.size(); // Extract prefer-vector-width attribute. unsigned PreferVectorWidthOverride = 0; if (F.hasFnAttribute("prefer-vector-width")) { StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString(); unsigned Width; if (!Val.getAsInteger(0, Width)) { Key += ",prefer-vector-width="; Key += Val; PreferVectorWidthOverride = Width; } } // Extract min-legal-vector-width attribute. unsigned RequiredVectorWidth = UINT32_MAX; if (F.hasFnAttribute("min-legal-vector-width")) { StringRef Val = F.getFnAttribute("min-legal-vector-width").getValueAsString(); unsigned Width; if (!Val.getAsInteger(0, Width)) { Key += ",min-legal-vector-width="; Key += Val; RequiredVectorWidth = Width; } } // Extracted here so that we make sure there is backing for the StringRef. If // we assigned earlier, its possible the SmallString reallocated leaving a // dangling StringRef. FS = Key.slice(CPU.size(), CPUFSWidth); auto &I = SubtargetMap[Key]; if (!I) { // This needs to be done before we create a new subtarget since any // creation will depend on the TM and the code generation flags on the // function that reside in TargetOptions. resetTargetOptions(F); I = std::make_unique( TargetTriple, CPU, FS, *this, MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride, RequiredVectorWidth); } return I.get(); } //===----------------------------------------------------------------------===// // Command line options for x86 //===----------------------------------------------------------------------===// static cl::opt UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true)); //===----------------------------------------------------------------------===// // X86 TTI query. //===----------------------------------------------------------------------===// TargetTransformInfo X86TargetMachine::getTargetTransformInfo(const Function &F) { return TargetTransformInfo(X86TTIImpl(this, F)); } //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// namespace { /// X86 Code Generator Pass Configuration Options. class X86PassConfig : public TargetPassConfig { public: X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) {} X86TargetMachine &getX86TargetMachine() const { return getTM(); } ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override { ScheduleDAGMILive *DAG = createGenericSchedLive(C); DAG->addMutation(createX86MacroFusionDAGMutation()); return DAG; } ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override { ScheduleDAGMI *DAG = createGenericSchedPostRA(C); DAG->addMutation(createX86MacroFusionDAGMutation()); return DAG; } void addIRPasses() override; bool addInstSelector() override; bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; bool addILPOpts() override; bool addPreISel() override; void addMachineSSAOptimization() override; void addPreRegAlloc() override; void addPostRegAlloc() override; void addPreEmitPass() override; void addPreEmitPass2() override; void addPreSched2() override; std::unique_ptr getCSEConfig() const override; }; class X86ExecutionDomainFix : public ExecutionDomainFix { public: static char ID; X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {} StringRef getPassName() const override { return "X86 Execution Dependency Fix"; } }; char X86ExecutionDomainFix::ID; } // end anonymous namespace INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis) INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { return new X86PassConfig(*this, PM); } void X86PassConfig::addIRPasses() { addPass(createAtomicExpandPass()); TargetPassConfig::addIRPasses(); if (TM->getOptLevel() != CodeGenOpt::None) { addPass(createInterleavedAccessPass()); addPass(createX86PartialReductionPass()); } // Add passes that handle indirect branch removal and insertion of a retpoline // thunk. These will be a no-op unless a function subtarget has the retpoline // feature enabled. addPass(createIndirectBrExpandPass()); // Add Control Flow Guard checks. const Triple &TT = TM->getTargetTriple(); if (TT.isOSWindows()) { if (TT.getArch() == Triple::x86_64) { addPass(createCFGuardDispatchPass()); } else { addPass(createCFGuardCheckPass()); } } } bool X86PassConfig::addInstSelector() { // Install an instruction selector. addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); // For ELF, cleanup any local-dynamic TLS accesses. if (TM->getTargetTriple().isOSBinFormatELF() && getOptLevel() != CodeGenOpt::None) addPass(createCleanupLocalDynamicTLSPass()); addPass(createX86GlobalBaseRegPass()); return false; } bool X86PassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; } bool X86PassConfig::addLegalizeMachineIR() { addPass(new Legalizer()); return false; } bool X86PassConfig::addRegBankSelect() { addPass(new RegBankSelect()); return false; } bool X86PassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); return false; } bool X86PassConfig::addILPOpts() { if (EnableCondBrFoldingPass) addPass(createX86CondBrFolding()); addPass(&EarlyIfConverterID); if (EnableMachineCombinerPass) addPass(&MachineCombinerID); addPass(createX86CmovConverterPass()); return true; } bool X86PassConfig::addPreISel() { // Only add this pass for 32-bit x86 Windows. const Triple &TT = TM->getTargetTriple(); if (TT.isOSWindows() && TT.getArch() == Triple::x86) addPass(createX86WinEHStatePass()); return true; } void X86PassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOpt::None) { addPass(&LiveRangeShrinkID); addPass(createX86FixupSetCC()); addPass(createX86OptimizeLEAs()); addPass(createX86CallFrameOptimization()); addPass(createX86AvoidStoreForwardingBlocks()); } addPass(createX86SpeculativeLoadHardeningPass()); addPass(createX86FlagsCopyLoweringPass()); addPass(createX86WinAllocaExpander()); } void X86PassConfig::addMachineSSAOptimization() { addPass(createX86DomainReassignmentPass()); TargetPassConfig::addMachineSSAOptimization(); } void X86PassConfig::addPostRegAlloc() { addPass(createX86FloatingPointStackifierPass()); } void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); } void X86PassConfig::addPreEmitPass() { if (getOptLevel() != CodeGenOpt::None) { addPass(new X86ExecutionDomainFix()); addPass(createBreakFalseDeps()); } addPass(createX86IndirectBranchTrackingPass()); if (UseVZeroUpper) addPass(createX86IssueVZeroUpperPass()); if (getOptLevel() != CodeGenOpt::None) { addPass(createX86FixupBWInsts()); addPass(createX86PadShortFunctions()); addPass(createX86FixupLEAs()); addPass(createX86EvexToVexInsts()); } addPass(createX86DiscriminateMemOpsPass()); addPass(createX86InsertPrefetchPass()); addPass(createX86InsertX87waitPass()); } void X86PassConfig::addPreEmitPass2() { const Triple &TT = TM->getTargetTriple(); const MCAsmInfo *MAI = TM->getMCAsmInfo(); addPass(createX86IndirectThunksPass()); // Insert extra int3 instructions after trailing call instructions to avoid // issues in the unwinder. if (TT.isOSWindows() && TT.getArch() == Triple::x86_64) addPass(createX86AvoidTrailingCallPass()); // Verify basic block incoming and outgoing cfa offset and register values and // correct CFA calculation rule where needed by inserting appropriate CFI // instructions. if (!TT.isOSDarwin() && (!TT.isOSWindows() || MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI)) addPass(createCFIInstrInserter()); // Identify valid longjmp targets for Windows Control Flow Guard. if (TT.isOSWindows()) addPass(createCFGuardLongjmpPass()); addPass(createX86LoadValueInjectionRetHardeningPass()); } std::unique_ptr X86PassConfig::getCSEConfig() const { return getStandardCSEConfigForOpt(TM->getOptLevel()); } diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index ec3db7b1e9e8..757ce8bc5c72 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -1,59 +1,63 @@ //===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares the X86 specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H #define LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H #include "X86Subtarget.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/StringMap.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetMachine.h" #include namespace llvm { class StringRef; class X86Subtarget; class X86RegisterBankInfo; class TargetTransformInfo; class X86TargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; + // True if this is used in JIT. + bool IsJIT; public: X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT); ~X86TargetMachine() override; const X86Subtarget *getSubtargetImpl(const Function &F) const override; // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget, // subtargets are per-function entities based on the target-specific // attributes of each function. const X86Subtarget *getSubtargetImpl() const = delete; TargetTransformInfo getTargetTransformInfo(const Function &F) override; // Set up the pass pipeline. TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } + + bool isJIT() const { return IsJIT; } }; } // end namespace llvm #endif // LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking-cm-lager.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking-cm-lager.ll new file mode 100644 index 000000000000..f515c1a34c73 --- /dev/null +++ b/llvm/test/CodeGen/X86/indirect-branch-tracking-cm-lager.ll @@ -0,0 +1,36 @@ +; RUN: llc -mtriple=x86_64-unknown-unknown -code-model=large < %s | FileCheck %s + +; In large code model indirect branches are needed when branching to addresses +; whose offset from the current instruction pointer is unknown. +;CHECK-COUNT-3: endbr + +@a = dso_local local_unnamed_addr global i32 1, align 4 + +; Function Attrs: nofree noinline norecurse nounwind uwtable writeonly +define dso_local void @ext() local_unnamed_addr #0 { +entry: + store i32 0, i32* @a, align 4 + ret void +} + +; Function Attrs: nofree norecurse nounwind uwtable +define dso_local i32 @main() local_unnamed_addr #1 { +entry: + tail call fastcc void @foo() + %0 = load i32, i32* @a, align 4 + ret i32 %0 +} + +; Function Attrs: nofree noinline norecurse nounwind uwtable writeonly +define internal fastcc void @foo() unnamed_addr #0 { +entry: + tail call void @ext() + ret void +} + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"cf-protection-return", i32 1} +!2 = !{i32 4, !"cf-protection-branch", i32 1} +!3 = !{i32 1, !"Code Model", i32 4}