The only GFX10 instructions which use exec affected by wave size are v_cmpx*. But in our assembler they use exec implicitly. So I cannot imagine any relevant tests with exec. I added 2 rather formal tests instead:

LGTM

I contemplate if adding a 'proxy' instruction like s_add_u64 would help.
Code emitter would expand it into s_add+s_addc and handle relocations.
Assembly output would look like this:

Corrected a typo

Looks fine.

Corrected typos in function attributes

Corrected SIInstrInfo::usesConstantBus

Corrected SIInstrInfo::usesConstantBus

I may be missing something, but these registers are already handled by AMDGPU::isSGPR() because they are defined in SReg_32RegClass.
The same is true for AMDGPUAsmParser::usesConstantBus.

1. Updated to account for GFX10 hw registers.
2. Separated bits juggling from high-level code.

This is checked during fixups relaxations. An error is reported if the offset does not fit in 16 bits. See lit test max-branch-distance.s

Thanks!

ping

Retitled and removed a comment

Removed GFX10-relevant changes

SWDEV-188513 is P2. Could you correct the offending predicate by your next commit?
Or I can remove all changes except the predicate correction - that will not affect GFX10.

ping

Could you explain what issues you see in this change? I'm trying to make assembler as close to SP3 as possible.

After a discussion with HW people it turned out that these operands (shared_base, shared_limit etc) differ from inline constants in that they compete with other scalars for constant bus access.

Shader programming documents state that MUBUF SOFFSET is "SGPR to supply unsigned byte offset. Must be an SGPR, M0 or inline constant."
Also note that our tests are based on SP3 tables which also allow inline constants.
Of course, using fp inline constants in this context is meaningless.

Typos has been corrected. Thanks!

Updated as suggested by Matt