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Wed, Jul 21

arcbbb committed rG8d86562e5f1f: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber (authored by arcbbb).
[RegisterCoalescer] Make resolveConflicts aware of earlyclobber
Wed, Jul 21, 9:11 PM
arcbbb closed D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Wed, Jul 21, 9:11 PM · Restricted Project

Sat, Jul 17

arcbbb committed rGbe8159bfa56f: [RISCV][RVV] Precommit a test case for D105684 (authored by arcbbb).
[RISCV][RVV] Precommit a test case for D105684
Sat, Jul 17, 9:44 AM
arcbbb closed D105685: [RISCV][RVV] Precommit a test case for D105684.
Sat, Jul 17, 9:44 AM · Restricted Project

Tue, Jul 13

arcbbb accepted D105417: [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants..

LGTM

Tue, Jul 13, 2:03 AM · Restricted Project

Sun, Jul 11

arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

Avoid postfix increment operator.

Sun, Jul 11, 11:40 PM · Restricted Project

Sat, Jul 10

post.kadirselcuk awarded rGf1cbea3e5275: [RISCV] Remove Zvamo implication for v1.0-rc change a Like token.
Sat, Jul 10, 9:25 PM
post.kadirselcuk awarded D105396: [RISCV] Remove Zvamo implication for v1.0-rc change a 100 token.
Sat, Jul 10, 9:24 PM · Restricted Project, Restricted Project

Fri, Jul 9

arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

clang-formatted

Fri, Jul 9, 2:46 AM · Restricted Project
arcbbb updated the summary of D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Fri, Jul 9, 2:33 AM · Restricted Project
arcbbb updated the diff for D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.

update a test case to show the difference

Fri, Jul 9, 2:20 AM · Restricted Project
arcbbb requested review of D105685: [RISCV][RVV] Precommit a test case for D105684.
Fri, Jul 9, 2:12 AM · Restricted Project
arcbbb requested review of D105684: [RegisterCoalescer] Make resolveConflicts aware of earlyclobber.
Fri, Jul 9, 2:07 AM · Restricted Project

Tue, Jul 6

arcbbb accepted D105206: [RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno.

LGTM

Tue, Jul 6, 10:07 AM · Restricted Project
arcbbb accepted D104802: [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors..

LGTM

Tue, Jul 6, 9:46 AM · Restricted Project
arcbbb committed rGf1cbea3e5275: [RISCV] Remove Zvamo implication for v1.0-rc change (authored by arcbbb).
[RISCV] Remove Zvamo implication for v1.0-rc change
Tue, Jul 6, 9:15 AM
arcbbb closed D105396: [RISCV] Remove Zvamo implication for v1.0-rc change.
Tue, Jul 6, 9:15 AM · Restricted Project, Restricted Project

Sat, Jul 3

arcbbb updated the diff for D105396: [RISCV] Remove Zvamo implication for v1.0-rc change.

Fix FileCheck prefix: ZVAMO

Sat, Jul 3, 11:40 PM · Restricted Project, Restricted Project
arcbbb updated the diff for D105396: [RISCV] Remove Zvamo implication for v1.0-rc change.

keep Zvamo0p10 and remove the implication only.

Sat, Jul 3, 11:48 AM · Restricted Project, Restricted Project
arcbbb requested review of D105396: [RISCV] Remove Zvamo implication for v1.0-rc change.
Sat, Jul 3, 7:18 AM · Restricted Project, Restricted Project

Jun 8 2021

arcbbb accepted D103736: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions..

LGTM

Jun 8 2021, 1:49 AM · Restricted Project
arcbbb accepted D103552: Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv..

LGTM!

Jun 8 2021, 1:29 AM · Restricted Project

Jun 7 2021

arcbbb added inline comments to D103552: Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv..
Jun 7 2021, 8:28 PM · Restricted Project
arcbbb accepted D103331: [RISCV] Masked compares should use a tail agnostic policy..

LGTM

Jun 7 2021, 8:03 PM · Restricted Project

Jun 4 2021

arcbbb committed rGfcf8827a98be: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C (authored by arcbbb).
[Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C
Jun 4 2021, 12:34 AM
arcbbb closed D103603: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C.
Jun 4 2021, 12:33 AM · Restricted Project

Jun 3 2021

arcbbb updated the diff for D103603: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C.

Add a case in AArch64 test and address review comments.

Jun 3 2021, 10:26 AM · Restricted Project
arcbbb requested review of D103603: [Sema][RISCV][SVE] Allow ?: to select Typedef BuiltinType in C.
Jun 3 2021, 3:01 AM · Restricted Project

Jun 1 2021

arcbbb accepted D103211: [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv..

LGTM

Jun 1 2021, 6:15 PM · Restricted Project

May 26 2021

arcbbb added a comment to D102739: [RISCV] Enable cross basic block aware vsetvli insertion.

LGTM

May 26 2021, 6:17 AM · Restricted Project

May 21 2021

arcbbb abandoned D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.

D102739 is the preferred approach.

May 21 2021, 9:22 AM · Restricted Project
arcbbb added a comment to D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks..

LGTM

May 21 2021, 9:18 AM · Restricted Project

May 20 2021

arcbbb added inline comments to D102737: [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks..
May 20 2021, 12:35 AM · Restricted Project

May 6 2021

arcbbb abandoned D98236: [RISCV] Add SiFive-VIU75 for llvm.

Thank you for all the suggestions.

May 6 2021, 11:38 PM · Restricted Project
arcbbb added a comment to D101938: [RISCV] Initial version of a demand based vsetvli insertion pass..

I think https://reviews.llvm.org/D100932 is still useful here.
How do you think if I move it into RISCVInsertVSETVLI.cpp instead?

May 6 2021, 11:17 PM · Restricted Project

May 5 2021

arcbbb planned changes to D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.

Thank you for reading this.
Because there is an alternative approach proposed by Craig https://reviews.llvm.org/D101938,
I'll check that first and then abandon this when we are in favor of that way.

May 5 2021, 7:42 PM · Restricted Project

May 3 2021

arcbbb updated the diff for D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.

rebased to pass unit tests.

May 3 2021, 8:16 PM · Restricted Project

May 2 2021

arcbbb updated the diff for D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.

address Roger's comment

i. add MIR tests.
May 2 2021, 11:57 PM · Restricted Project

Apr 29 2021

arcbbb updated the summary of D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.
Apr 29 2021, 12:15 AM · Restricted Project

Apr 28 2021

arcbbb accepted D101472: [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31..

LGTM too.

Apr 28 2021, 11:45 PM · Restricted Project

Apr 22 2021

arcbbb added a comment to D101002: [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32..

I am also thinking whether we can be faster by avoiding using ld/st unit
like:

vsetivli x0, #1, e32, m1
vmv.s.x v1, a0   // high 32b
vsetivli x0, #2, e32, m1
vslide1up.vx v1, v1, a1  // low 32b
vsetivli x0, a2, e64, m1
vrgather.vi v2, v1, #0
Apr 22 2021, 5:50 AM · Restricted Project
arcbbb accepted D100815: [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0..

LGTM

Apr 22 2021, 2:35 AM · Restricted Project

Apr 21 2021

arcbbb committed rG11072a0bdbc0: [RISCV][Clang] Add RVV AMO builtins (authored by arcbbb).
[RISCV][Clang] Add RVV AMO builtins
Apr 21 2021, 1:48 AM
arcbbb closed D100448: [RISCV][Clang] Add RVV AMO builtins.
Apr 21 2021, 1:48 AM · Restricted Project
arcbbb requested review of D100932: [RISCV] CleanupVSETVLI: Add phase to remove redundant VSETVLI instructions across basic blocks.
Apr 21 2021, 1:06 AM · Restricted Project

Apr 18 2021

arcbbb updated the diff for D100448: [RISCV][Clang] Add RVV AMO builtins.

re-formatted.

Apr 18 2021, 7:49 PM · Restricted Project
arcbbb updated the diff for D100448: [RISCV][Clang] Add RVV AMO builtins.

Addressed @khchen's comment.

Apr 18 2021, 7:35 PM · Restricted Project
arcbbb committed rG27edaee84e3e: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker… (authored by arcbbb).
[RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker…
Apr 18 2021, 7:06 PM
arcbbb closed D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker.
Apr 18 2021, 7:06 PM · Restricted Project

Apr 16 2021

arcbbb updated the diff for D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker.

Addressed @MaskRay 's comment

Apr 16 2021, 12:04 AM · Restricted Project

Apr 15 2021

arcbbb requested review of D100615: [RISCV][Driver] Make the ordering of CmdArgs consistent between RISCV::Linker and baremetal::Linker.
Apr 15 2021, 8:00 PM · Restricted Project

Apr 13 2021

arcbbb requested review of D100448: [RISCV][Clang] Add RVV AMO builtins.
Apr 13 2021, 11:42 PM · Restricted Project
arcbbb committed rGd5e962f1f20c: [RISCV] Implement COPY for Zvlsseg registers (authored by arcbbb).
[RISCV] Implement COPY for Zvlsseg registers
Apr 13 2021, 6:57 PM
arcbbb closed D100280: [RISCV] Implement COPY for Zvlsseg registers.
Apr 13 2021, 6:57 PM · Restricted Project

Apr 12 2021

arcbbb updated the diff for D100280: [RISCV] Implement COPY for Zvlsseg registers.

Address Craig's comment.

Apr 12 2021, 6:07 PM · Restricted Project
arcbbb updated the diff for D100280: [RISCV] Implement COPY for Zvlsseg registers.

Address HsiangKai's comment.

Apr 12 2021, 5:05 AM · Restricted Project

Apr 11 2021

arcbbb requested review of D100280: [RISCV] Implement COPY for Zvlsseg registers.
Apr 11 2021, 8:07 PM · Restricted Project

Mar 17 2021

arcbbb committed rGfca5d63aa8d4: [RISCV] Fix isel pattern of masked vmslt[u] (authored by arcbbb).
[RISCV] Fix isel pattern of masked vmslt[u]
Mar 17 2021, 8:18 PM
arcbbb closed D98839: [RISCV] Fix isel pattern of masked vmslt[u].
Mar 17 2021, 8:18 PM · Restricted Project
arcbbb requested review of D98839: [RISCV] Fix isel pattern of masked vmslt[u].
Mar 17 2021, 7:16 PM · Restricted Project

Mar 10 2021

arcbbb added a comment to D98236: [RISCV] Add SiFive-VIU75 for llvm.

I think we can hold this for the time being until it is ratified or no longer experimental.

Mar 10 2021, 6:22 PM · Restricted Project

Mar 8 2021

arcbbb requested review of D98236: [RISCV] Add SiFive-VIU75 for llvm.
Mar 8 2021, 11:02 PM · Restricted Project
arcbbb committed rG5cdb2e98608b: [RISCV][MC] Fix nf encoding for vector ld/st whole register (authored by arcbbb).
[RISCV][MC] Fix nf encoding for vector ld/st whole register
Mar 8 2021, 7:32 PM
arcbbb closed D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register.
Mar 8 2021, 7:31 PM · Restricted Project
arcbbb added a comment to D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register.

Thanks for the reminder, I'll file it once my bugzilla account is set up.

Mar 8 2021, 7:20 PM · Restricted Project
arcbbb added a comment to D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register.

Oops, sorry I didn't notice your patch, otherwise I would reply in yours instead. I just happened to encounter this runtime bug today.

Mar 8 2021, 8:54 AM · Restricted Project
arcbbb requested review of D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register.
Mar 8 2021, 8:24 AM · Restricted Project

Feb 24 2021

arcbbb accepted D97408: [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli.

LGTM

Feb 24 2021, 11:50 PM · Restricted Project

Feb 18 2021

arcbbb accepted D96934: [RISCV] Add support for fixed vector MULHU/MULHS..

LGTM

Feb 18 2021, 1:09 AM · Restricted Project

Feb 17 2021

arcbbb accepted D96873: [RISCV] Begin to support more subvector inserts/extracts.

LGTM

Feb 17 2021, 7:23 PM · Restricted Project

Feb 12 2021

arcbbb accepted D96505: [RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC).

LGTM!

Feb 12 2021, 7:51 PM · Restricted Project

Feb 9 2021

arcbbb added inline comments to D96352: [RISCV] Initial support for insert/extract subvector.
Feb 9 2021, 6:58 PM · Restricted Project
arcbbb updated the diff for D96352: [RISCV] Initial support for insert/extract subvector.

Updates.

  1. Fixed use of ConstantOperandVal()
  2. Fixed auto.
  3. Changed getRegClassIDForFixedLengthVector to getRegClassIDForLMUL
Feb 9 2021, 6:51 PM · Restricted Project
arcbbb added inline comments to D96352: [RISCV] Initial support for insert/extract subvector.
Feb 9 2021, 4:25 PM · Restricted Project
arcbbb updated the diff for D96352: [RISCV] Initial support for insert/extract subvector.

updates:

  1. clang-formatted.
  2. address Craig's comments.
Feb 9 2021, 4:14 PM · Restricted Project
arcbbb requested review of D96352: [RISCV] Initial support for insert/extract subvector.
Feb 9 2021, 9:12 AM · Restricted Project

Jan 31 2021

arcbbb added inline comments to D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions..
Jan 31 2021, 7:35 PM · Restricted Project
arcbbb added inline comments to D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions..
Jan 31 2021, 6:37 PM · Restricted Project

Jan 22 2021

arcbbb committed rG4edb63bbbe33: [RISCV] Fix intrinsic CodeGen test cases for vrgather (authored by arcbbb).
[RISCV] Fix intrinsic CodeGen test cases for vrgather
Jan 22 2021, 12:34 AM
arcbbb closed D95207: [RISCV] Fix RVV intrinsic CodeGen tests for vrgather.
Jan 22 2021, 12:34 AM · Restricted Project

Jan 21 2021

arcbbb updated the summary of D95207: [RISCV] Fix RVV intrinsic CodeGen tests for vrgather.
Jan 21 2021, 11:44 PM · Restricted Project
arcbbb requested review of D95207: [RISCV] Fix RVV intrinsic CodeGen tests for vrgather.
Jan 21 2021, 11:35 PM · Restricted Project
arcbbb accepted D95189: [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions.

LGTM. Thanks!

Jan 21 2021, 6:49 PM · Restricted Project
arcbbb committed rG96677503315e: [RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7 (authored by arcbbb).
[RISCV] Add intrinsics for RVV1.0 VFRSQRTE7 & VFRECE7
Jan 21 2021, 6:43 PM
arcbbb committed rG976cf53cc7a5: [RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0 (authored by arcbbb).
[RISCV] Add intrinsics for vector unordered indexed load in RVV 1.0
Jan 21 2021, 6:43 PM
arcbbb committed rGbea661d9a52f: [RISCV] Add intrinsics for RVV 1.0 vrgatherei16 (authored by arcbbb).
[RISCV] Add intrinsics for RVV 1.0 vrgatherei16
Jan 21 2021, 6:43 PM
arcbbb closed D95113: [RISCV] Add intrinsics for RVV v1.0 VFRSQRTE7 & VFRECE7.
Jan 21 2021, 6:43 PM · Restricted Project
arcbbb closed D95028: [RISCV] Add intrinsics for vector unordered indexed loads in RVV 1.0.
Jan 21 2021, 6:43 PM · Restricted Project
arcbbb closed D95014: [RISCV] Add intrinsics for vrgatherei16 instruction.
Jan 21 2021, 6:43 PM · Restricted Project

Jan 20 2021

arcbbb requested review of D95113: [RISCV] Add intrinsics for RVV v1.0 VFRSQRTE7 & VFRECE7.
Jan 20 2021, 7:22 PM · Restricted Project
arcbbb requested review of D95028: [RISCV] Add intrinsics for vector unordered indexed loads in RVV 1.0.
Jan 20 2021, 1:13 AM · Restricted Project

Jan 19 2021

arcbbb updated the diff for D95014: [RISCV] Add intrinsics for vrgatherei16 instruction.
Jan 19 2021, 11:12 PM · Restricted Project
arcbbb committed rG4dae2247fd62: [RISCV] refactor VPatBinary (NFC) (authored by arcbbb).
[RISCV] refactor VPatBinary (NFC)
Jan 19 2021, 7:17 PM
arcbbb closed D94951: [RISCV] refactor VPatBinary (NFC).
Jan 19 2021, 7:17 PM · Restricted Project
arcbbb added a comment to D94951: [RISCV] refactor VPatBinary (NFC).

I'm not sure I understand what's special about vrgathere16 that needs this refactor. Can you provide an explanation?

Jan 19 2021, 6:28 PM · Restricted Project
arcbbb requested review of D95014: [RISCV] Add intrinsics for vrgatherei16 instruction.
Jan 19 2021, 6:22 PM · Restricted Project
arcbbb requested review of D94951: [RISCV] refactor VPatBinary (NFC).
Jan 19 2021, 12:34 AM · Restricted Project

Jan 18 2021

arcbbb committed rG9cf511aa08ae: [RISCV] Add intrinsics for vector AMO operations (authored by arcbbb).
[RISCV] Add intrinsics for vector AMO operations
Jan 18 2021, 11:12 PM
arcbbb closed D94589: [RISCV] Add intrinsics for vector AMO instructions.
Jan 18 2021, 11:12 PM · Restricted Project

Jan 17 2021

arcbbb updated the diff for D94589: [RISCV] Add intrinsics for vector AMO instructions.

changed sra to srl

Jan 17 2021, 6:43 PM · Restricted Project