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Today

dmgreen accepted D91695: [ARM][AArch64] Adding Neoverse N2 CPU support.

Thanks for the changes. From what I can tell, this LGTM.

Mon, Nov 23, 8:09 AM · Restricted Project, Restricted Project
dmgreen added a comment to D90445: [SLP] Make SLPVectorizer to use `llvm.masked.gather` intrinsic.

If isLegalMaskedGather is returning false (as it will do for AArch64 NEON), then should this even be attempting to use gather/scatter? I would have thought that will never do worth it if it is just going to scalarize again?

Mon, Nov 23, 6:23 AM · Restricted Project
dmgreen added inline comments to D91704: [llvm-mca] Fix processing thumb instruction set.
Mon, Nov 23, 4:22 AM · Restricted Project
dmgreen added inline comments to D91077: [LoopVectorizer][SVE] Vectorize a simple loop with with a scalable VF..
Mon, Nov 23, 2:51 AM · Restricted Project
dmgreen added inline comments to D91704: [llvm-mca] Fix processing thumb instruction set.
Mon, Nov 23, 2:19 AM · Restricted Project
dmgreen accepted D91690: [LoopFlatten] Widen IV, cont'd.

Thanks. LGTM

Mon, Nov 23, 12:22 AM · Restricted Project
dmgreen added a comment to D91887: [ARM] Make t2DoLoopStartTP a terminator.

Can you quickly remind me about the different options/trade-offs here? Just as a refresher for me how everything fits together.

Mon, Nov 23, 12:22 AM · Restricted Project

Yesterday

dmgreen requested review of D91938: [ARM] MVE vabd .
Sun, Nov 22, 1:48 PM · Restricted Project
dmgreen requested review of D91937: [ISel] Port AArch64 SABD and UABD to DAGCombine.
Sun, Nov 22, 1:42 PM · Restricted Project
dmgreen committed rGc8c3a411c50f: [ARM] Ensure MVE_TwoOpPattern is used inside Predicate's (authored by dmgreen).
[ARM] Ensure MVE_TwoOpPattern is used inside Predicate's
Sun, Nov 22, 1:38 PM
dmgreen committed rGf3339b9f988c: [ARM] MVE VABD tests. NFC (authored by dmgreen).
[ARM] MVE VABD tests. NFC
Sun, Nov 22, 1:17 PM

Sat, Nov 21

dmgreen requested review of D91921: [ARM] Introduce MVETRUNC ISel lowering.
Sat, Nov 21, 12:17 PM · Restricted Project

Fri, Nov 20

dmgreen requested review of D91887: [ARM] Make t2DoLoopStartTP a terminator.
Fri, Nov 20, 12:03 PM · Restricted Project
dmgreen added a comment to D91800: [PassManager] Run Induction Variable Simplification pass *after* Recognize loop idioms pass, not before.

Do we have phase ordering tests for various memset/memcpy loops?

Fri, Nov 20, 7:21 AM · Restricted Project
dmgreen added a comment to D89800: [ARM][LowOverheadLoops] Don't generate a LOL if lr is redefined after the start.

When can this happen now? We added lr as a def of t2DoLoopStart so this kind of thing would not be possible, and we would not need to do this expensive / impossible checking so late in the backend, where it is so difficult to get really correct.

Fri, Nov 20, 6:57 AM · Restricted Project
dmgreen added inline comments to D91857: [ARM] Remove dead mov's in preheader of tail predicated loops.
Fri, Nov 20, 6:52 AM · Restricted Project
dmgreen added inline comments to D91866: [ARM] Cleanup for the MVETailPrediction pass.
Fri, Nov 20, 6:50 AM · Restricted Project
dmgreen requested review of D91866: [ARM] Cleanup for the MVETailPrediction pass.
Fri, Nov 20, 5:46 AM · Restricted Project
dmgreen committed rGf08c37da7bd4: [ARM] Disable WLSTP loops (authored by dmgreen).
[ARM] Disable WLSTP loops
Fri, Nov 20, 5:31 AM
dmgreen closed D91663: [ARM] Disable WLSTP loops.
Fri, Nov 20, 5:31 AM · Restricted Project
dmgreen added a comment to D91663: [ARM] Disable WLSTP loops.

Thanks. WLS can certainly be beneficial in places, so is best to leave on for non-tail predicated loop. We can try to make them less likely to revert and hopefully re-enable them for tail predicated loops in the future, once the performance/correctness is more reliable.

Fri, Nov 20, 5:28 AM · Restricted Project
dmgreen accepted D91848: [AArch64] Enable post RA scheduler for Cortex-R82.

OK fine, sure. Lets just do this bit first. LGTM

Fri, Nov 20, 4:02 AM · Restricted Project
dmgreen requested review of D91857: [ARM] Remove dead mov's in preheader of tail predicated loops.
Fri, Nov 20, 3:37 AM · Restricted Project
dmgreen added inline comments to D91848: [AArch64] Enable post RA scheduler for Cortex-R82.
Fri, Nov 20, 2:58 AM · Restricted Project
dmgreen added inline comments to D91690: [LoopFlatten] Widen IV, cont'd.
Fri, Nov 20, 1:18 AM · Restricted Project
dmgreen added a comment to D91848: [AArch64] Enable post RA scheduler for Cortex-R82.

Can you add a test line to the fuse-aes test? The postra feature is harder to test very well.

Fri, Nov 20, 12:53 AM · Restricted Project

Thu, Nov 19

dmgreen committed rG0e4cdfc56aed: [ARM] Add a WLS tail predication test. NFC (authored by dmgreen).
[ARM] Add a WLS tail predication test. NFC
Thu, Nov 19, 6:55 AM
dmgreen accepted D91790: [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition.

Thanks. LGTM

Thu, Nov 19, 5:44 AM · Restricted Project
dmgreen committed rG006b3bdeddb0: [ARM] Deliberately prevent inline asm in low overhead loops. NFC (authored by dmgreen).
[ARM] Deliberately prevent inline asm in low overhead loops. NFC
Thu, Nov 19, 5:29 AM
dmgreen closed D91257: [ARM] Deliberately prevent inline asm in low overhead loops. NFC.
Thu, Nov 19, 5:28 AM · Restricted Project
dmgreen added inline comments to D91690: [LoopFlatten] Widen IV, cont'd.
Thu, Nov 19, 4:33 AM · Restricted Project
dmgreen added inline comments to D90965: [IfCvt] Don't use pristine register for counting liveins for predicated instructions..
Thu, Nov 19, 2:28 AM · Restricted Project
dmgreen added inline comments to D91690: [LoopFlatten] Widen IV, cont'd.
Thu, Nov 19, 1:05 AM · Restricted Project

Wed, Nov 18

dmgreen added inline comments to D91690: [LoopFlatten] Widen IV, cont'd.
Wed, Nov 18, 2:11 PM · Restricted Project
dmgreen added inline comments to D91690: [LoopFlatten] Widen IV, cont'd.
Wed, Nov 18, 11:06 AM · Restricted Project
dmgreen added inline comments to D90935: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks.
Wed, Nov 18, 5:35 AM · Restricted Project
dmgreen added a comment to D91695: [ARM][AArch64] Adding Neoverse N2 CPU support.

Can you add the cpuid to host.cpp too?

Wed, Nov 18, 4:25 AM · Restricted Project, Restricted Project

Tue, Nov 17

dmgreen added a comment to D91267: [ARM] Remove copies from low overhead phi inductions..

Yeah this might look a little strange. This was really written for a following patch (D91358), where it was more about trying to create the new instructions without copies, than trying to specifically remove them. We do still need to remove those before the phi, but it seems to make sense to do that all together as we are already needing to check here. I was trying to get as much stuff out of the way as I could beforehand that other patch to simplify it.

Tue, Nov 17, 3:15 PM · Restricted Project
dmgreen requested review of D91663: [ARM] Disable WLSTP loops.
Tue, Nov 17, 3:05 PM · Restricted Project

Mon, Nov 16

dmgreen accepted D91561: [MachineScheduler] Inform pass infra of post-ra scheduler's dependencies.

Thanks, You even added MachineDominatorTree and MachineLoopInfo.

Mon, Nov 16, 1:23 PM · Restricted Project
dmgreen added a comment to D69814: [Scheduling] Enable AA in PostRA Machine scheduler.

Oh yeah. Sounds very sensible to me. Thanks!

Mon, Nov 16, 1:23 PM · Restricted Project
dmgreen added inline comments to D90935: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks.
Mon, Nov 16, 3:50 AM · Restricted Project
dmgreen committed rG48b43c9d4f03: [ARM] Cortex-M7 schedule (authored by dpenry).
[ARM] Cortex-M7 schedule
Mon, Nov 16, 2:16 AM
dmgreen closed D91355: [ARM] Cortex-M7 schedule.
Mon, Nov 16, 2:16 AM · Restricted Project
dmgreen added inline comments to D91077: [LoopVectorizer][SVE] Vectorize a simple loop with with a scalable VF..
Mon, Nov 16, 12:00 AM · Restricted Project

Sun, Nov 15

dmgreen updated the diff for D88382: [VPlan] Turn VPReductionRecipe into a VPValue.

Ooops. I thought this was already using State.set, but uploaded the wrong version. Now with that and the other changes.

Sun, Nov 15, 2:12 PM · Restricted Project
dmgreen added inline comments to D88447: [VPlan] Switch VPWidenRecipe to be a VPValue.
Sun, Nov 15, 10:40 AM · Restricted Project
dmgreen updated the diff for D88447: [VPlan] Switch VPWidenRecipe to be a VPValue.

Rebase and address comments

Sun, Nov 15, 10:40 AM · Restricted Project
dmgreen updated the diff for D88382: [VPlan] Turn VPReductionRecipe into a VPValue.

Rebase

Sun, Nov 15, 10:31 AM · Restricted Project
dmgreen added inline comments to D91266: [ARM][SchedModels] Add support for branch forms of ALU instructions to Cortex-A57 model.
Sun, Nov 15, 8:19 AM · Restricted Project
dmgreen added a comment to D90844: [TableGen][SchedModels] Fix read/write variant substitution #2.

Hello. Sorry for the delay. I don't know this code super well and was trying to figure out what the different parts were doing. I see that the produced output has code like this:

case 703: // t2ADDSrs
  if (SchedModel->getProcessorID() == 4) { // CortexA57Model
    if ((TII->isSwiftFastImmShift(MI))
        && TII->isPredicated(*MI))
      return 1066; // _ReadDefault
  }

The isSwiftFastImmShift is odd, when paired with a CortexA57Model, and comes from using StartIdx's PredTerm in TransVec.emplace_back(TransVec[StartIdx].PredTerm) I think. The _ReadDefault as the schedule class also sounds odd to me, as opposed to something that would use Writes too.

Sun, Nov 15, 8:11 AM · Restricted Project

Sat, Nov 14

dmgreen committed rG2104783d024c: [AArch64] Remove unused check prefixes. NFC (authored by dmgreen).
[AArch64] Remove unused check prefixes. NFC
Sat, Nov 14, 10:30 AM
dmgreen committed rG32556a983288: [ARM] Remove more unused check prefixes, NFC (authored by dmgreen).
[ARM] Remove more unused check prefixes, NFC
Sat, Nov 14, 7:38 AM

Fri, Nov 13

dmgreen accepted D90640: [LoopFlatten] Widen the IV.

Thanks. LGTM.

Fri, Nov 13, 6:58 AM · Restricted Project
dmgreen added a comment to D88380: [VPlan] Extend VPValue to also model sub- & 'virtual' values..

OK sounds great. I did not know that MLIR could represent multiple values, that's good to see.

Fri, Nov 13, 4:17 AM · Restricted Project
dmgreen added a comment to D91346: [AArch64] Add FCMLA AArch64ISD node..

OK sure. I was expecting some ISel lowering, to be honest. And perhaps for a vplan patch to appear :)

Fri, Nov 13, 4:09 AM · Restricted Project
dmgreen accepted D91345: [AArch64] Fix rottype use in complex instr defs..

Like I said on the other review, sometimes reviews can be split up too much into things that are not even testable.

Fri, Nov 13, 12:46 AM · Restricted Project
dmgreen added a comment to D90640: [LoopFlatten] Widen the IV.

now using RecursivelyDeleteDeadPHINode at the end to clean up dead phis. Doing this earlier proved to be a bit tricky with a few things in flight, but at least a nice clean up at the end.

Fri, Nov 13, 12:45 AM · Restricted Project

Thu, Nov 12

dmgreen added inline comments to D90935: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks.
Thu, Nov 12, 10:04 AM · Restricted Project
dmgreen accepted D91355: [ARM] Cortex-M7 schedule.

Ah Brilliant. Thanks for putting this up. We have been using this internally for some time to excellent effect.

Thu, Nov 12, 8:28 AM · Restricted Project
dmgreen added reviewers for D91358: [ARM][RegAlloc] Add t2LoopEndDec: MatzeB, qcolombet, SjoerdMeijer, samparker.
Thu, Nov 12, 8:04 AM · Restricted Project
dmgreen requested review of D91358: [ARM][RegAlloc] Add t2LoopEndDec.
Thu, Nov 12, 8:04 AM · Restricted Project
dmgreen added a comment to D91346: [AArch64] Add FCMLA AArch64ISD node..

Sounds OK, but I think there's such a thing as splitting up a patch too much! And if it's not possible to add tests for something, that can be a bad sign.

Thu, Nov 12, 6:52 AM · Restricted Project
dmgreen committed rG11dee2eae2f7: [ARM] Ensure CountReg definition dominates InsertPt when creating… (authored by dmgreen).
[ARM] Ensure CountReg definition dominates InsertPt when creating…
Thu, Nov 12, 5:48 AM
dmgreen closed D91287: [ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP.
Thu, Nov 12, 5:48 AM · Restricted Project
dmgreen updated the diff for D91287: [ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP.

Add a check that the InsertPt isn't end() still.

Thu, Nov 12, 3:37 AM · Restricted Project
dmgreen updated the diff for D91273: [ARM] Revert low overhead loops with calls before registry allocation..
Thu, Nov 12, 2:21 AM · Restricted Project
dmgreen added inline comments to D91273: [ARM] Revert low overhead loops with calls before registry allocation..
Thu, Nov 12, 2:19 AM · Restricted Project
dmgreen added inline comments to D91287: [ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP.
Thu, Nov 12, 2:05 AM · Restricted Project
dmgreen committed rG1551d8dd4839: [ARM] Remove unused check labels. NFC (authored by dmgreen).
[ARM] Remove unused check labels. NFC
Thu, Nov 12, 12:38 AM
dmgreen added a comment to D91060: [LoopVectorizer] NFC: Remove unnecessary asserts that VF cannot be scalable..

As far as I can tell these do sound OK, except perhaps for the one I put a question on.

Thu, Nov 12, 12:31 AM · Restricted Project
dmgreen added inline comments to D90935: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks.
Thu, Nov 12, 12:06 AM · Restricted Project

Wed, Nov 11

dmgreen added inline comments to D90640: [LoopFlatten] Widen the IV.
Wed, Nov 11, 2:27 PM · Restricted Project
dmgreen added a comment to D91255: [AArch64] Rearrange (dup(sext/zext)) to (sext/zext(dup)).

So what this seems to be proposing is that ever instance of dup(sext(..)) is transformed into sext(dup(..)). That's a pretty general transform. Off the top of my head... the extend could be free in places (zext i32->i64) but it may allow more folding into other instructions like the smull/saddl/ssubl it can allow here. If the operand is a load, that should at least have been folded into a single instruction already prior to the dup being made. But I would probably expect a sxth+dup to be quicker than a dup+sshll in general.

Wed, Nov 11, 2:02 PM · Restricted Project
dmgreen added inline comments to D91271: [AArch64] Attempt to sink mul operands.
Wed, Nov 11, 1:54 PM · Restricted Project
dmgreen committed rG3e5b8d83f752: [AArch4] Regenerate test checks for f16-imm.ll. NFC (authored by dmgreen).
[AArch4] Regenerate test checks for f16-imm.ll. NFC
Wed, Nov 11, 11:42 AM
dmgreen requested review of D91287: [ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP.
Wed, Nov 11, 11:23 AM · Restricted Project
dmgreen requested review of D91273: [ARM] Revert low overhead loops with calls before registry allocation..
Wed, Nov 11, 9:01 AM · Restricted Project
dmgreen requested review of D91267: [ARM] Remove copies from low overhead phi inductions..
Wed, Nov 11, 7:52 AM · Restricted Project
dmgreen added a comment to D91255: [AArch64] Rearrange (dup(sext/zext)) to (sext/zext(dup)).

This looks like two separate patches to me. One that folds dup(ext(..)) into ext(dup(..)), and another that tries to sink operands into a loop.

Wed, Nov 11, 7:50 AM · Restricted Project
dmgreen requested review of D91257: [ARM] Deliberately prevent inline asm in low overhead loops. NFC.
Wed, Nov 11, 6:51 AM · Restricted Project
dmgreen added a comment to D90687: [LV] Clamp VF hint when unsafe.

LGTM as well. It seems the current patch fixes the example I pasted in my previous comment.

Wed, Nov 11, 1:13 AM · Restricted Project

Tue, Nov 10

dmgreen accepted D91192: [ARM] Fix PR 47980: Use constrainRegClass during foldImmediate opt..

Hello. Nice test. Thanks for putting it together. LGTM

Tue, Nov 10, 12:41 PM · Restricted Project
dmgreen added a comment to D90591: [ARM] Introduce t2DoLoopStartTP.

Ah, Thanks! I'll try and fix that up now

Tue, Nov 10, 11:33 AM · Restricted Project
dmgreen added inline comments to D90935: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks.
Tue, Nov 10, 10:59 AM · Restricted Project
dmgreen accepted D90402: [LoopFlatten] Run it earlier, just before IndVarSimplify.

LGTM

Tue, Nov 10, 10:54 AM · Restricted Project
dmgreen accepted D90940: [LoopFlatten] Make it a FunctionPass.

Thanks for checking. LGTM

Tue, Nov 10, 10:49 AM · Restricted Project
dmgreen committed rG08d1c2d4701f: [ARM] Introduce t2DoLoopStartTP (authored by dmgreen).
[ARM] Introduce t2DoLoopStartTP
Tue, Nov 10, 10:08 AM
dmgreen closed D90591: [ARM] Introduce t2DoLoopStartTP.
Tue, Nov 10, 10:08 AM · Restricted Project
dmgreen committed rGdbe1bf63aa04: [ARM] Cleanup for ARMLowOverheadLoops. NFC (authored by dmgreen).
[ARM] Cleanup for ARMLowOverheadLoops. NFC
Tue, Nov 10, 9:28 AM
dmgreen committed rGc7e275388e3f: [ARM] Don't aggressively unroll vector remainder loops (authored by dmgreen).
[ARM] Don't aggressively unroll vector remainder loops
Tue, Nov 10, 9:02 AM
dmgreen closed D90055: [ARM] Don't aggressively unroll vector remainder loops.
Tue, Nov 10, 9:01 AM · Restricted Project
dmgreen committed rG7f34b9ddf817: [Sphinx] Fix langref formatting. NFC (authored by dmgreen).
[Sphinx] Fix langref formatting. NFC
Tue, Nov 10, 8:48 AM
dmgreen committed rG73a6cd4b6b58: [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR (authored by dmgreen).
[ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR
Tue, Nov 10, 8:29 AM
dmgreen closed D89883: [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR.
Tue, Nov 10, 8:29 AM · Restricted Project
dmgreen committed rGb2ac9681a700: [ARM] Alter t2DoLoopStart to define lr (authored by dmgreen).
[ARM] Alter t2DoLoopStart to define lr
Tue, Nov 10, 7:58 AM
dmgreen closed D89881: [ARM] Alter t2DoLoopStart to define lr.
Tue, Nov 10, 7:58 AM · Restricted Project
dmgreen accepted D90880: [LoopVectorizer] NFC: Return ElementCount from compute[Feasible]MaxVF.

Makes sense, thanks

Tue, Nov 10, 6:35 AM · Restricted Project

Mon, Nov 9

dmgreen added inline comments to D90940: [LoopFlatten] Make it a FunctionPass.
Mon, Nov 9, 12:04 PM · Restricted Project
dmgreen accepted D90879: [LoopVectorizer] NFC: Propagate ElementCount to more interfaces..
Mon, Nov 9, 11:58 AM · Restricted Project