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Fri, Oct 18

kbelochapka committed rL375274: Request access for kbelochapka.
Request access for kbelochapka
Fri, Oct 18, 12:59 PM

May 31 2018

kbelochapka added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Hi Quentin,
The dead flag on those registers is not set because we do not run "Live Variable Analysis" pass on -O0 optimization level.
We can add Live Variable Analysis pass prior of execution of Fast Register Allocator pass, but this will cause ~59 LIT tests to fail.
At the same time, in some situations the produced assembler code is more clean, does not contain unnecessary register spills.
And I am not sure can this potentially affect a code debuggability or not.
What would be your suggestion? Shall we add Live Variable Analysis pass on -O0?

May 31 2018, 4:42 PM

May 24 2018

kbelochapka updated the diff for D42677: added support for -fdiagnostics-format option to SourceMgr class (PR36117).
May 24 2018, 5:32 PM
kbelochapka updated the diff for D42678: added passing -fdiagnostics-format option from clang driver to cc1as (PR36117).
May 24 2018, 5:30 PM

Feb 22 2018

kbelochapka added a comment to D43544: [Transforms][SROA] Fixed assertion crash (PR30416).

Test?

Feb 22 2018, 2:50 PM
kbelochapka updated the diff for D43544: [Transforms][SROA] Fixed assertion crash (PR30416).
Feb 22 2018, 2:49 PM

Feb 21 2018

kbelochapka added a comment to D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).

Since a "naked" function can only have nothing but "asm" statements inside, and those "asm" statements can not have input or output parameters, it is safe to just disable any registers spilling for a "naked" function.

Do naked functions have vregs at all then? Could we just skip the whole register allocation process in runOnMachineFunction() instead?

Feb 21 2018, 12:21 PM

Feb 20 2018

kbelochapka created D43544: [Transforms][SROA] Fixed assertion crash (PR30416).
Feb 20 2018, 7:35 PM
kbelochapka created D43542: [CodeGen][FastRegAlloc] Disable registers spilling for a naked function (PR28641).
Feb 20 2018, 6:22 PM

Jan 30 2018

kbelochapka updated the diff for D42678: added passing -fdiagnostics-format option from clang driver to cc1as (PR36117).
Jan 30 2018, 3:25 PM

Jan 29 2018

kbelochapka created D42678: added passing -fdiagnostics-format option from clang driver to cc1as (PR36117).
Jan 29 2018, 8:37 PM
kbelochapka created D42677: added support for -fdiagnostics-format option to SourceMgr class (PR36117).
Jan 29 2018, 8:23 PM

Jan 10 2018

kbelochapka added a comment to D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

Four instructions perhaps:

vextractf128, vextractf128, vshufps, vblendps?

It is better than current six instructions.

Jan 10 2018, 8:24 PM
kbelochapka added a comment to D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

Hi Craig, I placed simple test on the Bugzilla, your fix seems to be working fine.
The only thing, there are couple or more of shuffle masks which looks like they can be a subject of the similar optimization, but the generated code for them remained not optimized.
IN0: |0|1| | |4|5| | |
IN1: |8|9| | | | |E|F|
MASK011: 0,1,4,5,8,9,14,15
IN0: |0|1| | | | |6|7|
IN1: |8|9| | |C|D| | |
MASK012: 0,1,6,7,8,9,12,13

Jan 10 2018, 6:54 PM

Jan 5 2018

kbelochapka added a comment to D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

can you add a test for "128 bit line swapped" shuffle masks: [8, 10, 12, 14, 0, 2, 4, 6,], [9, 11, 13, 15, 1, 3, 5, 7 ]

Jan 5 2018, 6:39 PM
kbelochapka added a comment to D41794: [X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation.

currently you call lowerVectorShuffleSplitLowHigh() form lowerV8F32VectorShuffle() only.

Jan 5 2018, 6:18 PM

Dec 12 2017

kbelochapka updated the diff for D40633: [PCG] Poor shuffle lane tracking (PR35454 ).

Reimplemented the fix based on the reviewers recommendations.
Now the fix makes an attempt to transform sequence :
SHUFFLE<T0>(MASK) --> BITCACT<T1> --> BINOP<T1> --> BITCAST<T0> --> SHUFFLE<T0>(MASK)
into:
BITCAST<T1> --> BINOP<T1> --> SHUFFLE<T1>(NEW_MASK)
It is always possible when sizeof of BINOP vector element type is smaller than sizeof of SHUFFLE vector element type,
and sometimes is possible when it is not.

Dec 12 2017, 4:21 PM

Nov 30 2017

kbelochapka added a comment to D40633: [PCG] Poor shuffle lane tracking (PR35454 ).

Thanks guys for valuable comments, will reimplementing the fix as suggested by Sanyaj.

Nov 30 2017, 6:10 PM

Nov 29 2017

kbelochapka created D40633: [PCG] Poor shuffle lane tracking (PR35454 ).
Nov 29 2017, 7:58 PM

Nov 21 2017

kbelochapka added a comment to D35587: [X86][ASM] Fixed assertion crash with inline asm (PR14393).

Simon, can you please take a second look at this one when you have a chance.

Nov 21 2017, 12:22 PM

Nov 20 2017

kbelochapka added a comment to D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .

Craig, can you please when you have chance, review the update that I had made for the initial fix of the bug.

Nov 20 2017, 6:29 PM

Nov 13 2017

kbelochapka updated the diff for D39704: [X86] [CodeGen] Compiler not using SHLD/SHRD instructions when doing double shift pattern combine for 16bit or 8bit arguments (PR35155).

Updates the fix to support 32bit mode, moved all non 64 bit tests into shift-double.ll

Nov 13 2017, 6:53 PM

Nov 6 2017

kbelochapka created D39704: [X86] [CodeGen] Compiler not using SHLD/SHRD instructions when doing double shift pattern combine for 16bit or 8bit arguments (PR35155).
Nov 6 2017, 3:06 PM

Sep 26 2017

kbelochapka created D38302: [X86][MC] Fixed crash when assembling a file that contains section with 64-bit alignment (PR34726).
Sep 26 2017, 6:49 PM

Sep 25 2017

kbelochapka committed rL314140: [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86….
[X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86…
Sep 25 2017, 12:28 PM
kbelochapka closed D37945: [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617) by committing rL314140: [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86….
Sep 25 2017, 12:28 PM
kbelochapka committed rL314044: [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038)..
[X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).
Sep 25 2017, 5:07 AM
kbelochapka closed D38117: [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038) by committing rL314044: [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038)..
Sep 25 2017, 5:07 AM

Sep 20 2017

kbelochapka created D38117: [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038) .
Sep 20 2017, 7:04 PM
kbelochapka added a comment to D13592: [MC] Fixed parsing of macro arguments where expressions with spaces are present..

Closing bug PR24319 https://bugs.llvm.org/show_bug.cgi?id=24319 because your fix had fixed this bug as well.

Sep 20 2017, 1:06 PM

Sep 15 2017

kbelochapka created D37945: [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617).
Sep 15 2017, 6:51 PM
kbelochapka requested review of D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .

Reimplemented fixup overflow check, treat PC relative fixup values as signed values and absolute fixup values as unsigned values.

Sep 15 2017, 2:59 PM
kbelochapka abandoned D35601: [X86][BITREVERSE] Optimized bitreverse builtin for 8 bit scalar integer (PR31810).

The performance measurement testing did not show any performance benefit for the proposed 8bit bit reversal intrinsic implementation over the existing one.

Sep 15 2017, 2:54 PM

Sep 1 2017

kbelochapka updated the diff for D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .

treat PC relative fixups as signed values and absolute fixups as unsigned values

Sep 1 2017, 4:11 PM

Aug 24 2017

kbelochapka updated the diff for D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .

as was pointed by Craig, corrected isIntN() argument mistake

Aug 24 2017, 4:03 PM
kbelochapka added inline comments to D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .
Aug 24 2017, 3:57 PM
kbelochapka added inline comments to D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .
Aug 24 2017, 3:19 PM

Aug 21 2017

kbelochapka created D36991: [x86] [MC] fixed no error diagnostic for out-of-range jrcxz/jecxz/jcxz (PR24072) .
Aug 21 2017, 4:55 PM

Aug 7 2017

kbelochapka updated the diff for D35587: [X86][ASM] Fixed assertion crash with inline asm (PR14393).

limit showing error message only to the cases that require copy of non floating point datum into MVT::f80 container.

Aug 7 2017, 4:15 PM

Jul 31 2017

kbelochapka committed rL309614: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).
[X86][MMX] Added custom lowering action for MMX SELECT (PR30418)
Jul 31 2017, 1:12 PM
kbelochapka closed D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418) by committing rL309614: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).
Jul 31 2017, 1:12 PM

Jul 18 2017

kbelochapka retitled D35601: [X86][BITREVERSE] Optimized bitreverse builtin for 8 bit scalar integer (PR31810) from [X86][BITREVERSE] Optimized bitreverse builtin for 8 bit scalar integer to [X86][BITREVERSE] Optimized bitreverse builtin for 8 bit scalar integer (PR31810).
Jul 18 2017, 7:17 PM
kbelochapka created D35601: [X86][BITREVERSE] Optimized bitreverse builtin for 8 bit scalar integer (PR31810).
Jul 18 2017, 7:13 PM
kbelochapka created D35587: [X86][ASM] Fixed assertion crash with inline asm (PR14393).
Jul 18 2017, 4:22 PM
kbelochapka updated the diff for D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).

test regenerated with update_llc_test_checks.py, unnecessary artifacts removed.

Jul 18 2017, 1:01 PM

Jul 14 2017

kbelochapka updated the diff for D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).

updated poorly formated diff file

Jul 14 2017, 1:20 PM

Jul 13 2017

kbelochapka updated the diff for D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).

replaced llc option -mcpu for -mtriple, the diff file reformatted

Jul 13 2017, 2:50 PM

Jul 12 2017

kbelochapka updated the diff for D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).

fix now works for 32bit mode, the test updated from crash checking to positive

Jul 12 2017, 7:30 PM
kbelochapka retitled D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418) from Fix for pr30418 - error in backend: Cannot select: t17: x86mmx = select_cc t2, Constant:i64<0>, t7, t8, seteq:ch to [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).
Jul 12 2017, 6:28 PM

Jun 26 2017

kbelochapka created D34661: [X86][MMX] Added custom lowering action for MMX SELECT (PR30418).
Jun 26 2017, 6:06 PM