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Wed, Oct 14

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

@MaskRay Thanks, that's first time I know the suffix -SAME :P

Wed, Oct 14, 8:43 PM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog:

  • Update testcase according to MaskRay's suggestion.
Wed, Oct 14, 8:41 PM · Restricted Project, Restricted Project
kito-cheng added reviewers for D89288: [RISCV] Enable the use of the old sptbr name: luismarques, lenary.
Wed, Oct 14, 7:41 PM · Restricted Project
kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

RISCV supports -mcpu with default empty arch to align gcc's -mtune behavior since clang didn't support -mtune before. But now clang has -mtune, is it a good idea to remove those options? (ex. rocket-rv32/rv64, sifive-7-rv32/64)

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Wed, Oct 14, 1:06 AM · Restricted Project, Restricted Project
kito-cheng updated the diff for D89025: [RISCV] Add -mtune support.

ChangeLog

  • Fix wording in comment
  • Add more comment in testcase
  • Fix format issue.
Wed, Oct 14, 1:02 AM · Restricted Project, Restricted Project

Tue, Oct 13

kito-cheng added a comment to D89025: [RISCV] Add -mtune support.

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang with GCC. But I wonder if this might be too problematic, in terms of compatibility.

Tue, Oct 13, 8:52 PM · Restricted Project, Restricted Project

Mon, Oct 12

kito-cheng added inline comments to D89244: [RISCV][ASAN] Fix TLS offsets.
Mon, Oct 12, 7:59 PM · Restricted Project

Wed, Oct 7

kito-cheng requested review of D89025: [RISCV] Add -mtune support.
Wed, Oct 7, 8:45 PM · Restricted Project, Restricted Project
kito-cheng requested review of D88951: [Tablegen][SubtargetEmitter] Print TuneCPU in Subtarget::ParseSubtargetFeatures.
Wed, Oct 7, 2:12 AM · Restricted Project

Thu, Sep 24

kito-cheng accepted D87997: [RISCV][crt] support building without init_array.

But this logic is enabled only if CRT_HAS_INITFINI_ARRAY is not defined. Which is controlled by cmake (configuration script). In addition, other architectures (x86, sparc, arm, aarch64, sparc, powerpc) - do allow such fallback option. It just seems strange that RISCV does not have one.

Thu, Sep 24, 2:33 AM · Restricted Project
kito-cheng added a comment to D87997: [RISCV][crt] support building without init_array.

RISC-V LLVM and GCC are default using init_array, curious why we need this?

Actually, yes. You are correct - this one is not needed for ASAN support... My understanding is that this may be needed if we link against some custom runtime. I'll adjust the description of the patch.

Thu, Sep 24, 2:07 AM · Restricted Project

Tue, Sep 22

kito-cheng added a comment to D87997: [RISCV][crt] support building without init_array.

RISC-V LLVM and GCC are default using init_array, curious why we need this?

Tue, Sep 22, 8:18 PM · Restricted Project

Aug 19 2020

kito-cheng added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

GCC part should review at gcc-patch mailing list instead of here, for other files (sanitizer_platform.h, sanitizer_common.h and sanitizer_symbolizer_libcdep.cpp), it's right place to review, but it should using the diff which generated within LLVM source-tree, and GCC will sync libsanitizer after LLVM is accepted.

What about config/riscv/riscv.c? Should I place it here to review?

Aug 19 2020, 12:28 AM

Aug 18 2020

kito-cheng added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

Aug 18 2020, 11:36 PM

Aug 6 2020

kito-cheng added a comment to D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension.

Zvamo implies A-extension.

I think it's require instead of imply?

Aug 6 2020, 11:53 PM · Restricted Project

May 28 2020

kito-cheng added inline comments to D80690: [RISCV] Support libunwind for riscv32.
May 28 2020, 7:15 PM · Restricted Project, Restricted Project

May 7 2020

kito-cheng added a comment to D79521: [RISCV] Add SiFive's interrupt modes.

Upstream didn't support those SiFive specific function attribute, and there is no plan to upstream unless CLIC ratified.
And I guess the attribute name would changed after GCC upstream, at least the prefix of SiFive- would be removed.

May 7 2020, 7:20 AM · Restricted Project

Apr 30 2020

kito-cheng added inline comments to D71124: [RISCV] support clang driver to select cpu.
Apr 30 2020, 7:56 AM · Restricted Project, Restricted Project
kito-cheng added a comment to D71124: [RISCV] support clang driver to select cpu.

Another proposal for -mcpu and -mtune:

Apr 30 2020, 2:06 AM · Restricted Project, Restricted Project

Feb 23 2020

kito-cheng added a comment to D74023: [RISCV] ELF attribute section for RISC-V.

Could you add following kind of test:

Feb 23 2020, 10:23 PM · Restricted Project, Restricted Project

Jan 10 2020

kito-cheng added a comment to D69987: [RISCV] Assemble/Disassemble v-ext instructions..

It seems to me that all remarks have already been addressed. Is there anything holding this patch? For it pretty much LGTM.

Jan 10 2020, 11:57 PM · Restricted Project, Restricted Project

Jan 9 2020

kito-cheng added a comment to D72245: [PoC][RISCV][LTO] Pass target-abi via module flag metadata.

Seems like this patch mixed with LTO related changes? Could you clean it up?

Jan 9 2020, 8:49 AM · Restricted Project, Restricted Project

Nov 14 2019

kito-cheng added a comment to D70116: [RISCV] add subtargets initialized with target feature.

In addition, I think my testcase is so weird and it does not make sense there are different isa extension are used in the same compilation unit...

Nov 14 2019, 7:30 AM · Restricted Project

Nov 8 2019

kito-cheng added inline comments to D69987: [RISCV] Assemble/Disassemble v-ext instructions..
Nov 8 2019, 1:15 AM · Restricted Project, Restricted Project

Oct 16 2019

kito-cheng added a reviewer for D68685: [RISCV] Scheduler description for Rocket Core: HsiangKai.
Oct 16 2019, 12:47 AM · Restricted Project

Oct 8 2019

kito-cheng added inline comments to D68685: [RISCV] Scheduler description for Rocket Core.
Oct 8 2019, 11:08 PM · Restricted Project

Sep 17 2019

kito-cheng added inline comments to D67508: [RISCV] support mutilib in baremetal environment.
Sep 17 2019, 3:33 PM · Restricted Project
kito-cheng committed rG42fe2fc8c935: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow (authored by kito-cheng).
[RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow
Sep 17 2019, 1:19 AM
kito-cheng committed rG645593844164: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly (authored by kito-cheng).
[RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
Sep 17 2019, 1:10 AM

Sep 12 2019

kito-cheng added inline comments to D67409: [RISCV] enable LTO support, pass some options to linker..
Sep 12 2019, 1:48 PM · Restricted Project

Sep 2 2019

kito-cheng created D67066: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow.
Sep 2 2019, 2:16 AM · Restricted Project, Restricted Project
kito-cheng created D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly.
Sep 2 2019, 2:11 AM · Restricted Project, Restricted Project

Aug 1 2019

kito-cheng added inline comments to D65497: [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating Libcall.
Aug 1 2019, 5:25 AM · Restricted Project

Jul 2 2019

kito-cheng committed rGeb9bc3827605: [ELF][RISCV] Support RISC-V in getBitcodeMachineKind (authored by kito-cheng).
[ELF][RISCV] Support RISC-V in getBitcodeMachineKind
Jul 2 2019, 7:14 PM

Jul 1 2019

kito-cheng updated the diff for D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.

Add 2 test cases.

Jul 1 2019, 10:39 PM · Restricted Project
kito-cheng added a comment to D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.

@MaskRay Thanks, I'll add test case soon :)

Jul 1 2019, 8:42 PM · Restricted Project

Feb 19 2019

kito-cheng committed rG303217e8b43d: [RISCV] Implement pseudo instructions for load/store from a symbol address. (authored by kito-cheng).
[RISCV] Implement pseudo instructions for load/store from a symbol address.
Feb 19 2019, 7:32 PM

Feb 10 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Update test/MC/RISCV/rvi-pseudos-invalid.s
Feb 10 2019, 7:28 PM · Restricted Project

Feb 5 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Fix parseBareSymbol with a constant symbols.
  • Rebase to D55325
Feb 5 2019, 10:47 AM · Restricted Project

Jan 24 2019

kito-cheng added a comment to D57141: [RISCV] Add implied zero offset load/store alias patterns.

@jrtc27 feel free to upload your one, it's just a 5 minute quick patch :P

Jan 24 2019, 6:56 PM · Restricted Project

Jan 23 2019

kito-cheng created D57141: [RISCV] Add implied zero offset load/store alias patterns.
Jan 23 2019, 11:31 PM · Restricted Project

Jan 16 2019

kito-cheng updated the diff for D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Changes:

  • Update testcase, R_RISCV_RELAX won't bind with symbol to fit binutils's behavior.
Jan 16 2019, 6:32 PM

Jan 14 2019

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Add missing tests
Jan 14 2019, 10:31 PM · Restricted Project

Jan 10 2019

kito-cheng added a comment to D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Okay, I'll take a look :)

Jan 10 2019, 8:38 AM
kito-cheng added inline comments to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Jan 10 2019, 7:58 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Merge emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol
  • Fix wrong operand type and syntax for floating point load instruction.
Jan 10 2019, 7:53 AM · Restricted Project

Oct 15 2018

kito-cheng added a comment to D53291: add riscv32e to the llvm.

rv32e arch and ilp32e ABI is decoupling in GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.

Oct 15 2018, 7:26 PM · Restricted Project

Oct 4 2018

kito-cheng added a comment to D51828: [RISCV] Fix disassembling of fence instruction with invalid field.

Hi Ana:

Oct 4 2018, 12:52 AM
kito-cheng added a comment to D48430: [RISCV] Add support for lowering jumptables.

GCC using 5 as threshold to decide using jump table or not for RISC-V and LLVM using 4.

Oct 4 2018, 12:26 AM

Sep 26 2018

kito-cheng added inline comments to D38719: [llvm-dwarfdump] Verify compatible TAG for attributes..
Sep 26 2018, 1:37 AM · debug-info

Sep 17 2018

kito-cheng created D52165: [RISCV] Support RISC-V in getBitcodeMachineKind.
Sep 17 2018, 1:59 AM · Restricted Project

Aug 29 2018

kito-cheng added inline comments to D50634: [RISCV] Add support for local PIC addressing.
Aug 29 2018, 2:21 AM

Aug 22 2018

kito-cheng updated the diff for D50043: [RISCV] RISC-V using -fuse-init-array by default.

Changes:

  • Add test.
Aug 22 2018, 10:26 AM
kito-cheng updated the diff for D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Changes:

  • Move declaration of RelaxCandidate.
  • Add comment.
  • Update testcase
Aug 22 2018, 10:01 AM
kito-cheng added a comment to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Hi Roger:

Aug 22 2018, 8:27 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Rebase.
Aug 22 2018, 8:23 AM · Restricted Project

Aug 13 2018

kito-cheng added inline comments to D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Aug 13 2018, 2:30 AM · Restricted Project
kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..

Changes:

  • Rename functions
    • emitLoadSymbolAddress -> emitLoadSymbolAddressHi
    • emitLoadWithSymbol -> emitLoadSymbol
    • emitStoreWithSymbol -> emitStoreSymbol
  • Return shouldForceImediateOperand to true for new pseudo instructions.
  • Add negative test
Aug 13 2018, 2:26 AM · Restricted Project

Aug 9 2018

kito-cheng updated the diff for D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
  • Add default case in switch.
Aug 9 2018, 1:59 AM · Restricted Project
kito-cheng created D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address..
Aug 9 2018, 1:55 AM · Restricted Project

Aug 2 2018

kito-cheng updated the diff for D50217: [RISCV] Add mnemonic alias: move, sbreak and scall..

Rearrange order for testcase.

Aug 2 2018, 8:12 PM
kito-cheng created D50217: [RISCV] Add mnemonic alias: move, sbreak and scall..
Aug 2 2018, 8:08 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Changes:

  • Update testcase for rv32i-aliases-invalid.s and rv64i-aliases-invalid.s
  • Fix rv32i-invalid.s
Aug 2 2018, 7:53 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Changes:

  • Add addw, sllw, srlw and sraw including testcase.
  • Add comment in testcase.
Aug 2 2018, 3:08 AM

Jul 31 2018

kito-cheng added inline comments to D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..
Jul 31 2018, 6:34 PM
kito-cheng updated the diff for D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..

Update testcase.

Jul 31 2018, 3:22 AM
kito-cheng created D50046: [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate..
Jul 31 2018, 3:07 AM
kito-cheng created D50043: [RISCV] RISC-V using -fuse-init-array by default.
Jul 31 2018, 1:39 AM
kito-cheng added a comment to D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target.

ping, Alex, could you commit that?

Jul 31 2018, 1:21 AM

May 16 2018

kito-cheng added a reviewer for D46850: [DebugInfo] Generate fixups as emitting DWARF .debug_line.: apazos.
May 16 2018, 7:55 PM

May 13 2018

kito-cheng added inline comments to D44888: [RISCV] Add -mrelax/-mno-relax flags to enable/disable RISCV linker relaxation.
May 13 2018, 8:16 PM

May 10 2018

kito-cheng added inline comments to D45773: [RISCV] Don't fold symbol diff.
May 10 2018, 8:31 PM
kito-cheng updated the diff for D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..

Changes:

  • Rebase.
  • Change fixup value of R_RISCV_RELAX to a constant 0 value for consistent with binutils's implementation.
May 10 2018, 2:01 AM
kito-cheng created D46677: [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates..
May 10 2018, 1:18 AM

May 8 2018

kito-cheng updated the diff for D45864: [RISCV] Support .option rvc and norvc.

Changes:

  • Add 2 test cases to show .option rvc and .option norvc in inline asm will not effect the code gen.
May 8 2018, 12:40 AM

May 1 2018

kito-cheng updated the diff for D45864: [RISCV] Support .option rvc and norvc.

Changes:

  • Add testcase for warning/failure cases.
May 1 2018, 8:22 PM

Apr 24 2018

kito-cheng updated the diff for D45864: [RISCV] Support .option rvc and norvc.

Changes:

  • Fix coding style issue.
  • Add more instructions to testcase.
  • Make emitDirectiveOptionRVC and emitDirectiveOptionNoRVC to pure virtual function.
  • Return nullptr rather than RISCVTargetStreamer in createRISCVObjectTargetStreamer, because we have pure virtual function in RISCVTargetStreamer now.
Apr 24 2018, 12:47 AM

Apr 19 2018

kito-cheng created D45864: [RISCV] Support .option rvc and norvc.
Apr 19 2018, 11:51 PM

Apr 12 2018

kito-cheng updated the diff for D45560: [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC.

Changes:

  • Add test case.
Apr 12 2018, 2:28 AM
kito-cheng created D45560: [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC.
Apr 12 2018, 2:04 AM

Apr 4 2018

kito-cheng added a comment to D45284: [RISCV] More validations on the input value of -march=.

Long time ago, GCC also accept upper case too, but I have no idea why Andrew change that? I guess one possible reason is because multi-lib?

Apr 4 2018, 9:12 PM
kito-cheng updated the diff for D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo.

Changes:

  • Reorder marco define into canonical order which specified in ISA manual.
  • Add missing test for marco.
Apr 4 2018, 8:11 AM
kito-cheng added a comment to D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo.

Hi Eli:

Apr 4 2018, 1:13 AM
kito-cheng updated the diff for D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo.

Changes:

  • Add testcase for TargetFeature: riscv, riscv32 and riscv64
Apr 4 2018, 1:13 AM

Mar 28 2018

kito-cheng updated the diff for D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo.

Changes:

  • Define riscv_atomic, riscv_flen, riscv_fdiv and riscv_fsqr, and add test for those marco.
  • Handle riscv, riscv32 and riscv64 in RISCVTargetInfo::hasFeature.
  • Fix several coding style issue.
  • Breaking the long lines in test case.
  • Add comment for RISCVTargetInfo::hasFeature.
Mar 28 2018, 12:11 AM

Mar 21 2018

kito-cheng added a comment to D44189: [RISCV] Verify the input value of -march=.

Hi Alex:

Mar 21 2018, 12:57 AM
kito-cheng updated the diff for D44189: [RISCV] Verify the input value of -march=.

Update revision according Alex's review.

Mar 21 2018, 12:55 AM

Mar 20 2018

kito-cheng created D44727: [RISCV] Extend getTargetDefines for RISCVTargetInfo.
Mar 20 2018, 10:29 PM

Mar 11 2018

kito-cheng updated the diff for D44189: [RISCV] Verify the input value of -march=.

Add test cases for the correct inputs.

Mar 11 2018, 8:15 PM

Mar 9 2018

kito-cheng updated the summary of D44189: [RISCV] Verify the input value of -march=.
Mar 9 2018, 12:53 AM

Mar 8 2018

kito-cheng updated the diff for D44189: [RISCV] Verify the input value of -march=.

This version only update variable name which changed in last version by accident.

Mar 8 2018, 6:50 PM

Mar 7 2018

kito-cheng added inline comments to D44189: [RISCV] Verify the input value of -march=.
Mar 7 2018, 11:40 PM
kito-cheng updated the diff for D44189: [RISCV] Verify the input value of -march=.
Mar 7 2018, 11:38 PM

Mar 6 2018

kito-cheng created D44189: [RISCV] Verify the input value of -march=.
Mar 6 2018, 10:25 PM

Feb 27 2018

kito-cheng accepted D43106: [RISCV] Force enable int128 for compiling long double routines.

LGTM, and I've tested this patch with https://reviews.llvm.org/D42958

Feb 27 2018, 9:39 PM

Feb 26 2018

kito-cheng added a comment to D43106: [RISCV] Force enable int128 for compiling long double routines.

So, do we want to enable this flag only based on a CMake macro like COMPILER_RT_HAS_FINT128_FLAG, or always add -fforce-enable-int128 to compiler-rt builds for RISCV32?

Feb 26 2018, 1:53 AM
kito-cheng updated the diff for D42958: [compiler-rt, RISCV] Support builtins for RISC-V.

Changes:

  • Add testcase.
  • Remove muldi3 support for RV64 in lib/builtins/riscv/mul3.S, because compiler-rt already provide a general version for muldi3.
  • Rename lib/builtins/riscv/mul3.S to lib/builtins/riscv/mulsi3.S for matching compiler-rt's naming convention.
Feb 26 2018, 1:47 AM

Feb 23 2018

kito-cheng added a comment to D43106: [RISCV] Force enable int128 for compiling long double routines.

Hi all:

Feb 23 2018, 12:03 AM

Feb 22 2018

kito-cheng added a comment to D42958: [compiler-rt, RISCV] Support builtins for RISC-V.

Hi Ana:

Feb 22 2018, 6:33 AM

Feb 20 2018

kito-cheng accepted D43146: [builtins] Fix c?zdi2 on sparc64/Linux and ignore riscv32.

LGTM for RISC-V part :)

Feb 20 2018, 5:49 PM