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Thu, Feb 13

andwar added inline comments to D74550: [AArch64][SVE] Add SVE index intrinsic.
Thu, Feb 13, 9:56 AM · Restricted Project
andwar added a comment to D74254: [llvm][aarch64] SVE addressing modes..

IMHO every test functions (e.g.:test_masked_ldst_sv2i8 ) should either test contiguous load or store (i.e. only one thing at a time). That will help triaging potential bugs in the future and also would be consistent with other test files in this folder.

I see your point, but the tests that use merge and store at the same time are using exactly the same addressing modes, it is not that they are using something different. So if something fails in the addressing mode of the load, it fails in the addressing mode of the store. Having them merged together saves quite some typing, and has no disadvantages in term of unit testing.

Thu, Feb 13, 4:34 AM · Restricted Project

Wed, Feb 12

andwar added a comment to D74254: [llvm][aarch64] SVE addressing modes..

Hi @fpetrogalli, thank you for working on this.

Wed, Feb 12, 6:32 AM · Restricted Project

Tue, Feb 11

andwar added inline comments to D73602: [SVE] Add support for lowering GEPs involving scalable vectors..
Tue, Feb 11, 9:30 AM · Restricted Project

Tue, Jan 28

andwar added a comment to D73286: [llvm][VectorUtils] Tweak VFShape for scalable vector functions..

One [nit] (non-blocking), otherwise LGTM.

Tue, Jan 28, 2:05 AM · Restricted Project

Mon, Jan 27

andwar added a comment to D73286: [llvm][VectorUtils] Tweak VFShape for scalable vector functions..

A few nits. Also, in the commit msg:

Mon, Jan 27, 10:00 AM · Restricted Project

Sat, Jan 25

andwar added a comment to D72798: [llvm][docs] LangRef for IR attribute `vector-function-abi-variant`..

LGTM

Sat, Jan 25, 4:20 AM · Restricted Project

Mon, Jan 20

andwar committed rG7e717b399055: [AArch64][SVE] Extend int_aarch64_sve_ld1_gather_imm (authored by andwar).
[AArch64][SVE] Extend int_aarch64_sve_ld1_gather_imm
Mon, Jan 20, 4:26 AM
andwar closed D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
Mon, Jan 20, 4:26 AM · Restricted Project
andwar added inline comments to D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
Mon, Jan 20, 1:49 AM · Restricted Project
andwar added inline comments to D72798: [llvm][docs] LangRef for IR attribute `vector-function-abi-variant`..
Mon, Jan 20, 1:31 AM · Restricted Project

Jan 17 2020

andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

Revert previous patch and settle on llvm.aarch64.sve.ld1.gather.scalar.offset

Jan 17 2020, 4:25 AM · Restricted Project
andwar added inline comments to D72798: [llvm][docs] LangRef for IR attribute `vector-function-abi-variant`..
Jan 17 2020, 2:10 AM · Restricted Project
andwar added inline comments to D72798: [llvm][docs] LangRef for IR attribute `vector-function-abi-variant`..
Jan 17 2020, 2:06 AM · Restricted Project

Jan 16 2020

andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

Fix the scaling of the offset

Jan 16 2020, 10:03 AM · Restricted Project
andwar added a comment to D72798: [llvm][docs] LangRef for IR attribute `vector-function-abi-variant`..

@fpetrogalli Thank you for working on this - just a few nits from me!

Jan 16 2020, 6:10 AM · Restricted Project
andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
  • Fix the offset limit in GLD1_IMM and SST1_IMM (now it depends on the size of the underylying datatype)
  • Update the tests accordingly
Jan 16 2020, 3:13 AM · Restricted Project

Jan 15 2020

andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

Similarly to gather loads, I've updated intrinisics for scatter stores ("vector base, scalar offset").

Jan 15 2020, 10:59 AM · Restricted Project
andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
  • Handled casses when the immediate offset is out of range (add relevant tests too)
  • Tweaked comments to better reflect the distinction that the ACLE makes ("scalar base, vector offsets" vs "vector base, scalar offset")
  • Updated commit msg
Jan 15 2020, 5:24 AM · Restricted Project

Jan 14 2020

andwar updated the diff for D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
  • Reverted changes from the previous patch
  • Renamed int_aarch64_sve_ld1_gather_imm to int_aarch64_sve_ld1_gather_scalar_offset
  • Renamed sve-intrinsics-gather-loads-vector-base.ll as sve-intrinsics-gather-loads-vector-base-imm-offset.ll
  • Added DAG combine rule for GLD1_IMM for scenarios where the offset is a non-immediate scalar
  • Added sve-intrinsics-gather-loads-vector-base-scalar-offset.ll test file
Jan 14 2020, 11:42 AM · Restricted Project

Jan 3 2020

andwar added a comment to D70590: [Examples] Add add_llvm_example_library macro and use it for IR example..

@fhahn Since https://reviews.llvm.org/D61446 has finally landed, what about revisiting the idea of using that instead? Just a thought.

Jan 3 2020, 1:03 PM · Restricted Project

Jan 2 2020

andwar added inline comments to D71698: [AArch64][SVE] Add intrinsic for non-faulting loads.
Jan 2 2020, 6:29 AM · Restricted Project
andwar committed rG404da13e1e94: [AArch64][SVE] Gather loads: pass 32 bit unpacked offsets as nxv2i32 (authored by andwar).
[AArch64][SVE] Gather loads: pass 32 bit unpacked offsets as nxv2i32
Jan 2 2020, 5:05 AM
andwar closed D71724: [AArch64][SVE] Gather loads: pass 32 bit unpacked offsets as nxv2i32.
Jan 2 2020, 5:04 AM · Restricted Project
andwar updated subscribers of D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.

Thank you for taking a look @eli.friedman. I've kept int_aarch64_sve_ld1_gather and int_aarch64_sve_ld1_gather_imm separate to better reflect the difference in the semantics of the corresponding instructions. I think that merging the two would obfuscate that separation a bit (though reduce code, which is usually a good thing). Keeping it as is would be my preference, but I might be missing the bigger picture?

Jan 2 2020, 3:02 AM · Restricted Project

Dec 20 2019

andwar created D71773: [AArch64][SVE] Update the definition of AdvSIMD_GatherLoad_VecTorBase_Intrinsic.
Dec 20 2019, 8:39 AM · Restricted Project
andwar committed rGbe2b7ea89ab4: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic (authored by andwar).
[AArch64][SVE] Add intrnisics for saturating scalar arithmetic
Dec 20 2019, 3:14 AM
andwar closed D71252: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic.
Dec 20 2019, 3:14 AM · Restricted Project
andwar committed rG88a973cf688e: [AArch64][SVE] Add intrinsics for binary narrowing operations (authored by andwar).
[AArch64][SVE] Add intrinsics for binary narrowing operations
Dec 20 2019, 2:21 AM
andwar closed D71552: [AArch64][SVE2] Add intrinsics for binary narrowing operations.
Dec 20 2019, 2:21 AM · Restricted Project

Dec 19 2019

andwar created D71724: [AArch64][SVE] Gather loads: pass 32 bit unpacked offsets as nxv2i32.
Dec 19 2019, 1:03 PM · Restricted Project
andwar updated the diff for D71252: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic.
  • Add patterns for scenarios when a 64bit value is requested from an intrinsic returning a 32 bit value (so that unecessary sxtw is avoided)
  • Add test cases for the above
  • Split tests into 4 seperate files (one per instruction)
  • Add missing ImmArg
  • Rebase on top of master
Dec 19 2019, 10:42 AM · Restricted Project
andwar added inline comments to D71252: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic.
Dec 19 2019, 10:42 AM · Restricted Project

Dec 17 2019

andwar updated the diff for D71552: [AArch64][SVE2] Add intrinsics for binary narrowing operations.
  • Add missing ImmArg
  • Add TImmLeaf-based equivalents for vecshiftR8, vecshiftR16 and vecshiftR32
  • Add missing s in the tests (that was an accidental typo)
Dec 17 2019, 2:23 AM · Restricted Project

Dec 16 2019

andwar created D71552: [AArch64][SVE2] Add intrinsics for binary narrowing operations.
Dec 16 2019, 8:34 AM · Restricted Project
andwar committed rGc41d2b5ab282: [AArch64][SVE2] Add intrinsics for binary narrowing operations (authored by andwar).
[AArch64][SVE2] Add intrinsics for binary narrowing operations
Dec 16 2019, 4:29 AM
andwar closed D71424: [AArch64][SVE2] Add intrinsics for binary narrowing operations.
Dec 16 2019, 4:28 AM · Restricted Project
andwar committed rG7e20c3a71d5f: [Aarch64][SVE] Add intrinsics for scatter stores (authored by andwar).
[Aarch64][SVE] Add intrinsics for scatter stores
Dec 16 2019, 3:54 AM
andwar closed D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 16 2019, 3:54 AM · Restricted Project

Dec 13 2019

andwar updated subscribers of D71252: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic.

Cheers for taking a look @eli.friedman !

Dec 13 2019, 9:38 AM · Restricted Project
andwar updated the diff for D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
  • add ImmArg in the defintion of AdvSIMD_ScatterStore_VectorBase_Intrinsic
  • duplicated imm0_31, uimm5s2, uimm5s4, uimm5s8 with TImmLeaf-based equivalents (required after adding ImmArg above)
  • rebased on top of trun
  • removed a whitespace
Dec 13 2019, 8:51 AM · Restricted Project
andwar updated subscribers of D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 13 2019, 8:51 AM · Restricted Project

Dec 12 2019

andwar created D71424: [AArch64][SVE2] Add intrinsics for binary narrowing operations.
Dec 12 2019, 9:09 AM · Restricted Project
andwar updated the diff for D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
  • Make sure that 32 bit unpacked offsets are passed as nxv2i32 (instead of nxv2i64)
  • Removed NFCs (landed in a seperate patch)
  • Refactored performST1ScatterCombine (better variable names)
Dec 12 2019, 6:52 AM · Restricted Project
andwar added inline comments to D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 12 2019, 6:42 AM · Restricted Project

Dec 11 2019

andwar committed rGa75463c47172: Add intrinsics for unary narrowing operations (authored by andwar).
Add intrinsics for unary narrowing operations
Dec 11 2019, 11:01 AM
andwar closed D71270: [AArch64][SVE2] Add intrinsics for unary narrowing operations.
Dec 11 2019, 11:00 AM · Restricted Project
andwar committed rG65651f197a2c: [AArch64][SVE] Add DAG combine rules for gather loads and sext/zext (authored by andwar).
[AArch64][SVE] Add DAG combine rules for gather loads and sext/zext
Dec 11 2019, 5:05 AM
andwar closed D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
Dec 11 2019, 5:04 AM · Restricted Project
andwar committed rG1eecbda08728: [AArch64][SVE] Move TableGen class definitions for gather loads (NFC) (authored by andwar).
[AArch64][SVE] Move TableGen class definitions for gather loads (NFC)
Dec 11 2019, 1:52 AM

Dec 10 2019

andwar created D71270: [AArch64][SVE2] Add intrinsics for unary narrowing operations.
Dec 10 2019, 6:56 AM · Restricted Project
andwar created D71252: [AArch64][SVE] Add intrnisics for saturating scalar arithmetic.
Dec 10 2019, 4:39 AM · Restricted Project

Dec 9 2019

andwar removed a parent revision for D71074: [Aarch64][SVE] Add intrinsics for scatter stores: D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
Dec 9 2019, 6:13 AM · Restricted Project
andwar removed a child revision for D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext: D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 9 2019, 6:13 AM · Restricted Project
andwar updated the diff for D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
  • make sure performST1ScatterCombine bails out for unpacked floats
  • remove MergeValues
  • rebase on top of master
Dec 9 2019, 6:13 AM · Restricted Project
andwar updated subscribers of D71074: [Aarch64][SVE] Add intrinsics for scatter stores.

Thank you for taking a look @eli.friedman!

Dec 9 2019, 5:35 AM · Restricted Project
andwar accepted D71146: [llvm][VFABI] Add more testing for LLVM internal mangling..

LGTM

Dec 9 2019, 1:17 AM · Restricted Project

Dec 5 2019

andwar added a reviewer for D71074: [Aarch64][SVE] Add intrinsics for scatter stores: sdesmalen.
Dec 5 2019, 10:24 AM · Restricted Project
andwar added a parent revision for D71074: [Aarch64][SVE] Add intrinsics for scatter stores: D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
Dec 5 2019, 10:24 AM · Restricted Project
andwar added a child revision for D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext: D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 5 2019, 10:24 AM · Restricted Project
andwar created D71074: [Aarch64][SVE] Add intrinsics for scatter stores.
Dec 5 2019, 10:24 AM · Restricted Project
andwar updated the diff for D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.

Remove a typo after rebase (uimm5s2 vs uim5s4)

Dec 5 2019, 9:14 AM · Restricted Project
andwar updated the diff for D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
  • Apply suggestions from @sdesmalen (e.g. add !Src.hasOneUse() in performANDCombine)
  • Removed a bunch of setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::nxv2i64, Legal), which are not needed for this patch
  • Simplified performSignExtendInRegCombine
  • Added patterns for sext_inreg (required for the new tests vvvv)
  • Added tests that verify that the new DAG Combine rules are not used when the result of gather load has multiple uses
Dec 5 2019, 3:43 AM · Restricted Project

Dec 2 2019

andwar updated the diff for D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm).
  • Reverted one incorrect (introduced by mistake) change in a TableGen pattern ( uimm5s2 vs uimm5s4)
  • Created a TableGen class for the intrinsics introduced here - for consistency with the other patches for gather loads
Dec 2 2019, 8:05 AM · Restricted Project

Nov 29 2019

andwar updated the diff for D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.

Added some NFCs before merging in:

Nov 29 2019, 2:20 AM · Restricted Project

Nov 28 2019

andwar added a comment to D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.

Thank you for reviewing @sdesmalen , updated accordingly.

Nov 28 2019, 7:04 AM · Restricted Project
andwar updated the diff for D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 28 2019, 6:57 AM · Restricted Project
andwar added inline comments to D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 28 2019, 6:57 AM · Restricted Project
andwar created D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext.
Nov 28 2019, 4:05 AM · Restricted Project
andwar added inline comments to D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm).
Nov 28 2019, 2:53 AM · Restricted Project
andwar added a child revision for D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets: D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm).
Nov 28 2019, 2:08 AM · Restricted Project
andwar added a parent revision for D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm): D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 28 2019, 2:08 AM · Restricted Project
andwar created D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm).
Nov 28 2019, 2:07 AM · Restricted Project

Nov 27 2019

andwar added a child revision for D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets: D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 27 2019, 9:32 AM · Restricted Project
andwar added a parent revision for D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets: D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.
Nov 27 2019, 9:32 AM · Restricted Project
andwar added a comment to D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.

Sorry for the builedbot failure. It can be ignored as this patch depends on https://reviews.llvm.org/D70542. It hasn't been merged-in yet and hence the patch doesn't apply cleanly.

Nov 27 2019, 9:31 AM · Restricted Project
andwar updated the summary of D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 27 2019, 7:22 AM · Restricted Project
andwar updated the summary of D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 27 2019, 7:22 AM · Restricted Project
andwar created D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets.
Nov 27 2019, 7:13 AM · Restricted Project

Nov 25 2019

andwar added inline comments to D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.
Nov 25 2019, 7:43 AM · Restricted Project
andwar updated the diff for D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.

I've uploaded new patch.

Nov 25 2019, 7:43 AM · Restricted Project

Nov 22 2019

andwar added inline comments to D70590: [Examples] Add add_llvm_example_library macro and use it for IR example..
Nov 22 2019, 4:07 AM · Restricted Project
andwar updated the diff for D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.

@sdesmalen Cheers for the quick review and your comments. I've updated the patch accordingly.

Nov 22 2019, 2:10 AM · Restricted Project
andwar added inline comments to D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.
Nov 22 2019, 2:05 AM · Restricted Project

Nov 21 2019

andwar added inline comments to D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.
Nov 21 2019, 8:10 AM · Restricted Project
andwar created D70542: [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsets.
Nov 21 2019, 8:01 AM · Restricted Project
andwar abandoned D67294: Register and parse a simplified version of '#pragma omp declare variant'.
Nov 21 2019, 1:07 AM · Restricted Project

Nov 14 2019

andwar added inline comments to D70107: [VFABI] TargetLibraryInfo mappings in IR..
Nov 14 2019, 4:10 AM · Restricted Project

Nov 12 2019

andwar added a comment to D70107: [VFABI] TargetLibraryInfo mappings in IR..

IIUC, this a transformation pass (it does modify the module, e.g. by appendToCompilerUsed(*M, {Global});). So you probably want to register it with one of the optimisation pipelines. I _believe_ that that's how you do it:

Nov 12 2019, 4:04 AM · Restricted Project

Nov 7 2019

andwar added a comment to D69416: [Examples] Add IRTransformations directory to examples..

Thanks for addressing my comments!

Nov 7 2019, 1:45 AM · Restricted Project

Nov 4 2019

andwar added a comment to D69416: [Examples] Add IRTransformations directory to examples..

This is great stuff, thank you for doing this!

Nov 4 2019, 1:00 PM · Restricted Project

Oct 31 2019

andwar added a comment to D69416: [Examples] Add IRTransformations directory to examples..

Includes are missing in SimplifyCFG.h:

cmake -G Ninja -DLLVM_TARGETS_TO_BUILD=X86 -DCMAKE_BUILD_TYPE=Release   -DLLVM_USE_NEWPM=On -DLLVM_BUILD_EXAMPLES=On ../../llvm/
(...)
ninja opt
(...)
/work/llvm-project/llvm/examples/IRTransforms/SimplifyCFG.h:15:1: error: unknown type name 'FunctionPass'
FunctionPass *createSimplifyCFGPass();
^
/work/llvm-project/llvm/examples/IRTransforms/SimplifyCFG.h:17:40: error: unknown type name 'PassRegistry'
void initializeSimplifyCFGLegacyPMPass(PassRegistry &);
                                       ^
Oct 31 2019, 10:29 AM · Restricted Project

Oct 26 2019

andwar added a comment to D69416: [Examples] Add IRTransformations directory to examples..

I think that having a reference to these examples somewhere in the official docs would be very helpful. Maybe somewhere here: http://llvm.org/docs/WritingAnLLVMPass.html?

Oct 26 2019, 11:38 AM · Restricted Project

Sep 21 2019

andwar added inline comments to D61446: Generalize the pass registration mechanism used by Polly to any third-party tool.
Sep 21 2019, 2:30 PM · Restricted Project, Restricted Project

Sep 11 2019

andwar added inline comments to D67294: Register and parse a simplified version of '#pragma omp declare variant'.
Sep 11 2019, 7:49 AM · Restricted Project
andwar added a comment to D67294: Register and parse a simplified version of '#pragma omp declare variant'.

I've addressed most of the comments except for those related to templates. I'd like to clarify as what is the expected behaviour there before proceeding with implementation.

Sep 11 2019, 2:19 AM · Restricted Project
andwar updated the diff for D67294: Register and parse a simplified version of '#pragma omp declare variant'.
  • Removed declare variant from Attr.td
  • Moved the 'vector-var-id' lookup from ParseOpenMP.cpp to SemaOpenMP.cpp
  • Parsing 'vector-var-id' as an expression
  • Removed the creation of the attribute in ActOnOpenMPDeclareVariantDirective
Sep 11 2019, 2:15 AM · Restricted Project

Sep 6 2019

andwar created D67294: Register and parse a simplified version of '#pragma omp declare variant'.
Sep 6 2019, 11:04 AM · Restricted Project