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Oct 20 2022
Oct 18 2022
Re-generate machine-combiner-mir.ll test checks
We have to revert it because tests were not correctly updated by 'update_mir_test_checks.py' script. Fix in D136170. I'll regenerate tests and update the review soon.
Rebase to fetch precommitted tests
Oct 14 2022
Rebase after D135776
Oct 13 2022
Addressed review comments
Thanks for the review.
@dmgreen, could you please submit the patch on my behalf? Author: Anton Sidorenko <anton.sidorenko@syntacore.com>
Oct 12 2022
A gentle ping.
Oct 11 2022
Move FRM operands creation from setSpecialOperandAttr to finalizeInsInstrs
Make flags intersection for new instructions, add Nsz flag check.
Oct 10 2022
Small code refactoring and tests update (change 'fast' flag to 'reassoc')
Oct 7 2022
Oct 6 2022
Addressed review comments
Oct 5 2022
Rebase to fetch merged dependency
This patch does not contain the full test to make changes more readable during the review.
Thanks for the review.
@frasercrmck, could you please submit the patch on my behalf? Author: Anton Sidorenko <anton.sidorenko@syntacore.com>
Oct 4 2022
Addressed review comments
Oct 3 2022
Apply VL shrinking only when SEW/LMUL ratio is unmodified. This change depends on D135086
Sep 28 2022
Sep 26 2022
Addressed review comments except for a few which have questions from my side.
Sep 22 2022
Sep 21 2022
Rebase
Sep 20 2022
@arcbbb, could you please submit the patch on my behalf? Author: Anton Sidorenko <anton.sidorenko@syntacore.com>
Thanks.
Sep 19 2022
Depends on D134179
Addressed review comments
Sep 16 2022
Sep 15 2022
In D130895#3787035, @reames wrote:I've looked at a few ideas in this area, and there's an interaction I want to point out that I don't have a good answer for.
While reducing the VL of a splat to match the demanded lanes can remove vsetv toggles, it can also add them. Specifically, if the splat happens to be scheduled in a region which uses the original wider VL, then reducing the VL actually pessimizes the code. This actually shows up in mixed VL code, particularly when combined with LICM for splats which can't be folded (profitably) into their users.
We can patch part of this by extending InsertVSETVLI to allow increasing VL on splats if the splat is TA. However, there's still a scheduling interaction here which is a bit hard to account for.
I generally do believe that having VL reduction for all computation (not just splats) is generally a good idea; I'm just trying to figure out how to slice the pieces so that we can get there incrementally without nasty regressions along the way.
Sep 13 2022
A gentle ping
Sep 6 2022
Make VL choosing for a splat-like VMV based on its users
Aug 12 2022
A gentle ping on the question about adding a markup of merge operands for intrinsics.
Aug 2 2022
In D130895#3691031, @craig.topper wrote:What if the user is the merge operand of a tail undisturbed instruction. The VL of the using instruction would not apply to it then.