Apr 13 2021
Apr 12 2021
Apr 9 2021
Apr 7 2021
Can we have testcases which check what happens with
I feel like this would be a bit easier to get in if it was broken into 1 patch per combine?
The original code was confusing. Rewrote this to use getICmpTrueVal + APInt. I think this simplifies the behaviour for s1 quite a bit.
Apr 6 2021
- Change KB check to an assert
- Handle vectors
- Add a vector test in AMDGPU (which has ZeroOrOneBooleanContent for vectors)
Apr 5 2021
From someone who isn't very familiar with this code: Why do we need the preference flag in the first place? As indirectbr isn't particularly common, can't we check whether the result is a BlockAddress after the fact?
Apr 2 2021
Apr 1 2021
Mar 30 2021
Mar 29 2021
Mar 25 2021
Add verifier tests (and actually copy the memoperand from the memset)
Mar 24 2021
I made this AArch64-specific for now.
LGTM. Kind of weird that we create normal IMPLICIT_DEFs in the IRTranslator though? I guess it's code shared with SDAG.
There are a bunch of rotate combines in the DAGCombiner, so it would make sense to have a generic G_ROR and G_ROL. Looks like some low-hanging fruit.
Mar 23 2021
Add legalizer tests
I'm wondering if we should just allow regular G_ADD to use pointer types, and reserve G_PTR_ADD for non-integral address spaces.
Mar 22 2021
Would it be hard to teach CSEMIRBuilder to handle the missing cases so that you can match top-down from the G_SELECT? It would be nice to avoid maintaining a list of constant-foldable opcodes if possible.
I think if the errors on Windows and Linux are gone, it's fine to recommit.
(Should we have tests for these?)
Mar 19 2021
Mar 18 2021
Mar 17 2021
Mar 15 2021
Mar 12 2021
I think something like this would work post-legalization:
If we have to allow variable width operands for these, it doesn't really help AArch64 that much. We have to match the constant pattern to a target specific opcode, and then lower the rest of these to shifts by default. I can see the benefit of AMDGPU, but with variable extracts this just puts us back where we started for AArch64.
- Make the LSB + width registers
- Update verifier
- Add a MIRBuilder test
Mar 11 2021
Mar 8 2021
This LGTM at this point?
Move DL out of the if and reuse it.
Address review comments.
Mar 5 2021
Mar 4 2021
This time, disallow 0 and 1 specifically.
Mar 3 2021
Looks like this blocks selecting vector neg since we miss some imported patterns. E.g.
Mar 2 2021
- Fix a bug in G_DUP for preISelLower and add a testcase which exercises it to select-dup.mir
- Add getAArch64VectorConstantSplat, which checks for G_DUP as well as G_BUILD_VECTOR. Use that instead in places which now need to check for G_DUP.
Mar 1 2021
Feb 26 2021
Feb 25 2021
Feb 24 2021
I think this looks reasonable. LGTM