Page MenuHomePhabricator
Feed Advanced Search

Dec 6 2017

gadi.haber added a comment to D40879: [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC>.

I can combine them to a single file.
The reason for the separation is to improve the ability to track the coverage.
Note that there is also the PPRO ISA set.

Dec 6 2017, 12:19 AM

Dec 5 2017

gadi.haber created D40880: [X86][FMA][FMA4]: Adding full coverage of MC encoding for the FMA, FMA4 isa sets.<NFC>.
Dec 5 2017, 11:42 PM
gadi.haber created D40879: [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC>.
Dec 5 2017, 11:23 PM

Dec 3 2017

gadi.haber created D40776: [X86][AVX512]: Adding full coverage of MC encoding for the AVX512 isa sets (w/o AVX512F).<NFC>.
Dec 3 2017, 9:22 AM · Restricted Project, Restricted Project

Dec 1 2017

gadi.haber retitled D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC> from [X86][AVX2]: Adding full coverage of MC encoding for the AVX2 isa set.<NFC> to [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX2 isa set.<NFC>.
Dec 1 2017, 11:05 AM
gadi.haber updated the diff for D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>.
  1. Added AVX tests for 32 and 64 bits.
  2. Updated AVX2 64 bit tests to include xmm15 test in addition to xmm6 tests
Dec 1 2017, 11:05 AM

Nov 30 2017

gadi.haber added a comment to D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

ping

Nov 30 2017, 3:18 AM

Nov 29 2017

gadi.haber updated the diff for D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Removed duplicates per Simon's comment

Nov 29 2017, 1:53 AM
gadi.haber retitled D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC> from [X86]: Adding full coverage of MC encoding for all X86 ISA Sets.<NFC> to [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.
Nov 29 2017, 1:39 AM

Nov 27 2017

gadi.haber updated the diff for D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

following Simon's comment to add the retl scheduling information.

Nov 27 2017, 2:26 AM

Nov 26 2017

gadi.haber added a comment to D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

Good point.
From the tables I have, I could not find any scheduling difference between retl and retq they are both mapped to:
XED_IFORM_RET_NEAR
latency = 2 cycles + 5 cycles load latency.
3 uOps
ports: 23, 0156, 6

Nov 26 2017, 11:38 PM
gadi.haber accepted D40351: [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class.
Nov 26 2017, 11:19 PM
gadi.haber added inline comments to D40351: [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class.
Nov 26 2017, 6:31 AM
gadi.haber updated the diff for D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>.

AVX2-32.s : Removed redundant # signs from AVX2-32.s
AVX2-64.s: Duplicated the tests to use XMM8 and YMM9

Nov 26 2017, 6:23 AM

Nov 25 2017

gadi.haber added a comment to D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>.

Ah, You mean the XMM registers.

Nov 25 2017, 10:33 PM

Nov 23 2017

gadi.haber created D40387: [X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>.
Nov 23 2017, 4:00 AM · Restricted Project
gadi.haber added a comment to D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>.

You mean that each instruction should cover all registers?
I did a quick check and it produces a huge number of tests that exceed 200k including AVX512.
I, therefore, chose to use only representatives.

Nov 23 2017, 12:18 AM

Nov 22 2017

gadi.haber added a reviewer for D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>: m_zuckerman.
Nov 22 2017, 5:18 AM
gadi.haber retitled D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC> from [X86]: Adding full coverage of MC encoding for all X86 ISA Sets.NFC to [X86]: Adding full coverage of MC encoding for all X86 ISA Sets.<NFC>.
Nov 22 2017, 5:16 AM
gadi.haber added a reviewer for D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>: m_zuckerman.
Nov 22 2017, 5:15 AM

Nov 21 2017

gadi.haber updated the summary of D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.
Nov 21 2017, 3:25 AM
gadi.haber created D40287: [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>.
Nov 21 2017, 1:31 AM

Nov 20 2017

gadi.haber updated the diff for D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

sorted the instructions per Zvi's comment

Nov 20 2017, 4:35 AM

Nov 16 2017

gadi.haber updated the diff for D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

Removed old scheduling for the GATHER instructions which has overridden the new ones.
Fixed the overall load latency attribute for HSW from 4 cycles to 5.

Nov 16 2017, 5:23 AM
gadi.haber added a comment to D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

good catch, The old scheduling has overridden the new one in the td file. I will update the diff file

Nov 16 2017, 4:32 AM

Nov 15 2017

gadi.haber accepted D39899: [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class.
Nov 15 2017, 6:04 AM
gadi.haber added a comment to D39899: [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class.

Ah you're right. For SNB this is fine.
My comment was for HSW. Sorry.

Nov 15 2017, 5:35 AM
gadi.haber added a comment to D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

Unfortunately, I cannot give you the exact numbers.
Overall, on ~900 benchmarks the performance speedup gain of new scheduling is ~6%.

Nov 15 2017, 5:13 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Simon, splitting the instructions based on the CPUID bit is referred actually according to "CPU extension".
There are a total of 62 extensions.
I can do it according to extensions. The only problem with that is that it will complicate the generation of the tests.

Nov 15 2017, 3:40 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

I updated the list of ISA Sets.
I think we can consdier removing the REAL and the Protected ISA right?

Nov 15 2017, 3:34 AM
gadi.haber updated the summary of D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.
Nov 15 2017, 3:31 AM
gadi.haber added a comment to D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..

Performance runs are done on 3 main benchmarks: SPEC CPU 2017, Geekbench4, EEMBC suite of automotive, denbench, coremark-pro, networking, telecom.

Nov 15 2017, 1:53 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Please ignore my previous comment. These instructions are not used by the compiler Ring 1.
I will remove them from the ISA Set.

Nov 15 2017, 1:46 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

The BBX* ISA Sets are new AVX512 instrs. Here are some examples below (<format: #iclass, extension, category, iform, isa_set>:
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_XMMu32_MASKmskw_MEMu32_BBX, BBX2_128
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_XMMu32_MASKmskw_XMMu32_BBX, BBX2_128
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_YMMu32_MASKmskw_MEMu32_BBX, BBX2_256
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_YMMu32_MASKmskw_YMMu32_BBX, BBX2_256
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_ZMMu32_MASKmskw_MEMu32_BBX, BBX2_512
VPSLCTLASTD, AVX512EVEX, BBX2, VPSLCTLASTD_ZMMu32_MASKmskw_ZMMu32_BBX, BBX2_512
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_XMMu64_MASKmskw_MEMu64_BBX, BBX2_128
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_XMMu64_MASKmskw_XMMu64_BBX, BBX2_128
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_YMMu64_MASKmskw_MEMu64_BBX, BBX2_256
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_YMMu64_MASKmskw_YMMu64_BBX, BBX2_256
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_ZMMu64_MASKmskw_MEMu64_BBX, BBX2_512
VPSLCTLASTQ, AVX512EVEX, BBX2, VPSLCTLASTQ_ZMMu64_MASKmskw_ZMMu64_BBX, BBX2_512

Nov 15 2017, 1:33 AM

Nov 14 2017

gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Ok. The CLZERO instruction is going to be part of AMD ISA Set. It is very recent and part of of the Rizen CPU.

Nov 14 2017, 11:36 PM
gadi.haber created D40021: [X86][Haswell]: Updating the scheduling information for the Haswell subtarget..
Nov 14 2017, 4:23 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Do you mean the following LWP instructions that belong to the XOP ISA set?:
LLWPCB LLWPCB_GPRvqq
LWPINS LWPINS_GPRyqq_GPRvd_IMMd
LWPINS LWPINS_GPRyqq_MEMd_IMMd
LWPVAL LWPVAL_GPRyqq_GPRvd_IMMd
LWPVAL LWPVAL_GPRyqq_MEMd_IMMd
SLWPCB SLWPCB_GPRvqq

Nov 14 2017, 1:07 AM

Nov 13 2017

gadi.haber retitled D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC> from [X86]: Adding full coverage of MC encoding for all X86 ISA Sets to [X86]: Adding full coverage of MC encoding for all X86 ISA Sets.NFC.
Nov 13 2017, 11:24 PM
gadi.haber added a comment to D39899: [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class.

yes. SLM is good enough

Nov 13 2017, 6:12 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Sorry. Here is a more readbale table of I486 + I486REAL:

Nov 13 2017, 6:06 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

I486 will include encoding + asm of the following instrs:

Nov 13 2017, 5:51 AM
gadi.haber added a comment to D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.

Unfortunately, I am using an internal DB with python scripts.

Nov 13 2017, 5:09 AM
gadi.haber created D39952: [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>.
Nov 13 2017, 1:37 AM
gadi.haber committed rL318024: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..
[X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.
Nov 13 2017, 12:44 AM
gadi.haber closed D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes. by committing rL318024: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..
Nov 13 2017, 12:43 AM
gadi.haber closed D37799: [X86][Skylake] Replacing -mcpu=skx by -mattr in a codegen test. NFC..
Nov 13 2017, 12:43 AM
gadi.haber updated the diff for D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..

Updated diff after rebase

Nov 13 2017, 12:39 AM
gadi.haber retitled D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes. from [X86][SKX] Replace scheduling info of intrinsic SKX opcodes by the non-intrinsic opcodes. to [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..
Nov 13 2017, 12:36 AM
gadi.haber updated the summary of D37799: [X86][Skylake] Replacing -mcpu=skx by -mattr in a codegen test. NFC..
Nov 13 2017, 12:32 AM
gadi.haber added a comment to D39899: [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class.

Note that WriteALU means 1 cycle latency using Port 0156

Nov 13 2017, 12:25 AM

Nov 12 2017

gadi.haber added inline comments to D39840: [MC][X86] Code padding for performance stability - Branch instructions and targets alignment.
Nov 12 2017, 11:58 PM
gadi.haber updated the diff for D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..

Updated diff file after adding the following instructions to the SKX scheduling file:
(V)MAXCPD/MAXCPS/MAXCSD/MAXCSS/MINCPD/MINCPS/MINCSD/MINCSS

Nov 12 2017, 3:47 AM
gadi.haber updated the diff for D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..

Updated diff following Craig's comment.

Nov 12 2017, 12:59 AM

Nov 9 2017

gadi.haber created D39833: [X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes..
Nov 9 2017, 1:14 AM

Oct 31 2017

gadi.haber accepted D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.
Oct 31 2017, 3:13 AM

Oct 30 2017

gadi.haber added inline comments to D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.
Oct 30 2017, 5:31 AM
gadi.haber added a reviewer for D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool: gadi.haber.
Oct 30 2017, 5:09 AM

Oct 24 2017

gadi.haber committed rL316492: [X86][Broadwell] Added the instruction scheduling information for the Broadwell….
[X86][Broadwell] Added the instruction scheduling information for the Broadwell…
Oct 24 2017, 1:20 PM
gadi.haber closed D39054: [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU. by committing rL316492: [X86][Broadwell] Added the instruction scheduling information for the Broadwell….
Oct 24 2017, 1:20 PM

Oct 22 2017

gadi.haber added inline comments to D39134: [X86][SSE] Add MOVHPSrm to domain tables.
Oct 22 2017, 2:31 AM

Oct 21 2017

gadi.haber added inline comments to D39054: [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU..
Oct 21 2017, 11:11 PM

Oct 18 2017

gadi.haber updated the summary of D39054: [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU..
Oct 18 2017, 7:56 AM
gadi.haber created D39054: [X86][Broadwell] Added the instruction scheduling information for the Broadwell CPU..
Oct 18 2017, 7:08 AM
gadi.haber accepted D34393: [MC] Adding code padding for performance stability - infrastructure. NFC..
Oct 18 2017, 12:41 AM

Oct 17 2017

gadi.haber committed rL315998: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests..
[X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.
Oct 17 2017, 6:46 AM
gadi.haber closed D38994: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC> by committing rL315998: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests..
Oct 17 2017, 6:46 AM
gadi.haber committed rL315985: [X86][Skylake] fixed/updated regression test mmx-schedule.ll which failed after….
[X86][Skylake] fixed/updated regression test mmx-schedule.ll which failed after…
Oct 17 2017, 3:00 AM
gadi.haber updated the summary of D38994: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC>.
Oct 17 2017, 2:27 AM
gadi.haber added a reviewer for D38994: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC>: aaboud.
Oct 17 2017, 2:18 AM
gadi.haber created D38994: [X86][Broadwell] Added the broadwell cpu to the scheduling regression tests.<NFC>.
Oct 17 2017, 2:13 AM

Oct 16 2017

gadi.haber committed rL315978: [X86][SKL] Updated scheduling information for the SkylakeClient target.
[X86][SKL] Updated scheduling information for the SkylakeClient target
Oct 16 2017, 11:47 PM
gadi.haber closed D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target by committing rL315978: [X86][SKL] Updated scheduling information for the SkylakeClient target.
Oct 16 2017, 11:47 PM
gadi.haber added a comment to D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target.

This modified version of the SkylakeClient schedulings does indeed show gains on SKL without apparent regressions when compared to the existing SKL schedulings.
Thus, we are motivated to continue with the process of updating all X86 target schedulings.
Next step, once this patch is committed, is to submit the Broadwell schedulings for review.

Oct 16 2017, 2:43 AM

Oct 15 2017

gadi.haber accepted D38890: [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and Knights Landing CPUs..
Oct 15 2017, 7:23 AM
gadi.haber added inline comments to D34393: [MC] Adding code padding for performance stability - infrastructure. NFC..
Oct 15 2017, 7:04 AM
gadi.haber added a reviewer for D34393: [MC] Adding code padding for performance stability - infrastructure. NFC.: gadi.haber.
Oct 15 2017, 6:53 AM
gadi.haber added a comment to D38890: [X86] Add FeatureSlowBTMem to Haswell, Broadwell, Skylake, Cannonlake, and Knights Landing CPUs..

Yes. The X86 Bit Test is known to run slowly on all X86 CPUs.

Oct 15 2017, 4:52 AM

Oct 11 2017

gadi.haber added a comment to D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target.

The .td file is actually generated by a script and if you notice it already contains some (not many) regular expressions when possible,
For the SKX scheduling, for example, there are many regular expressions that include the broadcast, mask and zeroing bits for all relevant AVX512 instructions.
The problem is that there are not many opportunities to group instructions into regular expressions.
For example, the MMX_* is spread between groups 1, 2,3,8,9,12, etc.
The differences between the groups could be in any of the latency, number of uOps or the ports used by the uOPs.
This makes it hard to use regular expressions.

Oct 11 2017, 4:57 AM
gadi.haber added inline comments to D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target.
Oct 11 2017, 2:29 AM
gadi.haber updated the diff for D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target.

Updated diff following Simon's comment to remove the COMMON check prefix from the bmi2 scheduling test.

Oct 11 2017, 2:26 AM

Oct 10 2017

gadi.haber created D38727: [X86][SKL] Updated scheduling information for the SkylakeClient target.
Oct 10 2017, 6:34 AM
gadi.haber committed rL315291: [X86][SKYLAKE] Update regression test to differentiate between HASWELL and….
[X86][SKYLAKE] Update regression test to differentiate between HASWELL and…
Oct 10 2017, 2:53 AM
gadi.haber closed D38685: [X86][SKYLAKE] Update regression test to differentiate between HASWELL and SKYLAKE scheduling.<NFC> by committing rL315291: [X86][SKYLAKE] Update regression test to differentiate between HASWELL and….
Oct 10 2017, 2:53 AM

Oct 9 2017

gadi.haber created D38685: [X86][SKYLAKE] Update regression test to differentiate between HASWELL and SKYLAKE scheduling.<NFC> .
Oct 9 2017, 4:35 AM

Oct 8 2017

gadi.haber committed rL315175: [X86][SKX] Adding the scheduling information for the SKX target..
[X86][SKX] Adding the scheduling information for the SKX target.
Oct 8 2017, 5:55 AM
gadi.haber closed D38443: [X86][SKX] Adding the scheduling information for the SKX target. by committing rL315175: [X86][SKX] Adding the scheduling information for the SKX target..
Oct 8 2017, 5:54 AM
gadi.haber updated the diff for D38443: [X86][SKX] Adding the scheduling information for the SKX target..

Updated diff file after rebase,

Oct 8 2017, 1:09 AM

Oct 4 2017

gadi.haber added a comment to D38443: [X86][SKX] Adding the scheduling information for the SKX target..

Ping :-)

Oct 4 2017, 3:17 AM

Oct 1 2017

gadi.haber added a comment to D38443: [X86][SKX] Adding the scheduling information for the SKX target..

Good point. We had multiple rounds of checks and it seems that indeed some (not all) of the memory instructions do need to include additional latency based on whether they are load of an address or data, load of 128 or 256 or 512 bits vector, load and store and store alone.
I intend to go back and fix it for the Skylake Client and for Haswell.

Oct 1 2017, 9:17 AM
gadi.haber updated the summary of D38443: [X86][SKX] Adding the scheduling information for the SKX target..
Oct 1 2017, 3:16 AM
gadi.haber created D38443: [X86][SKX] Adding the scheduling information for the SKX target..
Oct 1 2017, 3:15 AM

Sep 30 2017

gadi.haber committed rL314594: [X86][SKX] Added codegen regression test for avx512 instructions scheduling.NFC..
[X86][SKX] Added codegen regression test for avx512 instructions scheduling.NFC.
Sep 30 2017, 7:32 AM
gadi.haber closed D38035: [X86][SKX] Added codegen regression test for avx512 instructions scheduling.NFC. by committing rL314594: [X86][SKX] Added codegen regression test for avx512 instructions scheduling.NFC..
Sep 30 2017, 7:32 AM

Sep 28 2017

gadi.haber updated the diff for D38035: [X86][SKX] Added codegen regression test for avx512 instructions scheduling.NFC..

Had to replace all test files with new ones as they were using the avx512 intrinsics which are now in the process of being replaced by IR.
As a result I created 2 new tests which were compiled from the following regression tests:

Sep 28 2017, 3:07 AM

Sep 27 2017

gadi.haber committed rL314306: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag..
[X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.
Sep 27 2017, 7:46 AM
gadi.haber closed D38222: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC. by committing rL314306: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag..
Sep 27 2017, 7:46 AM
gadi.haber added a reviewer for D38222: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC.: RKSimon.
Sep 27 2017, 4:13 AM

Sep 25 2017

gadi.haber updated the diff for D38222: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC..

Updated diff after running update_llc_test_checks on the 8 tests and re-applying the changes to get rid of the "End of function" comments.

Sep 25 2017, 5:03 AM
gadi.haber updated the diff for D38222: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC..

Updated diff after a rebase.

Sep 25 2017, 5:03 AM
gadi.haber created D38222: [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC..
Sep 25 2017, 5:03 AM