Updated diff after adding -mattr=+avx512vpopcntdq to the test: avx512vpopcntdq-schedule-intrinsics.ll

Updated diff after splitting the avx512 scheduling test into the following test files:
avx512bw-schedule-intrinsics.ll
avx512bwvl-schedule-intrinsics.ll
avx512cd-schedule-intrinsics.ll
avx512cdvl-schedule-intrinsics.ll
avx512dq-schedule-intrinsics.ll
avx512dqvl-schedule-intrinsics.ll
avx512-schedule-fma-intrinsics.ll
avx512-schedule-gather-scatter-intrin.ll
avx512-schedule-intrinsics.ll
avx512vpopcntdq-schedule-intrinsics.ll

If you do not see standing issues, please accept the review so we can focus on SKylakeServer. Thanx!

Yes. Make sense. I will start with extending the avx512 scheduling test coverage.

Please note that apart from this scheduling patch we have only one more large patch left - the SkylakeServer schedulings, which I like to submit for review as soon as this one is committed.

corrected updated diff to use git diff HEAD^

good catch on the missing scheduling for gather instructions!

Updated diff after fixing scheduling information was missing from avx2-schedule.ll test due to a typo bug in the X86SchedSkylakeCleint.td

Updated diff after rebase codegen tests + added VGATHER schedulings.

Updated diff to include the --check-prefix=COMMON flag in the run commands.

Yes I'm working to add the GATHER instructions.

As an example here are the encodings coverage I have for the MULX32rm opcode:

In fact, my next task after committing the SKL + SKX scheduling is to extend the MC tests to include all encodings coverage of all the instructions starting SNB.
Not sure if ALL encoding variations with all register types 8,16,32,64 will be included but at the moment I was able to gather more than 10K encodings coverage for about 5K LLVM opcodes.

Updated after the following changes:

1. modifying 3 Codegen tests to use the -mattr flag instead of the -mcpu flags.
2. removing remaining AVX512 instructions for mask registers manipulations in X86SchedSkylake.td
3. Changed the load latency from 4 cycles in HSW to 5 cycles.
4. Better regrouping some of the instructions in X86SchedSkylake.td

generated new diff with all changes.

Added the following comment to pr32329.ll:
"According to https://bugs.llvm.org/show_bug.cgi?id=32329 it checks DAG ISEL failure on SKX target"

Updated diff after removing all AVX512 instructions

Good point. All AVX512 ISA is disabled in SKL. Will update the diff file.

Updated diff following comments by Craig. Brought back BSWAP(16|32) + fixed ports for the MUL and IMUL 16 and 32.

Updated diff file after comments by Craig Topper about differences in MUL and IMUL instructions for 8 vs. 16 vs 32 vs 64 bits.

Unfortunately, splitting the patch creates an even worse case of unstable scheduling which produces regressions.
I am working on fine tuning the existing scheduling - which I hope to put on review soon.

Updated diff after comments by Craig. Found missing some of the IMUL instrs + added the rr_REV instructions.

Ignore my last comment.
I was able to retrieve the information for IMUL(16|32|64)rri8 and IMUL(16|32|64)rmi8
I will add them in.

Unfortunately, I could not retrieve the data about the mentioned IMUL instructions from the HSW architects.
I hope to dig into the archives together with the architects and search for all missing instructions in the next commits for both SNB, HSW and the next SKX and SKL patches.

I see. Code alignment in X86 is indeed an issue.
There are currently two pending reviews for patches that start providing a fix for the code alignment issue in X86.
The reviews are in a pending state for quite some time now.
Maybe we can give them higher priority and get them in?

20% is high. Try to verify if this is not code alignment related.

Yes, This is correct.

ping.

2nd updated diff with cleaner diff on gather_address.ll test following comments by Zvi Rackover.

Updated diff following comments by zvi.

Updated diff after adding back a comment related to test_floatret function.

Updated diff file after fixing comments provided by Simon.

Dear Chandler.

Following Chandler's comments I am reverting the commit to address the issues reported in the modified tests.

rebase with latest LLVM version fro June 27 2017

ping

Updated diff to include recent changes made to X86 schedule .td files for horizontal add/sub instructions

Updated diff following fixes made to 3 LITs under Codegen X86.