Mar 18 2019
V2: Like the previous commit, no longer supports a method for LLPC to
call to write the PAL metadata into IR metadata. The plan now is that LLPC will use MsgPackDocument and put the msgpack binary blob into IR metadata itself.
V2: Removed AMDGPUPALMetadata API used directly by LLPC. The plan now is
that LLPC will continue to put the PAL metadata binary blob into IR metadata itself.
Mar 17 2019
Mar 16 2019
V5: Added vec3 to AMDGPUCallingConvention.td. Fixed call-return-types test for dwordx3 buffer/flat.
(I will add vec5 to AMDGPUCallingConvention.td in the vec5 change.)
V5: Added vec3/vec5 non-shader arg and ret type test cases, including passing by stack.
V4: Properly addressed review comment.
V3: Adjusted the MIR roundtrip fix to use scoping instead of explicit flush.
Mar 15 2019
V2: Also fix the same bug in Matt's AMDGPU MIR roundtrip commit.
Mar 14 2019
Mar 13 2019
V4: Added vec3/vec5 shader arg test cases.
V4: Fixed vec3 in sign_extend test.
V3: Addressed review comment.
Mar 12 2019
V2: Addressed review comment: Commented extra clamp bit operands.
Mar 11 2019
The answer I have got from the HW team is that you can use abs and neg modifiers on f32 data in v_cndmask_b32, v_mov_b32 and v_movrel*_b32.
V3: Added multi-dword vgpr spill test, inc vec3 and vec5.
It seems to me that this could use a test-case that fails without this fix.
V3: Fixed new cost tests so they work with and without legal v3/v5
types. Added v5i64/v5f64 kernarg test cases as suggested by Matt.
I'll double check.
Mar 10 2019
Mar 8 2019
Mar 6 2019
V3: Addressed review comment by widening illegal odd vectors in a
V2: Fixed missing part of change, including defaulting v5 operations to
expand. Fixed broken v5f32 select. Fixed reg class priorities.
Fixed spilling and asm constraints, and added sgpr spill test.
Actually I only have a vec3 spilling test for sgprs. I didn't see any multi-dword vgpr spill tests.
V2: Fixed broken v3f32 select.
Fixed reg class priorities. Updated a fragile test. Addressed review comments on DL::getIdxType. Fixed vec3 sgpr inline asm constraint. Added vec3 sgpr spill test.
Needs a test for the 96-bit spills. An -O0 test case with a value live across a block should work
Mar 5 2019
What about flat and segmented memory operations?
V2: Addressed Stas's review comment about empty block.
Mar 4 2019
V2: Moved ARM and AMDGPU changes out to their own commits.