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Fri, Oct 23

vpykhtin committed rG00255f419298: [AMDGPU] Fix access beyond the end of the basic block in… (authored by vpykhtin).
[AMDGPU] Fix access beyond the end of the basic block in…
Fri, Oct 23, 9:20 AM
vpykhtin closed D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..
Fri, Oct 23, 9:19 AM · Restricted Project

Thu, Oct 22

vpykhtin added inline comments to D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..
Thu, Oct 22, 9:55 AM · Restricted Project
vpykhtin added a comment to D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Jay, Matt do you have objections with this patch?

Thu, Oct 22, 9:25 AM · Restricted Project

Wed, Oct 21

vpykhtin updated the diff for D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Fixed formatting issue

Wed, Oct 21, 1:41 AM · Restricted Project

Tue, Oct 20

vpykhtin updated the diff for D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Fixed formattind and lint issues.

Tue, Oct 20, 10:30 AM · Restricted Project

Mon, Oct 19

vpykhtin updated the diff for D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Added test, more review issues fixed.

Mon, Oct 19, 9:33 AM · Restricted Project

Fri, Oct 16

vpykhtin added a comment to D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Actually do we have a test with a call in between def and use?

Probably not, how a call looks like at this stage?

It should be s_setpc_b64 at this point and it is a terminator and branch. Although I am not sure it can be detected as an EXEC change.

Fri, Oct 16, 1:25 AM · Restricted Project

Wed, Oct 14

vpykhtin added a comment to D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Actually do we have a test with a call in between def and use?

Wed, Oct 14, 10:21 PM · Restricted Project
vpykhtin added inline comments to D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..
Wed, Oct 14, 9:32 AM · Restricted Project
vpykhtin updated the diff for D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..

Per review fixes.

Wed, Oct 14, 9:30 AM · Restricted Project
vpykhtin requested review of D89386: [AMDGPU] Fix access beyond the end of the basic block in execMayBeModifiedBeforeAnyUse..
Wed, Oct 14, 5:00 AM · Restricted Project

Sun, Oct 11

vpykhtin added a comment to D64393: [AMDGPU] Fix DPP combiner check for exec modification.

I've found the case when execMayBeModifiedBeforeAnyUse randomly leads to a coredump, which is hard to debug. Most likely it's because an instruction beyond the end of a basic block is accessed. This means that the first loop calculates some instructions twice and I was wrong assuming use_nodbg_instructions doesn't repeat them. In fact there is no code in MachineRegisterInfo::verifyUseList that ensures that uses belonging to one instruction should be sequent in the use list nor the traces of such ordering can be found in MachineRegisterInfo::addRegOperandToUseList. I'm going to fix this code.

Sun, Oct 11, 6:16 PM · Restricted Project

Sep 24 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

If that piece of code turns out to be mandatory, we'll find out soon enough and we would get a test case :).

Sep 24 2020, 7:38 AM · Restricted Project
vpykhtin committed rGd9beff04a308: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining (authored by vpykhtin).
[RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining
Sep 24 2020, 7:36 AM
vpykhtin closed D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.
Sep 24 2020, 7:35 AM · Restricted Project

Sep 23 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

Sorry, I had to explain the context around the modified code.

Sep 23 2020, 4:52 AM · Restricted Project

Sep 22 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

HI Quentin,

Sep 22 2020, 4:26 AM · Restricted Project

Sep 7 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

ping

Sep 7 2020, 7:09 PM · Restricted Project

Aug 31 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

Honestly, I have no idea one way or another. I'm leaning toward @arsenm's theory that the implicit def may be needed in case the full register is never fully covered.
But I would need to dig deeper into this.

Aug 31 2020, 4:09 AM · Restricted Project
vpykhtin updated the diff for D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

Rebased, updated per review comments.

Aug 31 2020, 3:48 AM · Restricted Project
vpykhtin updated the summary of D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.
Aug 31 2020, 3:20 AM · Restricted Project

Aug 20 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

Can you remove the commit message from the previous commit from this message? I found it confusing to read it here

Aug 20 2020, 3:11 AM · Restricted Project

Aug 18 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

ping

Aug 18 2020, 7:12 AM · Restricted Project

Jul 23 2020

vpykhtin accepted D84026: [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier.

Ok, let's keep it simple, no much benefit with maps. LGTM.

Jul 23 2020, 10:35 PM · Restricted Project
vpykhtin added a comment to D84026: [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier.

Overally looks good

Jul 23 2020, 2:52 AM · Restricted Project

Jul 15 2020

vpykhtin added a comment to D83825: AMDGPU: Rename add/sub with carry out instructions.

I have no objections but I'll ask Dmirty to check this from asm/dasm side.

Jul 15 2020, 8:04 AM · Restricted Project

Jul 14 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

It would help if 9d7bc0874cf20f44cd331c77f5a003b4c4b262bd had a test...

I'm somewhat suspicious, since I have seen cases where the implicit def is needed in cases where the full register is never fully covered. However, it's possible this is still a leftover from before DetectDeadLanes was added

Jul 14 2020, 10:28 PM · Restricted Project

Jul 10 2020

vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

ping

Jul 10 2020, 8:44 AM · Restricted Project

Jul 7 2020

vpykhtin accepted D82916: LIS: fix handleMove to properly extend main range.

Given than the condition here is rare, I'm ok with the patch, reworking undef handling in scheduler is a massive work.

Jul 7 2020, 9:36 AM · Restricted Project
vpykhtin added a comment to D82916: LIS: fix handleMove to properly extend main range.

I understood your patch. Generally I think patching LIS with cleared undef flags ins't right at first place because the semantic of register lifetime is ruined. After the first move there should be an undef flag set at the %1.sub2 = IMPLICIT_DEF instruction which would break lives of all subregs live at this point. Can we drop updating LIS during scheduling and recreate it from scratch? Or may be fully recreate only the intervals for the registers involved in moves when the undef flag is patched after scheduling?

Jul 7 2020, 9:15 AM · Restricted Project
vpykhtin added a comment to D82916: LIS: fix handleMove to properly extend main range.

Can you please add a LiveInterval dump (possibly truncated) for the test before and after each move to this review? It's a bit hard to follow what happens there.

Jul 7 2020, 5:07 AM · Restricted Project

Jul 3 2020

vpykhtin committed rGbb69ca822aae: [AMDGPU] Don't combine DPP if DPP register is used more than once per… (authored by vpykhtin).
[AMDGPU] Don't combine DPP if DPP register is used more than once per…
Jul 3 2020, 5:22 AM
vpykhtin closed D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jul 3 2020, 5:21 AM · Restricted Project

Jul 2 2020

vpykhtin updated the diff for D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.

Update before commit: used isIdenticalTo, rebased.

Jul 2 2020, 4:47 AM · Restricted Project
vpykhtin added a comment to D82580: [RegisterCoalescer] Dumper for JoinVals.

Ping

Jul 2 2020, 4:15 AM · Restricted Project
vpykhtin added a comment to D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.

Ping

Jul 2 2020, 4:15 AM · Restricted Project

Jun 26 2020

vpykhtin added inline comments to D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jun 26 2020, 3:45 AM · Restricted Project
vpykhtin updated the diff for D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.

Rebased, added check if use is Src0 or Src1

Jun 26 2020, 3:13 AM · Restricted Project
vpykhtin added inline comments to D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jun 26 2020, 2:40 AM · Restricted Project
vpykhtin updated the diff for D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.

Indeed, thanks Jay, updated.

Jun 26 2020, 2:08 AM · Restricted Project
vpykhtin updated the summary of D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.
Jun 26 2020, 1:36 AM · Restricted Project

Jun 25 2020

vpykhtin updated the diff for D82580: [RegisterCoalescer] Dumper for JoinVals.

Rebased, per review issues fixed, moved VNInfo::print definition ot of class.

Jun 25 2020, 10:53 PM · Restricted Project
vpykhtin updated the summary of D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 10:53 PM · Restricted Project
vpykhtin added inline comments to D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 12:28 PM · Restricted Project
vpykhtin added inline comments to D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 11:54 AM · Restricted Project
vpykhtin added inline comments to D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jun 25 2020, 10:46 AM · Restricted Project
vpykhtin updated the summary of D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 10:46 AM · Restricted Project
vpykhtin updated the summary of D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 10:46 AM · Restricted Project
vpykhtin created D82580: [RegisterCoalescer] Dumper for JoinVals.
Jun 25 2020, 10:46 AM · Restricted Project
vpykhtin added inline comments to D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jun 25 2020, 10:13 AM · Restricted Project
vpykhtin abandoned D82451: [AMDGPU] Fix DPP Combiner:.

split to parts

Jun 25 2020, 8:00 AM · Restricted Project
vpykhtin created D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction.
Jun 25 2020, 8:00 AM · Restricted Project
vpykhtin added a comment to D82451: [AMDGPU] Fix DPP Combiner:.
  1. skip multiple per instruction DPP register usage.
  2. don't combine when DPP register is used as part of superreg/supersubreg.

I had to refactor the code to fix the first issue,

Would it make sense to split this patch into two or three? Refactoring, fix bug 1, fix bug 2?

Jun 25 2020, 4:42 AM · Restricted Project
vpykhtin updated the diff for D82451: [AMDGPU] Fix DPP Combiner:.

Rebased, per review issues fixed:

Jun 25 2020, 4:09 AM · Restricted Project

Jun 24 2020

vpykhtin added inline comments to D82451: [AMDGPU] Fix DPP Combiner:.
Jun 24 2020, 8:36 AM · Restricted Project
vpykhtin created D82451: [AMDGPU] Fix DPP Combiner:.
Jun 24 2020, 4:49 AM · Restricted Project

Jun 20 2020

vpykhtin created D82258: [RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining.
Jun 20 2020, 7:23 AM · Restricted Project

Jun 9 2020

vpykhtin updated the diff for D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection.

Updated patch. Everything is done except I decided to left readsM0 check for the no-ret atomics case.

Jun 9 2020, 7:39 AM · Restricted Project
vpykhtin added inline comments to D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection.
Jun 9 2020, 7:39 AM · Restricted Project

Jun 6 2020

vpykhtin added a comment to D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection.

The SI_INIT_M0 is still used for instructions that I mention in hasNonDefaultM0. Comments say it was introduced to produce S_MOV_B32 m0 so the CSE could join them.

Jun 6 2020, 1:34 AM · Restricted Project

Jun 5 2020

vpykhtin created D81275: [AMDGPU] Move default initialization of M0 register after the instruction selection.
Jun 5 2020, 10:01 AM · Restricted Project

May 29 2020

vpykhtin accepted D80754: AMDGPU/GlobalISel: cmp/select method for insert element.

LGTM

May 29 2020, 7:01 AM · Restricted Project
vpykhtin accepted D80767: GlobalISel: fix CombinerHelper::matchEqualDefs().

LGTM

May 29 2020, 7:01 AM · Restricted Project

May 26 2020

vpykhtin committed rG92f3828dc567: [AMDGPU] Fix wait counts in the presence of 16bit subregisters (authored by vpykhtin).
[AMDGPU] Fix wait counts in the presence of 16bit subregisters
May 26 2020, 2:40 AM
vpykhtin closed D80033: [AMDGPU] Fix wait counts in the presence of 16bit subregisters.
May 26 2020, 2:40 AM · Restricted Project

May 15 2020

vpykhtin created D80033: [AMDGPU] Fix wait counts in the presence of 16bit subregisters.
May 15 2020, 2:09 PM · Restricted Project
vpykhtin added a reviewer for D80033: [AMDGPU] Fix wait counts in the presence of 16bit subregisters: foad.
May 15 2020, 2:09 PM · Restricted Project

May 6 2020

vpykhtin added a reviewer for D79435: [AMDGPU] Drop 16 bit subreg suffixes on print: dp.
May 6 2020, 2:07 AM · Restricted Project
vpykhtin accepted D79435: [AMDGPU] Drop 16 bit subreg suffixes on print.

LGTM.

May 6 2020, 2:07 AM · Restricted Project

May 5 2020

vpykhtin accepted D79362: [AMDGPU] Fix FoldImmediate for 16 bit operand.

LGTM.

May 5 2020, 2:06 AM · Restricted Project

Apr 27 2020

vpykhtin added a reviewer for D78597: [AMDGPU] Define AGPR subregs: dp.
Apr 27 2020, 3:42 AM · Restricted Project

Mar 20 2020

vpykhtin accepted D76371: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64.

LGTM.

Mar 20 2020, 1:03 AM · Restricted Project

Mar 17 2020

vpykhtin accepted D76230: [AMDGPU] Enable SEXT divergence driven selection..

LGTM, assuming Matt's concern is addressed.

Mar 17 2020, 6:52 AM · Restricted Project

Mar 4 2020

vpykhtin accepted D75472: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to separate basic block.

I cannot follow all the consequences of adding the landing pad, but this looks a robust solution since it's hard to find appropriate insertion point for s_or_saveexec instruction in the beginning of SI_ELSE constaining block.

Mar 4 2020, 6:11 AM · Restricted Project

Feb 27 2020

GitHub <noreply@github.com> committed rG061a0fdd36ff: Merge pull request #35 from RadeonOpenCompute/LowerKernelCalls (authored by vpykhtin).
Merge pull request #35 from RadeonOpenCompute/LowerKernelCalls
Feb 27 2020, 3:35 AM

Feb 18 2020

vpykhtin accepted D74649: [TBLGEN] Emit register pressure set enum.

LGTM.

Feb 18 2020, 5:55 AM · Restricted Project

Jan 27 2020

vpykhtin accepted D73386: [AMDGPU] Attempt to reschedule withou clustering.

LGTM, Thanks.

Jan 27 2020, 10:20 AM · Restricted Project
vpykhtin added a comment to D73386: [AMDGPU] Attempt to reschedule withou clustering.

LGTM.

Jan 27 2020, 9:13 AM · Restricted Project
vpykhtin accepted D73417: [AMDGPU] Add file headers for few files where it is missing..

LGTM, thanks.

Jan 27 2020, 8:55 AM · Restricted Project
vpykhtin committed rG4332f1a4c826: [AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions. (authored by vpykhtin).
[AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions.
Jan 27 2020, 6:34 AM
vpykhtin closed D73338: [AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions.
Jan 27 2020, 6:34 AM · Restricted Project

Jan 24 2020

vpykhtin accepted D73292: [AMDGPU] Correct NumLoads in clustering.

LGTM.

Jan 24 2020, 6:31 AM · Restricted Project
vpykhtin created D73338: [AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions.
Jan 24 2020, 2:42 AM · Restricted Project

Jan 21 2020

vpykhtin accepted D72737: [AMDGPU] Bundle loads before post-RA scheduler.

LGTM

Jan 21 2020, 9:13 AM · Restricted Project

Dec 12 2019

vpykhtin accepted D71132: PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand.

LGTM.

Dec 12 2019, 9:09 AM · Restricted Project
vpykhtin added a comment to D71132: PostRA Machine Sink should take care of COPY defining register that is a sub-register by another COPY source operand.

Almost LGTM. Do you need those liveins reorderings?

Dec 12 2019, 8:04 AM · Restricted Project

Dec 6 2019

vpykhtin added a comment to D71089: [AMDGPU] Optimizing unnecessary copies for REG_SEQUENCE PHI operand. Also fixes rocBLAS error.

Looks good, but the test would be nice to have.

Dec 6 2019, 8:12 AM · Restricted Project

Nov 26 2019

vpykhtin committed rG008e65a7bfb3: [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer… (authored by vpykhtin).
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer…
Nov 26 2019, 8:07 AM
vpykhtin closed D70405: [AMDGPU] Fix emitIfBreak CF lowering: use a temp register to make register coalescer life easier..
Nov 26 2019, 8:07 AM · Restricted Project

Nov 19 2019

vpykhtin accepted D70400: [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen.

LGTM.

Nov 19 2019, 8:34 AM · Restricted Project
vpykhtin added inline comments to D70405: [AMDGPU] Fix emitIfBreak CF lowering: use a temp register to make register coalescer life easier..
Nov 19 2019, 6:54 AM · Restricted Project
vpykhtin updated the diff for D70405: [AMDGPU] Fix emitIfBreak CF lowering: use a temp register to make register coalescer life easier..

updated the diff per comment. Used utils/update_llc_test_checks.py tool to update autogenerated test.

Nov 19 2019, 6:54 AM · Restricted Project

Nov 18 2019

vpykhtin updated the diff for D70405: [AMDGPU] Fix emitIfBreak CF lowering: use a temp register to make register coalescer life easier..

added test fix.

Nov 18 2019, 10:31 AM · Restricted Project
vpykhtin added inline comments to D70400: [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen.
Nov 18 2019, 10:05 AM · Restricted Project
vpykhtin created D70405: [AMDGPU] Fix emitIfBreak CF lowering: use a temp register to make register coalescer life easier..
Nov 18 2019, 9:38 AM · Restricted Project
vpykhtin accepted D70402: [AMDGPU][DPP] Corrected DPP combiner.

LGTM.

Nov 18 2019, 8:44 AM · Restricted Project
vpykhtin added a comment to D70400: [AMDGPU][GFX10] Disabled v_movrel*[sdwa|dpp] opcodes in codegen.

Look mostly good, but can you split this change into one that relates to DPP and another that disables asm only instructions?

Nov 18 2019, 8:18 AM · Restricted Project

Oct 25 2019

vpykhtin committed rGc9c18e5a3194: [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when… (authored by vpykhtin).
[AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when…
Oct 25 2019, 11:41 AM
vpykhtin closed D69430: Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required).
Oct 25 2019, 11:40 AM · Restricted Project