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Fri, Feb 14

ftynse added inline comments to rG39cb2a8fc799: [mlir] Fix argument attribute attribute reassignment in ConvertStandardToLLVM.
Fri, Feb 14, 4:06 AM
ftynse requested changes to D74584: [mlir] Refactor TypeConverter to add conversions without inheritance.

Could you also update https://mlir.llvm.org/docs/DialectConversion/#type-conversion ?

Fri, Feb 14, 2:21 AM · Restricted Project
ftynse added a comment to D74584: [mlir] Refactor TypeConverter to add conversions without inheritance.

Thanks River! I had prototyped a similar thing, but you've beaten me to it and added fancy templates :)

Fri, Feb 14, 2:21 AM · Restricted Project
ftynse accepted D74401: [MLIR] Add std.atomic_rmw op.

LGTM when extra documentation is added as discussed on Discourse.

Fri, Feb 14, 1:56 AM · Restricted Project
ftynse accepted D74532: [mlir] Linalg: Extend promotion to non f32 buffers..

I wonder how much of the test here is just carried over mechanically and if we could do something to reduce this churn...

Fri, Feb 14, 1:45 AM · Restricted Project
ftynse added a reviewer for D74592: Do not build the CUBIN conversion pass when NVPTX Backend isn't configured: herhut.
Fri, Feb 14, 1:36 AM · Restricted Project
ftynse committed rG39cb2a8fc799: [mlir] Fix argument attribute attribute reassignment in ConvertStandardToLLVM (authored by ftynse).
[mlir] Fix argument attribute attribute reassignment in ConvertStandardToLLVM
Fri, Feb 14, 1:27 AM
ftynse added a comment to D74211: [mlir] use unpacked memref descriptors at function boundaries.

Should be fixed by 39cb2a8fc79976171b20369ff756f7fa43232b50.

Fri, Feb 14, 1:26 AM · Restricted Project

Thu, Feb 13

ftynse updated subscribers of D74543: [MLIR][Affine] Mark affine.min and affine.max as NoSideffect..

Weird, AffineMinOp and AffineMaxOp do have the trait, they are just below (I asked @OuHangKresnik to add them in one of recent commits). Can we explore more what's the problem with loop.parallel not seing the trait?

Thu, Feb 13, 4:53 AM · Restricted Project
ftynse committed rG2e8c112ecf56: [mlir] Add elementAttr to TypedArrayAttrBase. (authored by abeakkas).
[mlir] Add elementAttr to TypedArrayAttrBase.
Thu, Feb 13, 12:32 AM
ftynse closed D73579: [mlir] Add elementAttr to TypedArrayAttrBase..
Thu, Feb 13, 12:32 AM · Restricted Project
ftynse committed rG005b720373f1: [NFC][mlir] Adding some helpful EDSC intrinsics (authored by kernhanda).
[NFC][mlir] Adding some helpful EDSC intrinsics
Thu, Feb 13, 12:23 AM
ftynse closed D74119: [NFC][mlir] Adding some helpful EDSC intrinsics.
Thu, Feb 13, 12:23 AM · Restricted Project
ftynse added inline comments to D74466: [mlir] StdToLLVM: Add error when the sourceMemRef of a subview is not a llvm type..
Thu, Feb 13, 12:14 AM · Restricted Project

Wed, Feb 12

ftynse committed rG4f865b77941d: [mlir] support creating memref descriptors from static shape with non-zero… (authored by gysit).
[mlir] support creating memref descriptors from static shape with non-zero…
Wed, Feb 12, 1:47 PM
ftynse committed rG56aba9699d8d: [MLIR] Fix wrong header for mlir-cuda-runner (authored by clementval).
[MLIR] Fix wrong header for mlir-cuda-runner
Wed, Feb 12, 1:47 PM
ftynse closed D74474: [mlir] support creating memref descriptors from static shape with non-zero offset.
Wed, Feb 12, 1:47 PM · Restricted Project
ftynse closed D74497: [MLIR] Fix wrong header for mlir-cuda-runner.
Wed, Feb 12, 1:47 PM · Restricted Project
ftynse accepted D74474: [mlir] support creating memref descriptors from static shape with non-zero offset.

Thanks!

Wed, Feb 12, 1:37 PM · Restricted Project
ftynse accepted D74497: [MLIR] Fix wrong header for mlir-cuda-runner.

Thanks!

Wed, Feb 12, 12:15 PM · Restricted Project
ftynse accepted D73893: [MLIR][GPU] Implement initial mapping from loop.parallel to gpu.launch..

Looks okay for the first take at it.

Wed, Feb 12, 12:15 PM · Restricted Project
ftynse requested changes to D74474: [mlir] support creating memref descriptors from static shape with non-zero offset.

Can you add a tests where the non-zero offset is exercised?

Wed, Feb 12, 6:22 AM · Restricted Project
ftynse closed D74421: [mlir] Linalg fusion: ignore indexed_generic producers.

Landed 5ae9c4c86806811cab3735dd56237ec1a9614354

Wed, Feb 12, 6:22 AM · Restricted Project
ftynse committed rG5ae9c4c86806: [mlir] Linalg fusion: ignore indexed_generic producers (authored by ftynse).
[mlir] Linalg fusion: ignore indexed_generic producers
Wed, Feb 12, 6:14 AM
ftynse committed rGfd11cda2519f: [mlir] StdToLLVM: Add error when the sourceMemRef of a subview is not a llvm… (authored by poechsel).
[mlir] StdToLLVM: Add error when the sourceMemRef of a subview is not a llvm…
Wed, Feb 12, 6:14 AM
ftynse closed D74466: [mlir] StdToLLVM: Add error when the sourceMemRef of a subview is not a llvm type..
Wed, Feb 12, 6:14 AM · Restricted Project
ftynse updated the diff for D74421: [mlir] Linalg fusion: ignore indexed_generic producers.

Add test

Wed, Feb 12, 6:13 AM · Restricted Project
ftynse accepted D74480: [MLIR][CUDA] Fix build file for mlir-cuda-runner.
Wed, Feb 12, 5:54 AM · Restricted Project
ftynse added a comment to D74472: Fix MLIR build when the NVPTX target isn't configured.

It looks like similar changes may be needed to mlir-cuda-runner and, potentially, mlir-cpu-runner.

Wed, Feb 12, 5:36 AM · Restricted Project
ftynse added a comment to D74401: [MLIR] Add std.atomic_rmw op.

Great work! I only have some nits.

Wed, Feb 12, 4:14 AM · Restricted Project
ftynse accepted D74472: Fix MLIR build when the NVPTX target isn't configured.
Wed, Feb 12, 3:46 AM · Restricted Project
ftynse accepted D74466: [mlir] StdToLLVM: Add error when the sourceMemRef of a subview is not a llvm type..

Nit: please explain in the commit message that this was segfaulting before your change, and why it was. Or, as https://mlir.llvm.org/getting_started/DeveloperGuide/ states it, the commit message should explain _why_ you are making the change.

Wed, Feb 12, 1:02 AM · Restricted Project
ftynse accepted D74378: [MLIR] Add std.assume_align op..

My brain didn't wire up to the simple and new stuff.

Wed, Feb 12, 1:02 AM · Restricted Project
ftynse committed rGa9a305716bbf: [mlir] Revise naming of MLIROptMain and MLIRMlirOptLib (authored by marbre).
[mlir] Revise naming of MLIROptMain and MLIRMlirOptLib
Wed, Feb 12, 12:53 AM
ftynse closed D73778: [mlir] Revise naming of MLIROptMain and MLIRMlirOptLib.
Wed, Feb 12, 12:52 AM · Restricted Project

Tue, Feb 11

ftynse added a comment to D74174: [MLIR] Allow Loop dialect IfOp and ForOp to define values .

I am mostly nitpicking. Let's finish the design discussion on discourse and land this!

Tue, Feb 11, 12:06 PM · Restricted Project
ftynse created D74421: [mlir] Linalg fusion: ignore indexed_generic producers.
Tue, Feb 11, 9:54 AM · Restricted Project
ftynse requested changes to D74406: Add RsqrtOp to LLVM dialect..

I don't think this belongs to the LLVM dialect. LLVM IR does not have rsqrt as operation or intrinsics, so neither should the dialect. We can have it in a higher-level dialect that lowers to llvm.intr.sqrt (to introduce) and llvm.fdiv (already available). But this expansion should _not_ happen when converting from the LLVM dialect to LLVM IR, that mapping is intentionally kept trivial.

Tue, Feb 11, 7:14 AM · Restricted Project
ftynse committed rGea3a25e4f516: [mlir] StdToLLVM: add a separate test for the new memref calling convention (authored by ftynse).
[mlir] StdToLLVM: add a separate test for the new memref calling convention
Tue, Feb 11, 5:07 AM
ftynse added inline comments to D74211: [mlir] use unpacked memref descriptors at function boundaries.
Tue, Feb 11, 5:07 AM · Restricted Project
ftynse accepted D74389: [MLIR][GPU] Disallow llvm tanh intrinsics when lowering to NVVM/ROCm..

The granularity of exposing them is not clear to me. I also thought about an intrinsics/non-intrinsics split. But even the definition of what intrinsic based lowering means is vague. LLVM::ExpOp is an operation but ultimately lowered to some intrinsic.

Tue, Feb 11, 2:44 AM · Restricted Project
ftynse requested changes to D74378: [MLIR] Add std.assume_align op..

Thanks for pushing on this. Having alignment attribute as an ODS argument looks like it would remove a bunch of boilerplate for you.

Tue, Feb 11, 2:33 AM · Restricted Project
ftynse added a comment to D74389: [MLIR][GPU] Disallow llvm tanh intrinsics when lowering to NVVM/ROCm..

This would work for me. At scale, we may need to analyze effects of such approach on compile time. The converter essentially twice the number of patterns it has to search through, and there are potential rollbacks of rewrites that generated illegal operations.

Tue, Feb 11, 1:58 AM · Restricted Project

Mon, Feb 10

ftynse accepted D74363: [mlir] Allow constructing a ValueRange from an ArrayRef<BlockArgument>.

Thanks, River!

Mon, Feb 10, 11:36 PM · Restricted Project
ftynse accepted D73671: [MLIR][Standard] Add folding for indexCast(indexCast(x)) -> x.
Mon, Feb 10, 9:50 AM · Restricted Project
ftynse accepted D73672: [MLIR][Standard] Implement constant folding for IndexCast.
Mon, Feb 10, 9:50 AM · Restricted Project
ftynse accepted D74302: [mlir][EDSC] Almost NFC - Refactor and untangle EDSC dependencies.
Mon, Feb 10, 9:05 AM · Restricted Project
ftynse committed rG1555d7f72908: [mlir] subview op lowering for target memrefs with const offset (authored by gysit).
[mlir] subview op lowering for target memrefs with const offset
Mon, Feb 10, 8:38 AM
ftynse closed D74280: [mlir] subview op lowering for target memrefs with const offset.
Mon, Feb 10, 8:38 AM · Restricted Project
ftynse accepted D74171: [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect.
Mon, Feb 10, 8:29 AM · Restricted Project
ftynse accepted D74280: [mlir] subview op lowering for target memrefs with const offset.

Thanks, Tobias! Let me know if you need me to land this for you.

Mon, Feb 10, 8:06 AM · Restricted Project
ftynse added a comment to D74302: [mlir][EDSC] Almost NFC - Refactor and untangle EDSC dependencies.

Layering-wise, this makes sense to me. EDSC is a utility library, similar to IR, and should not depend on an ever-growing set of dialects, rather the inverse.

Mon, Feb 10, 8:01 AM · Restricted Project
ftynse requested changes to D74302: [mlir][EDSC] Almost NFC - Refactor and untangle EDSC dependencies.

cmake seems broken

Mon, Feb 10, 7:48 AM · Restricted Project
ftynse accepted D74307: [MLIR] Support memrefs with complex element types..
Mon, Feb 10, 7:30 AM · Restricted Project
ftynse closed D74211: [mlir] use unpacked memref descriptors at function boundaries.

Landed in https://github.com/llvm/llvm-project/commit/5a1778057f72b8e0444a7932144a3fa441b641bc

Mon, Feb 10, 6:23 AM · Restricted Project
ftynse committed rG5a1778057f72: [mlir] use unpacked memref descriptors at function boundaries (authored by ftynse).
[mlir] use unpacked memref descriptors at function boundaries
Mon, Feb 10, 6:05 AM
ftynse added inline comments to D74211: [mlir] use unpacked memref descriptors at function boundaries.
Mon, Feb 10, 5:38 AM · Restricted Project
ftynse updated the diff for D74211: [mlir] use unpacked memref descriptors at function boundaries.

Added example with unranked memref to the doc.
Added a helper view class.

Mon, Feb 10, 5:16 AM · Restricted Project

Fri, Feb 7

ftynse updated the diff for D74211: [mlir] use unpacked memref descriptors at function boundaries.

addressed most comments

Fri, Feb 7, 2:07 PM · Restricted Project
ftynse added inline comments to D74211: [mlir] use unpacked memref descriptors at function boundaries.
Fri, Feb 7, 2:07 PM · Restricted Project
ftynse added inline comments to D74171: [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect.
Fri, Feb 7, 1:39 PM · Restricted Project
ftynse added inline comments to D74171: [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect.
Fri, Feb 7, 11:21 AM · Restricted Project
ftynse accepted D74171: [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect.
Fri, Feb 7, 11:12 AM · Restricted Project
ftynse committed rG7edf27f7a75a: [mlir] Add NoSideEffect to Affine min max (authored by OuHangKresnik).
[mlir] Add NoSideEffect to Affine min max
Fri, Feb 7, 6:21 AM
ftynse closed D74203: Add NoSideEffect to Affine min max.
Fri, Feb 7, 6:21 AM · Restricted Project
ftynse added a comment to D73893: [MLIR][GPU] Implement initial mapping from loop.parallel to gpu.launch..

I'm missing some higher-level documentation on what each function is supposed to do.

Fri, Feb 7, 5:53 AM · Restricted Project
ftynse added inline comments to D73893: [MLIR][GPU] Implement initial mapping from loop.parallel to gpu.launch..
Fri, Feb 7, 5:36 AM · Restricted Project
ftynse accepted D74179: [mlir][VectorOps] Generalized vector.print to i32/i64.
Fri, Feb 7, 5:00 AM · Restricted Project
ftynse requested changes to D74171: [mlir] [LLVMIR] add all vector reduction intrinsics to LLVM IR dialect.
Fri, Feb 7, 4:42 AM · Restricted Project
ftynse accepted D74203: Add NoSideEffect to Affine min max.

Thanks!

Fri, Feb 7, 4:34 AM · Restricted Project
ftynse created D74211: [mlir] use unpacked memref descriptors at function boundaries.
Fri, Feb 7, 3:41 AM · Restricted Project

Thu, Feb 6

ftynse accepted D74119: [NFC][mlir] Adding some helpful EDSC intrinsics.
Thu, Feb 6, 2:27 PM · Restricted Project
ftynse accepted D73671: [MLIR][Standard] Add folding for indexCast(indexCast(x)) -> x.
Thu, Feb 6, 5:50 AM · Restricted Project
ftynse added inline comments to D74119: [NFC][mlir] Adding some helpful EDSC intrinsics.
Thu, Feb 6, 5:41 AM · Restricted Project
ftynse committed rG5c3b34930c31: [mlir] Add AffineMaxOp (authored by OuHangKresnik).
[mlir] Add AffineMaxOp
Thu, Feb 6, 1:32 AM
ftynse closed D73848: Add AffineMaxOp.
Thu, Feb 6, 1:32 AM · Restricted Project

Wed, Feb 5

ftynse accepted D73848: Add AffineMaxOp.
Wed, Feb 5, 4:28 AM · Restricted Project

Tue, Feb 4

ftynse accepted D73934: [mlir] Add support for basic location translation to LLVM..

Thanks River, this is very useful!

Tue, Feb 4, 2:41 PM · Restricted Project
ftynse added a comment to D73848: Add AffineMaxOp.

Almost there, a couple more comments.

Tue, Feb 4, 1:26 AM · Restricted Project
ftynse accepted D73764: [mlir] Added RankedIntElementsAttr class.

LGTM after one nit is fixed.

Tue, Feb 4, 12:59 AM · Restricted Project

Mon, Feb 3

ftynse added a comment to D73893: [MLIR][GPU] Implement initial mapping from loop.parallel to gpu.launch..

I suppose you want high-level feedback on this, so I'm not nitpicking in the code.

Mon, Feb 3, 1:52 PM · Restricted Project
ftynse committed rG3b4d24d77014: [mlir] Accept an LLVM::LLVMFuncOp in the builder of LLVM::CallOp (authored by ftynse).
[mlir] Accept an LLVM::LLVMFuncOp in the builder of LLVM::CallOp
Mon, Feb 3, 1:33 PM
ftynse closed D73895: [mlir] Accept an LLVM::LLVMFuncOp in the builder of LLVM::CallOp.
Mon, Feb 3, 1:33 PM · Restricted Project
ftynse added inline comments to D73912: [mlir] Turn flags in ConvertStandardToLLVM into pass flags.
Mon, Feb 3, 1:24 PM · Restricted Project
ftynse added inline comments to D73848: Add AffineMaxOp.
Mon, Feb 3, 10:01 AM · Restricted Project
ftynse created D73895: [mlir] Accept an LLVM::LLVMFuncOp in the builder of LLVM::CallOp.
Mon, Feb 3, 8:10 AM · Restricted Project
ftynse committed rGe0ea706a59b9: [mlir] ConvertStandardToLLVM: do not rely on command line options internally (authored by ftynse).
[mlir] ConvertStandardToLLVM: do not rely on command line options internally
Mon, Feb 3, 4:52 AM
ftynse committed rGf3fa4a34b62e: [mlir] Drop customization hooks from StandardToLLVM conversion (authored by ftynse).
[mlir] Drop customization hooks from StandardToLLVM conversion
Mon, Feb 3, 4:28 AM
ftynse closed D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.
Mon, Feb 3, 4:28 AM · Restricted Project
ftynse updated the diff for D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.

Rebase

Mon, Feb 3, 4:28 AM · Restricted Project
ftynse added a comment to D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.

I'm wondering how it will be possible to extend the list of patterns for non-standard ops and still make use of the existing LLVMLoweringPass? I'm currently using the patternListFiller to add my own patterns to the pass. If the LLVMLoweringPass was exposed in a header, I could at least reuse that.

Mon, Feb 3, 4:24 AM · Restricted Project
ftynse added a comment to D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.

Just wondering how this will impact the LLVM lowering customization scalability problem in general. By removing the hook for patterns, won't we go from an explosion of populate* functions to an explosion of LLVM lowering passes?

Mon, Feb 3, 4:19 AM · Restricted Project
ftynse committed rG9adbb6c468c1: [mlir] Fix link to 'Getting started with MLIR' (authored by marbre).
[mlir] Fix link to 'Getting started with MLIR'
Mon, Feb 3, 4:05 AM
ftynse closed D73770: [mlir] Fix link to 'Getting started with MLIR'.
Mon, Feb 3, 4:05 AM · Restricted Project
ftynse requested changes to D73848: Add AffineMaxOp.

Thanks! I have a couple of comments inline. Major comments:

  • the lowering looks incorrect;
  • please call SomethingOp only the thing that is an actual Op in the IR, use OpBase or Base for common implementation details.
Mon, Feb 3, 2:08 AM · Restricted Project

Fri, Jan 31

ftynse accepted D72802: [mlir] Introduce bare ptr calling convention for MemRefs in LLVM dialect.

AFAIK, MLIR changes cannot affect libc++ tests so it's okay to land if those are the only problem.

Fri, Jan 31, 2:53 PM · Restricted Project
ftynse added a comment to D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.

Alex, Thanks for this! It will definitely make things simpler! However, it's going to conflict with D72802. Could we wait for that diff to land and see what else is needed here to keep everything?

Fri, Jan 31, 1:21 PM · Restricted Project
ftynse created D73795: [mlir] Drop customization hooks from StandardToLLVM conversion.
Fri, Jan 31, 10:54 AM · Restricted Project
ftynse committed rG23ccc055c760: [mlir] Remove the dependency of StdToLLVM on LoopToStd (authored by ftynse).
[mlir] Remove the dependency of StdToLLVM on LoopToStd
Fri, Jan 31, 10:54 AM
ftynse committed rG9dfcddfaae50: [mlir] Linalg tiling: generate code avoding out-of-bounds accesses (authored by ftynse).
[mlir] Linalg tiling: generate code avoding out-of-bounds accesses
Fri, Jan 31, 10:45 AM